VHDL Reference Guide v1 17th May 2016 Prepared by Digitronix Nepal

June 11, 2018 | Author: Gaihre Krishna | Category: Vhdl, Electronics, Digital Electronics, Digital & Social Media, Digital Technology
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VHDL Reference Guide Prepared by Digitronix NepalVHDL Reference Guide For Beginners Table of Contents: Design and Simulation of 1. Gate 2. MUX, Encoder 3. DeMUX, Decoder 4. Half Adder 5. Full Adder 6. ALU Design (2–bit) 7. Latch , Flip-flops 8. Structural Design in VHDL: 8 bit ALU Design 9. Counter Design 10. Finite State Machine: Sequence Detector 11. File Handling in VHDL 12. Image Processing in VHDL 13. Complete flow for Implementing design in Spartan 3e FPGA 1|Page For any Queries contact : [email protected] or +977-9841078525 ALL. USE ieee. end Behavioral.ALL. end and_gate_vhd. b : in STD_LOGIC.com or +977-9841078525 . RTL View of And Gate Testbench of And Gate for Simulation LIBRARY ieee. z : out STD_LOGIC). ENTITY and_gate_tb IS 2|Page For any Queries contact : [email protected] Reference Guide Prepared by Digitronix Nepal No. use IEEE. architecture Behavioral of and_gate_vhd is --signal declaration if have begin z<= a and b.STD_LOGIC_1164. entity and_gate_vhd is Port ( a : in STD_LOGIC.std_logic_1164. 1: – And Gate and 3-bit decoder AND Gate --VHDL Program of AND Gate library IEEE. BEGIN -.VHDL Reference Guide Prepared by Digitronix Nepal END and_gate_tb. a<='0'. b<='1'.Instantiate the Unit Under Test (UUT) uut: and_gate_vhd PORT MAP ( a => a. b : IN std_logic. b<='1'. wait for 100 ns.insert stimulus here a<='0'. -. b<='0'. END. b => b. end process. signal z : std_logic. 3|Page For any Queries contact : [email protected] process stim_proc: process begin -. wait for 100 ns. a<='1'. -. END COMPONENT. ARCHITECTURE behavior OF and_gate_tb IS COMPONENT and_gate_vhd PORT( a : IN std_logic. --Inputs signal a : std_logic := '0'. a<='1'. wait for 100 ns. wait for 100 ns. b<='0'. wait for 100 ns. z : OUT std_logic ). signal b : std_logic := '0'. wait.hold reset state for 100 ns. z => z ).com or +977-9841078525 . VHDL Reference Guide Prepared by Digitronix Nepal Simulation Waveform of the AND Gate For More Chapters Please Subscribe with Digitronix Nepal by [email protected] or +977-9841078525 .com 4|Page For any Queries contact : digitronixnepali@gmail.


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