UAMI11086

UNIVERSIDAD AUTONOMA METROPOLITANA IZTAPALAPA DEPARTAMENTO DE INGENIERIA ELECTRICA “MEDIDOR DE POTENCIA DIGITAL” PROYECTO TERMINAL P R E S E N TA GARCÍA RÍOS PERLA ASESOR DE PROYECTO _________________________________ ING. DONACIANO JIMENEZ V. 1-ANTECEDENTES 2-OBJETIVOS 2.1 Objetivo general 2.2 Objetivos Particulares 3-METODOLOGÏA 3.1 Diseño general del medidor de potencia 3.2 Componentes básicos del medidor de potencia 3.2.1 Convertidor A/D 3.2.2 Resistencia de carga 3.2.3 Atenuador 3.2.4 Convertidor de CA a CD 4-RESULTADOS Y DISCUSIÓN 5- CONCLUSIONES 6-ANEXO 7-REFERENCIAS MEDIDOR DE POTENCIA DIGITAL 1- ANTECEDENTES En los hospitales como parte del equipo de cirugía se cuenta con unidades de electrocirugía. Estos dispositivos son conocidos como electrocauterio, su uso es una practica común para el cirujano, en vez de bisturí convencional, para la creación de incisiones. Los instrumentos electocirugía dividen el tejido mediante la energía creada por una corriente alterna de alta frecuencia. Esta frecuencia incrementa la temperatura tisular con la punta del instrumento para lesionar y seccionar la membrana celular. Dependiendo de onda empleada, la corriente puede ser usada para seccionar tejido o para coagular vasos sanguíneos. Dado que la corriente pasa a través del cuerpo es importante que se tenga un control estricto de la potencia que incide en él, de no hacerlo se corre el riesgo que el equipo no este funcionando correctamente y se le aplique más corriente de la necesaria el paciente produciéndole quemaduras de grado significativo. La potencia instantánea es el ritmo al que un elemento absorbe energía, y varía como función del tiempo. Esta definida como la corriente por el voltaje que pasa por el cuerpo, para realizar esta medición es necesario contar con el equipo adecuado, el costo comercial de dicho equipo es alto.[1,2,3] El presente proyecto presenta una alternativa de bajo costo para medir la potencia de dispositivos con las características de los electrocauterios. 2-OBJETIVOS 2.1 Objetivo general Diseñar e implementar un dispositivo que se capaz de medir la potencia electrica en forma digital. 2.2 Objetivos Particulares • • • Implementar el medidor potencia propuesto para el Valleylab E3000 (SurgiStat Electrosurgical Generator). Utilizar el ICL 7107 en su aplicación medidor de voltaje. Diseñar un transformador que disminuya la corriente del primario y proporcione un valor en el secundario que refleje la potencia. 3-METODOLOGÏA 3.1 Diseño general del medidor de potencia Para la realización del diseño de medidor se potencia se toma como base la propuesta mostrada en el manual de servicio Valleylab E3000 (SurgiStat Electrosurgical Generator) . El diagrama se muestra en la figura 1. Esta formado por la resistencia de carga de 500 a 50 W, un medidor de corriente a radio frecuencia y un seleccionador de escala para mediciones de 0 –125 W y de 0 – 500 W. La medición de la potencia se realiza de forma indirecta, leyendo en el galvanometro la medición de la corriente con un calculo simple se obtiene la potencia, a continuación se muestra matemáticamente en la ecuación 1[3]. P = V²/ R (1) Donde: P = Potencia V = Voltaje R = Resistencia Figura 1 En la figura 2 se muestra el diagrama a bloques del diseño modificado de la figura 1. para su implementación en forma digital. La primera etapa es el acondicionamiento de la señal está formada por la resistencia de carga, el atenuador y el convertidor de AC a DC. La segunda etapa es la conversión A/D y el despliegue. Instrumento Corriente o voltaje a medir Despliegue Convertidor A/D Señal en CC Resistencia de carga Señal en CA Atenuador Señal preescalada Convertidor de AC a DC Figura 2 El instrumento es el dispositivo al que se le va a medir la potencia, se conecta en serie con la resistencia de carga y con el primario del transformador, este arreglo permite disminuir la corriente que viene del instrumento o dispositivo que se esta midiendo . La parte del secundario va conectada a la entrada del circuito Convertidor de AC a DC del cual se obtiene un voltaje el DC que representa el valor de la potencia eléctrica del dispositivo, El voltaje entra al convertidor analogico/digital y el nivel de voltaje se muestra en los displays. La figura 2 se explica con más detalle en la siguiente sección. 3.2 Componentes básicos del medidor de potencia 3.2.1 Convertidor A/D Como la medición de la potencia es de forma digital necesitamos un dispositivo que nos convierta la medición de analógica a digital. El Convertidor A/D de 3 ½ dígitos sus aplicaciones más comunes son voltímetros y amperímetros digitales. En el diseño de este voltímetro digital se presenta el convertidor A/D CMOS ICL 7107. El diagrama de terminales para este circuito integrado se muestra en la figura 3. El ICL7107 alimenta un despliegue de diodos emisor de luz (LED). Se incluyen descodificadores de 7 segmentos, alimentadores de despliegue, referencias y un reloj. El circuito integrado opera en tres fases: 1) regreso automático a cero, 2) integración de la señal y 3) integración de la referencia. En la fase 1 de la conversión de doble pendiente, el ciclo se lleva a cero para empezar nuevamente. Este proceso se conoce como fase de regreso automático a cero. En la fase dos del método de doble pendiente, la señal se integra durante un tiempo fijo con una pendiente que depende de la combinación RC del amplificador operacional de integración. En la fase 3, la entrada del integrador se conmuta de Vi a Vref. La polaridad se determina durante la fase 2 de modo que el integrador se descargue hacia cero. El número de pulsos de reloj que se cuentan entre el inicio de este ciclo (fase 3) y el momento en que la salida del integrador pasa por cero es una medida digital de la magnitud de Vi. El potencial de alimentación del integrado se aplica a los pines 1 y 21, siendo de +5V y -5V respectivamente, respecto a tierra. Se requiere de 4 unidades de display siete segmentos, ánodo común para mostrar la medición con tres cifras signada y otro display del mismo tipo para indicar que la medición está fuera del rango de la escala. Los pines del 2 al 8 manejan el display que muestra las unidades de la cifra, los pines del 9 al 14 manejan el display que muestra las decenas y los pines de 15 al 18 y del 22 al 25 manejan el display que muestra las centenas. Con el pin 20 se maneja el display que muestra el signo negativo y con el pin 19 se maneja el display que indica el sobre rango. El pin 32 (COM) actúa como tierra flotante para los voltajes de entrada y de referencia. El voltaje que se quiere medir se coloca entre los pines 31 y 30, es capas de medir hasta 2 V , observándose en los displays hasta 1.999 V . Los pines 38 (OSC3), 39 (OSC2) y 40 (OSC1) proporcionan acceso al reloj interno. La frecuencia de oscilación se determina con la ecuación 2: Fosc = 0.45 / (R5 C5) (2) Internamente esta frecuencia se divide entre cuatro para obtener los pulsos utilizados por el contador y la circuitería de control lógico durante cada ciclo de medida. Con el pin 37 (TEST) se comprueba la correcta conexión de los displays. La presición de la medición depende de la exactitud componentes con los que es construido. de los Figura 3 Donde: R1 = 470 KΩ R2 = 1MΩ R3 potenciómetro de 25 KΩ R4 = 24KΩ R5 = 100KΩ C1 = 0.22µF C2 = 0.047µF C3 = 0.01µF C4 = 0.1µF C5 = 100pF 3.2.2 Resistencia de carga La resistencia de carga representa la impedancia que presenta el cuerpo al pasar la corriente a través de él, de la punta activa a la placa de paciente del electrocauterio, dicha impedancia es considerada de 500 Ω (el valor considera la impedancia de la placa de paciente)[1,3]. En la figura 1 se muestra el arreglo de resistencias propuesto, esta formado por 4 resistencias de 250 Ω a 50 W en paralelo con 4 del mismo valor, debido a problemas por los valores comerciales se utilizan 8 juegos de resistencias en paralelo de 470 Ω a 25 W y 2 juegos de resistencias de 120 Ω a 25 W, se obtiene una resistencia equivalente de 500 Ω. Se utilizan resistencias de potencia debido a que la los niveles corriente que manejan los electrocauterios es alto. 3.2.3 Atenuador El atenuador no es más que un transformador de núcleo de ferrita. La función de todo tipo de transformador consiste en transformar o cambiar la electricidad de alguna manera. Un transformador básico consta de dos bobinas enrolladas sobre el mismo núcleo de hierro, el cual forma un circuito magnético cerrado. El transformador no funciona con corriente continua es necesario suministrar corriente alterna o corriente continua pulsátil. En el devanado, al que se le suministra energía se le denomina primario, y al devanado del cual se toma la energía se llama secundario. Cualquier cambio en la corriente del primario produce un cambio en el flujo que enlaza el devanado secundario inducirá un voltaje en las terminales del secundario. Si el voltaje en el secundario es el mismo que el voltaje del primario, al trasformador se le denomina transformador uno a uno, si el voltaje del secundario es mayor que el del primario, éste será un transformador elevador, y cuando el voltaje del secundario es menor que el voltaje del primario, éste será un transformador reductor. La potencia suministrada al primario, con una frecuencia específica, produce una potencia de la misma frecuencia en el secundario[2]. Las relaciones de corriente en un transformador son: Ep/Es = Is/Ip Donde: (3) Ep = voltaje aplicado en el primario Es = voltaje en el secundario Ip = corriente en el primario Is = corriente en el secundario Las relaciones de voltaje en un transformador son: Ep/Es = Np/Ns Donde: (3) Ep = voltaje aplicado en el primario Es = voltaje en el secundario Np = número de vueltas en el primario Ns = número de vueltas en el secundario Con base en lo anterior el tipo de transformador que se requiere en este proyecto es un transformador elevador, con el embobinado primario de 4 vueltas de alambre magneto con calibre 11 para que no existan perdidas de voltaje en la señal de entrada, el embobinado secundario son 7 vueltas las suficientes para que el voltaje en el secundario represente la potencia eléctrica en la resistencia de carga. 3.2.4 Convertidor de CA a CD Figura 4 En convertidor de CA a CD es parte del acondicionamiento de la señal, normaliza la entrada a un voltaje de corriente continua. La figura 4 muestra el circuito utilizado, a la entrada no inversora del AOP entra el voltaje del secundario del transformador, dicho voltaje es de corriente alterna a la salida obtenemos un voltaje en corriente continua. La polarización del TL081 es de +5 V y –5 V. 4-RESULTADOS Y DISCUSIÓN Tabla 1: Resultados obtenidos a diferentes frecuencias y resultados teoricos Vrms (V) W54kHz W100kHz W147kHz W199kHz Wteo (m watts) (m watts) (m watts) (m watts) (m watts) 7.07 6.03 5.03 4.03 3.01 53 44 36 28 18 98 80 64 48 32 141 118 95 71 47 190 156 123 92 62 99 72 50 32 18 Para realizar estas mediciones se utiliza un generador de funciones por no contar con un electrocoagulador. La tabla 1 muestra los resultados experimentales, estos valores se obtuvieron directamente del despliegue del convertidor A/D. Se fijaron 4 diferentes valores de frecuencias y se tomaron 5 valores diferentes de voltaje, la ultima columna son los resultados teoricos obtenidos con la ecuación 1. De la tabla podemos observar que 100 Hz es la frecuencia en que los valores de potencia son muy aproximados, a frecuencias menores los valores disminuyen y en el caso contrario aumentan, esto se debe al ancho de banda del medidor de potencia. También se observa los valores obtenidos son pequeños por limitaciones propias del generador de funciones. En el Anexo se muestran ilustraciones del circuito funcionando. 5-CONCLUSIONES Se ha presentado el diseño de un medidor de potencia digital como una alternativa de bajo costo, para la realizar mantenimiento preventivo a unidades de electrocirugia en hospitales que no cuenten con los recursos para adquirir uno comercial. El dispositivo es capaz de mostrar la potencia eléctrica de un instrumento o dispositivo de su voltaje o corriente de salida del mismo. El dispositivo tiene un rango de medición limitado de 0 W a 2 W,como sugerencia para mejorar al diseño anterior se puede aumentar el rango de medición con el diagrama de la figura 5, es un circuito de auto rango, con el cual podemos realizar mediciones de 0 W a 200W sin necesidad de seleccionar las escalas de manera manual. Figura 5 7-REFERENCIAS [1] [2] [3] Medical Instrumentation, Aplication and Design, Webster, Editorial Houghton Mifflin, Segunda Edición. Electrónica Moderna para ingenieros y técnicos, Milton Kaufman, Editorial Mc Graw Hill, Segunda Edición. Manual de servicio Valleylab E3000 (SurgiStat Electrosurgical Generator) . Building a Battery Operated Auto Ranging DVM with the ICL7106 Application Note AN046 Larry Goff Introduction In the ﬁeld of DVM design, three areas are being addressed with vigor: size, power dissipation, and novelty. The handheld portable multimeter has gained in popularity since low power dissipation devices enabled battery operation, LSI A/D converters reduced IC count, and novelties such as conductance, automatic range scaling, and calculating were included to entice the user. This application note describes a technique for auto-ranging a battery operated DVM suitable for panel meter applications. Also, circuit ideas will be presented for conductance and resistance measurement, 9V battery and 5V supply operations, and current measurement. Input Divider Network A simpliﬁed drawing of the divider network is shown in Figure 2. This conﬁguration was chosen for simplicity and implementation using analog switches. The low leakage ID101s are used for input protection, and the second set of switches to IN LO reduces the net error due to switch resistance. This can be seen calculating IN HI and IN LO voltages for the two equivalent circuits. For equivalent circuit A,  RS + R ⁄ K  V MEAS = V IN HI =  ------------------------------------  V IN  R S + R + R ⁄ K (EQ. 1) Auto Ranging Circuitry The control signals necessary for auto-ranging are overrange, under-range, and clock. The over-range and underrange inputs control the direction of a scale shift, becoming active at the completion of an invalid conversion and remaining active until a valid conversion occurs. The clock input controls the timing of a scale shift. This signal should occur only once per conversion cycle, during a time window which will not upset an ongoing conversion and must be disabled after valid conversions. In the circuit of Figure 1, inverted over-range (O/R) and under-range (U/R) are generated by detecting the display reading. The ICL7106 turns the most signiﬁcant digit on and blanks the rest to indicate an over-range. An under-range occurs if the display reads less than 0100. R1C1 and R2C2 are required to deglitch O/R and U/R. The next step in the logic disables O/R and U/R prior to shifting into nonexistent ranges. O/R is disabled when in the 200V range, while U/R is disabled when in the 200mV range. The next level of gating disables the clock if the conditions are as described above and a valid conversion state exists. Clock is enabled only when a range shift is called for and there exists a valid range to shift into. The CD4029 is a four bit up/down counter, used as a register to hold the present state and as a counter to shift the scale as directed by the control inputs. The CD4028 is a BCD to decimal decoder interfacing the CD4029 and ladder switches. An additional exclusive OR gate package is added to drive the appropriate decimal point. where RS = switch resistance, R = input resistance (1MΩ), and 1 + K is the desired divider ratio. Ideally VINHI should be R⁄K 1 V IDEAL =  ---------------------- V IN =  ------------  V IN  R ⁄ K + R  1 + K (EQ. 2) Therefore the percent error is: Ideal – Actual --------------------------------------- 100, Ideal R S + R/K   or  1 – ( 1 + K ) ----------------------------------  100 R S + R/K + R  (EQ. 3) (EQ. 4) The worst case error occurs at (1+K) = 1000. For this example, the error due to a 1kW switch resistance is 99.7%. IN HI for equivalent circuit B is the same as Equation 1. However, IN LO for circuit B is: RS    ------------------------------------  V IN ,  R S + R + R ⁄ K (EQ. 5) and combining Equations (1) and (5) R⁄K V MEAS = V INHI – V INLO =  ------------------------------------  V IN  R + R + R ⁄ K S (EQ. 6) The percent error is equal to: R/K  1 – ( 1 + K ) ----------------------------------  100  R + R + R/K S (EQ. 7) Using the same values for RS, (1+K), and R, the worst case error is 0.1%. This error can be further improved if lower rDS(ON) switches are used. From the results calculated above, the worst case conversion error due to switch resistance will be one count of the least signiﬁcant digit for a full scale input, and a slight adjustment to R itself will correct the remaining error on all scales. 1 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 V+ 1 2 V+ 3 4 5 6 7 ICL7106 PIN26 V8 9 V+ D1 C1 B1 A1 F1 G1 E1 D2 OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF CREF COMMON IN HI IN LO A-Z BUFF INT VG2 C3 A3 G3 BP 40 39 38 100pF CLOCK A/Z CREF 100kΩ 37 DIG GND 36 35 1µF 34 24kΩ 33 32 31 30 29 28 27 26 25 24 23 22 21 V0.47µF 47kΩ 3N169 N CH. 0.01µF 47MΩ R8 5.1kΩ D1 Q2 D S D Q1 S 20kΩ 22kΩ 1kΩ C3 0.1µF 2 D 3 1 10 4011 3 13 12 4011 11 4011 1 2 4011 6 4 A 8 9 74C32 5 2 C1 R1 TEST TEST 1 2 3 4 CD4029BC 5 6 7 8 V C1 10 C2 11 B2 12 A2 13 F2 14 E2 10kΩ 6 O/RANGE 3 4 4023 3 11 4 12 13 10 2 1 5 6 8 9 12 11 13 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL 2N3702 Q3 100kΩ 1MΩ D2 0.22µF Application Note 046 TEST 4023 5 10 0.005µF TEST O/RANGE 1 10kΩ 2 8 R2 9 4023 C2 0.005µF VIN C ID101 V+ PE V+ 16 CLK 15 14 13 12 Q7 11 UP/DOWN 10 BINARY 9 DECODE 1 2 3 4 CD402T 5 6 7 8 V C 12 D 11 A A 10 9 BACK PLANE DECODER ARROW 1 2 B 5 C 6 8 9 12 A OR D 13 5, 13 12 TEST UP/DOWN COUNTER 8 6 CD4016 TEST 2 O V+ 16 3 15 1 14 B 13 6, 12 1 2 B A V+ D 13, 5 4 8 CD4016 9 R1 R2 R3 1.001kΩ 3 R4 R6 VIN 1MΩ 10.1kΩ 10 11 R5 3 4 111.1kΩ Q1 10 11 9 OPEN OPEN FIGURE 1. AUTO RANGING CIRCUITRY Application Note 046 R IN HI ID101 VIN IN LO R/999 R/99.01 R/9 + SWITCH CONTROL LINES 200V 20V 2V 200mV FIGURE 2A. + R TO IN HI VIN R/K VMEAS R SWITCH + R TO IN HI VIN R/K VMEAS TO IN LO R SWITCH TO IN LO - - FIGURE 2B. EQUIVALENT CIRCUIT A (SWITCHES TO IN LO REMOVED) FIGURE 2C. EQUIVALENT CIRCUIT B (SWITCHES TO IN LO INCLUDED) FIGURE 2. INPUT DIVIDER NETWORK Ranging Clock Circuit Two N-Channel MOSFETs, a PNP transistor and a handful of passive components combine to generate the clock signal used to gate the auto-ranging logic. A closer look at the inner workings of the ICL7106 will help clarify the discussion of this circuit. The analog section of the ICL7106 is shown in Figure 3. It can be shown that CREF low (pin 33 of ICL7106) will sit at -VREF for DE+ and at common for DE-, with DE+ designating the deintegrate phase for a positive input signal and DE- referring to a negative input signal. During the autozero phase, CREF low is tied to an external reference through pin 35, which in Figure 1 is VREF below the positive supply. The net result is that CREF low is above COMMON during auto-zero, is left to ﬂoat during signal integrate, and is at or below COMMON during deintegrate. R8 and D1 are added externally to pull CREF to COMMON during integrate, with Q2 and R1 included to speed this action. The signal at CREF low is now a square wave that is high during auto-zero and low at all other times. Q1 and Q3 amplify and level shift this waveform for logic level compatibility. This clock signal is gated through D2 and controls the timing of the auto-ranging circuitry. C3 is added to delay the clock, eliminating disparity with O/R and U/R (see Figure 4 for timing diagram). 3 Application Note 046 CREF RINT CREF+ V+ 34 REF HI 36 A-Z 10µA 31 IN HI INT DEDE+ INPUT HIGH 6.2V A-Z 2.8V REF LO 35 A-Z CREF 33 BUFFER 28 V+ 1 29 INTEGRATOR + CAZ A-Z CINT INT 27 + - - + - TO DIGITAL SECTION A-Z N 32 COMMON INT 30 IN LO 26 VA-Z AND DE(±) INPUT LOW DE+ DE+ - COMPARATOR FIGURE 3. ANALOG SECTION OF ICL7106 INTEGRATOR A/Z OVER-RANGE CONVERSION A/Z VALID CONVERSION A/Z CREF LOW (PIN 33) CLOCK O/R, U/R FIGURE 4. TIMING DIAGRAM Supply Requirements The circuit of Figure 1 operates on a standard 9V transistor battery. CMOS logic and a CMOS A/D converter (ICL7106) are used to extend battery life; the approximate power drain for this circuit is 8mW. The circuit in Figure 5 can also be added to detect low supply voltage. The circuit of Figure 6 can be used to generate ±5V from a single 5V supply. The ICL7660 is a voltage converter which takes a 5V input and produces a -5V output. With respect to common mode signals, the circuit of Figure 1 will have inﬁnite common mode handling capability if operated from a ﬂoating 9V battery. However, if powered by a ﬁxed supply such as in Figure 6, the common mode capability of the converter will be limited to approximately ±2V, if COMMON is disconnected from -VIN. 4 Application Note 046 For transconductance measurement, merely switch RSTD and RX. This scheme makes the measurement of large resistors, in conductance form, convenient and easy. This is also convenient for leakage measurements. A simple current meter can be built using the circuit of Figure 8. The low leakage of the ICL7106 (10pA/max) makes possible the measurement of currents in the mid pico-Amp range. However, the switch leakage current will limit the accuracy of the resistor network and may degrade converter resolution. 1MΩ 1 2 3 4 FIG 7 180K TO DISPLAY INDICATOR BACKPLANE TEST ICL8211 8 7 6 5 1MΩ FIGURE 5. LOW VOLTAGE DETECTOR +5V NC 1 2 + 10µF ICL7660 3 4 6 NC 5 10µF -5V R 8 7 NC 90R AUTO-RANGING DVM CIRCUIT IIN 9R IN LO ICL7106 900R IN HI - FIGURE 6. GENERATING ±5V FROM +5V Resistance, Transconductance and Current Circuits The purpose of this section is to show the simplicity of measuring transconductance (1/R) and resistance with the ICL7106. The circuit of Figure 7 requires only one precision resistor per decade range of interest. The conversion output is described by the formula:  RX   --------------- 1000  R STD V+ FIGURE 8. CURRENT METER Using the ICL7126 and ICL7107 With a few modiﬁcations, the circuit of Figure 1 can easily be adapted for use with either the low power ICL7126 or the ICL7107. Using the ICL7126 simply requires a change in the values of the integrating and auto-zero components. Refer to the ICL7126 data sheet for details. The ICL7107 is an LED version of the ICL7106, and is a bit trickier to use in this application. First the over-range/underrange logic must be changed slightly. Simply replace the quad exclusive-NOR with an LM339; connect the outputs, as before, to the CD4023 triple 3-input NAND. Second, the ICL7107 requires +5V and -5V rather than the +9V battery used in Figure 1. If battery operation is desired, the negative supply can be derived from 4 Ni-Cad cells in series and an ICL7660 (see Figure 9). Note that both supplies ﬂoat with respect to the input terminals. (Logic supplies are V+ and DIG. GND.) (EQ. 8) REF HI RSTD REF LO IN914 or IN4148 X4 ICL7106 IN HI RX IN LO COMMON FIGURE 7. TRANSCONDUCTANCE AND RESISTANCE MEASUREMENT 5 Application Note 046 ICL7107 +5V ICL7660 1 2 + 10µF 3 4 8 7 6 5 + 10µF -5V 12kΩ 1 V3 2 D1 3 C1 4 B1 5 A1 6 F1 7 G1 8 E1 9 D2 10 C2 11 B2 12 A2 13 F2 + 14 E2 15 D3 16 B3 + U /RANGE + 17 F3 18 E3 19 AB4 20 POL CD4023 OR 74C10 + LM339 33kΩ OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 GND 21 NEGATIVE (0V) LOGIC SUPPLY -5V O /RANGE FIGURE 9. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUTS. THE LM339 IS REQUIRED TO ENSURE LOGIC COMPATIBILITY WITH HEAVY DISPLAY LOADING All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Ofﬁce Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: ( 321) 724-7000 FAX: ( 321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6 S E M I C O N D U C T O R ICL7106, ICL7107 31/2 Digit LCD/LED Display A/D Converter Description The Harris ICL7106 and ICL7107 are high performance, low power 31/2 digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED) display. The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10µV, zero drift of less than 1µV/οC, input bias current of 10pA max., and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. January 1994 Features • Guaranteed Zero Reading for 0V Input on All Scales • True Polarity at Zero for Precise Null Detection • 1pA Typical Input Current • True Differential Input and Reference, Direct Display Drive - LCD ICL7106 - LED lCL7l07 • Low Noise - Less Than 15µVp-p • On Chip Clock and Reference • Low Power Dissipation - Typically Less Than 10mW • No Additional Active Circuits Required • New Small Outline Surface Mount Package Available Ordering Information PART NUMBER ICL7106CPL ICL7106RCPL ICL7106CM44 ICL7107CPL ICL7107RCPL ICL7107CM44 TEMPERATURE RANGE 0oC to +70oC 0oC to +70oC 0oC to +70oC 0 C to +70 C 0oC to +70oC 0 C to +70 C o o o o PACKAGE 40 Lead Plastic DIP 40 Lead Plastic DIP (Note 1) 44 Lead Metric Plastic Quad Flatpack 40 Lead Plastic DIP 40 Lead Plastic DIP (Note 1) 44 Lead Metric Plastic Quad Flatpack NOTE: 1. “R” indicates device with reversed leads. Pinouts ICL7106, ICL7107 (PDIP) TOP VIEW REF LO REF HI CREF+ V+ D1 C1 B1 (1’s) A1 F1 G1 E1 D2 C2 (10’s) B2 A2 F2 E2 D3 (100’s) B3 F3 E3 (1000) AB4 (MINUS) POL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 OSC 1 39 OSC 2 38 OSC 3 37 TEST 36 REF HI 35 REF LO 34 CREF+ 33 CREF32 COMMON 31 IN HI 30 IN LO 29 A-Z 28 BUFF 27 INT 26 V25 G2 (10’s) 24 C3 23 A3 22 G3 21 BP/GND A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 (100’s) NC NC TEST OSC 3 NC OSC 2 OSC 1 V+ D1 C1 B1 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 NC G2 C3 A3 G3 BP/GND POL AB4 E3 F3 B3 ICL7106, ICL7107 (MQFP) TOP VIEW COMMON CREFIN LO BUFF IN HI A-Z INT 11 23 12 13 14 15 16 17 18 19 20 21 22 V- CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1993 File Number 3082 2-33 Speciﬁcations ICL7106, ICL7107 Absolute Maximum Ratings Supply Voltage ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V ICL7107, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V ICL7107, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+ Thermal Information Thermal Resistance (MAX, See Note 1) θJA 40 Pin Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . 50oC/W 44 Pin MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W Maximum Power Dissipation ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2W Operating Temperature Range . . . . . . . . . . . . . . . . . . 0oC to +70oC Storage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s Max) . . . . . . . . . . . . . . . . +265oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. Electrical Speciﬁcations (Note 3) PARAMETERS SYSTEM PERFORMANCE Zero Input Reading VIN = 0.0V, Full-Scale = 200mV VlN = VREF, VREF = 100mV -VIN = +VlN ≅ 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full-Scale Full-Scale = 200mV or Full-Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) VCM = 1V, VIN = 0V, Full-Scale = 200mV (Note 5) VIN = 0V, Full-Scale = 200mV (Pk-Pk Value Not Exceeded 95% of Time) VlN = 0 (Note 5) VlN = 0, 0 < TA < +70 C (Note 5) VIN = 199mV, 0o < TA < +70oC, (Ext. Ref. 0ppm/oC) (Note 5) o o TEST CONDITIONS MIN TYP MAX UNIT -000.0 ±000.0 999/ 1000 ±0.2 +000.0 Digital Reading Digital Reading Counts Ratiometric Reading 999 1000 ±1 Rollover Error - Linearity - ±0.2 50 15 ±1 - Counts µV/V µV pA µV/oC ppm/oC Common Mode Rejection Ratio Noise - Leakage Current Input Zero Reading Drift Scale Factor Temperature Coefficient - 1 0.2 1 10 1 5 End Power Supply Character V+ Supply Cur- VIN = 0 (Does Not Include LED Current for ICL7107) rent End Power Supply Character V- Supply Current ICL7107 Only COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With Respect to + Supply) 25kΩ Between Common and Positive Supply (With Respect to + Supply) - 0.8 1.8 mA 2.4 0.6 2.8 1.8 3.2 mA V ppm/oC Temperature Coefficient of Analog Common - 80 - DISPLAY DRIVER ICL7106 ONLY Pk-Pk Segment Drive Voltage Pk-Pk Backplane Drive Voltage V+= to V- = 9V, (Note 4) 4 5 6 V 2-34 ICL7106, ICL7107 Electrical Speciﬁcations (Note 3) (Continued) PARAMETERS ICL7107 ONLY Segment Sinking Current (Except Pin 19 and 20) Pin 19 Only Pin 20 Only V+ = 5V, Segment Voltage = 3V 5 10 4 8 16 7 mA mA mA TEST CONDITIONS MIN TYP MAX UNIT NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at TA = +25oC, fCLOCK = 48kHz. ICL7106 is tested in the circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2. 4. Back plane drive is in phase with segment drive for ‘off’ segment, 180o out of phase for ‘on’ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. Typical Applications and Test Circuits + IN R1 R3 OSC 1 40 OSC 2 39 OSC 3 38 C4 TEST 37 R4 C1 R5 C5 C2 R2 C3 DISPLAY 9V ICL7106 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULLSCALE +5V R5 C1 C5 C2 R2 C3 DISPLAY + IN R1 R3 OSC 1 40 OSC 2 39 OSC 3 38 C4 TEST 37 R4 -5V BP 21 ICL7107 20 POL 19 AB4 G1 D1 C1 B1 A1 D2 10 C2 11 B2 12 A2 15 D3 16 B3 V+ E1 14 E2 18 E3 F1 13 F2 17 F3 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ REF HI 36 REF LO 35 CREF+ 34 CREF- 33 COM 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 1 2 3 4 5 6 7 8 9 DISPLAY FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULLSCALE 2-35 GND 21 ICL7106, ICL7107 Design Information Summary Sheet • OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50KΩ fOSC Typ. = 48KHz • OSCILLATOR PERIOD tOSC = RC/0.45 • INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC/4 • INTEGRATION PERIOD tINT = 1000 x (4/fOSC) • 60/50Hz REJECTION CRITERION tINT/t60Hz or tlNT/t60Hz = Integer • OPTIMUM INTEGRATION CURRENT IINT = 4.0µA • FULL-SCALE ANALOG INPUT VOLTAGE VlNFS Typically = 200mV or 2.0V • INTEGRATE RESISTOR V INFS R = INT I INT • INTEGRATE CAPACITOR (t ) (I ) INT INT C = INT V INT • INTEGRATOR OUTPUT VOLTAGE SWING (t ) (I ) INT INT V = INT C INT • VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT typically = 2.0V • DISPLAY COUNT COUNT = 1000 × V V IN REF • CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48KHz; tCYC = 333ms • COMMON MODE INPUT VOLTAGE (V- + 1.0V) < VlN < (V+ - 0.5V) • AUTO-ZERO CAPACITOR 0.01µF < CAZ < 1.0µF • REFERENCE CAPACITOR 0.1µF < CREF < 1.0µF • VCOM Biased between Vi and V-. • VCOM ≅ V+ - 2.8V Regulation lost when V+ to V- < ≅6.8V. If VCOM is externally pulled down to (V + to V -)/2, the VCOM circuit will turn off. • ICL7106 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VGND ≅ V+ - 4.5V • ICL7106 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. • ICL7107 POWER SUPPLY: DUAL ±5.0V V+ = +5.0V to GND V- = -5.0V to GND Digital Logic and LED driver supply V+ to GND • ICL7107 DISPLAY: LED Type: Non-Multiplexed Common Anode Typical Integrator Ampliﬁer Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 2-36 ICL7106, ICL7107 Detailed Description Analog Section Figure 3 shows the Analog Section for the ICL7106 and ICL7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer ampliﬁer, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a ﬁxed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. De-Integrate Phase The ﬁnal phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Speciﬁcally the digital reading displayed is: DISPLAYCOUNT = 1000 V  IN  .  V REF  Differential Input The input can accept differential voltages anywhere within the common mode range of the input ampliﬁer, or speciﬁcally from 0.5V below the positive supply to 1.0V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V fullscale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. STRAY CREF STRAY RINT CAZ A-Z 29 INTEGRATOR + CINT INT 27 CREF V+ + REF HI 36 A-Z REF LO 35 A-Z CREF 33 BUFFER V+ 28 1 34 + - 10µA 31 IN HI INT DEDE+ INPUT HIGH 6.2V 2.8V - + - TO DIGITAL SECTION A-Z A-Z N 32 COMMON INT 30 IN LO VA-Z AND DE(±) INPUT LOW DE+ DE+ - COMPARATOR FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107 2-37 ICL7106, ICL7107 Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) Analog COMMON This pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are ﬂoating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefﬁcient (0.001%/V), low output impedance (≅15Ω), and a temperature coefﬁcient typically less than 80ppm/oC. The limitations of the on chip reference should also be recognized, however. With the ICL7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefﬁcient (TC), internal chip dissipation, and package thermal resistance can increase noise near full-scale from 25µV to 80µVp-p. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least signiﬁcant digits blanked. Similarly, units with a negative TC may cycle between over-range and a non-overrange count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. The ICL7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a ﬁxed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. V+ V REF HI REF LO 6.8V ZENER IZ ICL7106 ICL7107 V- FIGURE 4A. V+ V ICL7106 ICL7107 REF HI REF LO COMMON 20kΩ 6.8kΩ ICL8069 1.2V REFERENCE FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. On the ICL7106 it is coupled to the internally generated digital supply through a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied. V+ 1MΩ TO LCD DECIMAL POINT ICL7106 BP TEST 21 37 TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT 2-38 ICL7106, ICL7107 The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “1888”. The TEST pin will sink about 15mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave). This may burn the LCD display if maintained for extended periods. Digital Section Figures 7 and 8 show the digital section for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large Pchannel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. Figure 8 is the Digital Section of the ICL7107. It is identical to the ICL7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. V+ V+ BP ICL7106 DECIMAL POINT SELECT TO LCD DECIMAL POINTS TEST CD4030 GND FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE a a b f g e d c b c f a b g e d c e f a b g c d 21 BACKPLANE LCD PHASE DRIVER 7 SEGMENT DECODE 7 SEGMENT DECODE 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 0.5mA SEGMENT OUTPUT 2.0mA 1000’s COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK † ÷200 LATCH 100’s COUNTER 10’s COUNTER 1’s COUNTER 1 V+ ÷4 INTERNAL DIGITAL GROUND LOGIC CONTROL 6.2V 500Ω † THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY TEST VTH = 1V 37 26 40 OSC 1 OSC 2 39 OSC 3 38 V- FIGURE 7. ICL7106 DIGITAL SECTION 2-39 ICL7106, ICL7107 a a b f g e d c b c f g e d c e d a b f g c a b 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 0.5mA TO SEGMENT 8.0mA DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT V+ † † THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY 40 OSC 1 OSC 2 39 OSC 3 38 CLOCK ÷4 1000’s COUNTER 100’s COUNTER 7 SEGMENT DECODE 7 SEGMENT DECODE LATCH 10’s COUNTER 1’s COUNTER 1 V+ LOGIC CONTROL 500Ω 27 DIGITAL GROUND 37 TEST FIGURE 8. ICL7107 DIGITAL SECTION System Timing Figure 9 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used: 1. An external oscillator connected to pin 40. 2. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and autozero (1000 to 3000 counts). For signals less than full-scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). 40 39 38 INTERNAL TO PART ÷4 CLOCK GND ICL7107 TEST ICL7106 INTERNAL TO PART ÷4 CLOCK 40 39 R 38 C RC OSCILLATOR FIGURE 9. CLOCK CIRCUITS 2-40 ICL7106, ICL7107 Component Value Selection Integrating Resistor Both the buffer ampliﬁer and the integrator have a class A output stage with 100µA of quiescent current. They can supply 4µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full-scale, 470kΩ is near optimum and similarly a 47kΩ for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the ICL7106 or the ICL7107, when the analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is ﬁne. For the ICL7107 with +5V supplies and analog COMMON tied to supply ground, a ±3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.22µF and 0.10µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor The size of the auto-zero capacitor has some inﬂuence on the noise of the system. For 200mV full-scale where noise is very important, a 0.47µF capacitor is recommended. On the 2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Capacitor A 0.1µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e. the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1.0µF will hold the roll-over error to 0.5 count in this instance. Oscillator Components ICL7107 Reference Voltage The analog input required to generate full-scale output (2000 counts) is: VlN = 2VREF . Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full-scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 1 20kΩ and 0.22µF. This makes the system slightly quieter and also avoids a divider network on the input. The ICL7107 with ±5V supplies can accept input signals up to ±4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN ≠ 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or ﬁxed) offset voltage between COMMON and IN LO. ICL7107 Power Supplies The ICL7107 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive l.C. Figure 10 shows this application. See ICL7660 data sheet for an alternative. In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than ±1.5V. 3. An external reference is used. V+ CD4009 V+ OSC 1 OSC 2 OSC 3 IN914 + 10 µF - 0.047 µF IN914 For all ranges of frequency a 100kΩ resistor is recommended and the capacitor is selected from the equation 0.45 For48kHzClock(3Readings/second), f = RC C = 100pF GND V- V- = 3.3V FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V 2-41 ICL7106, ICL7107 Typical Applications The ICL7106 and ICL7107 may be used in a wide variety of conﬁgurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Harris semiconductor. Application Notes A016 “Selecting A/D Converters” A017 “The Integrating A/D Converter” A018 “Do’s and Don’ts of Applying A/D Converters” A023 “Low Cost Digital Panel Meter Designs” A032 “Understanding the Auto-Zero and Common Mode Performance of the ICL7106/7/9 Family” A046 “Building a Battery-Operated Auto Ranging DVM with the ICL7106” A052 “Tips for Using Single Chip 31/2 Digit A/D Converters” Typical Applications TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP 21 TO BACKPLANE TO DISPLAY 0.22µF 0.01µF 0.47µF 47KΩ 9V 1KΩ 0.1µF 1MΩ + IN 22KΩ 100pF SET VREF = 100mV 100KΩ OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 1KΩ 0.1µF 1MΩ 0.01µF 0.47µF 47KΩ + IN 22KΩ +5V 100pF SET VREF = 100mV 100KΩ TO PIN 1 - IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 - 0.22µF -5V TO DISPLAY Values shown are for 200mV full-scale, 3 readings/sec., ﬂoating supply voltage (9V battery). Values shown are for 200mV full-scale, 3 readings/sec. IN LO may be tied to either COMMON for inputs ﬂoating with respect to supplies, or GND for single ended inputs. (See discussion under Analog COMMON.) FIGURE 12. ICL7107 USING THE INTERNAL REFERENCE FIGURE 11. ICL7106 USING THE INTERNAL REFERENCE 2-42 ICL7106, ICL7107 Typical Applications (Continued) TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO DISPLAY 0.22µF V0.01µF 0.47µF 47KΩ 1KΩ 0.1µF 1.2V (ICL8069) 1MΩ + IN 10KΩ 10KΩ V+ 100pF SET VREF = 100mV 100KΩ OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO DISPLAY 0.22µF -5V 0.01µF 0.47µF 47KΩ 1KΩ 0.1µF 1MΩ 100KΩ 6.8V + IN +5V 100pF SET VREF = 100mV 100KΩ TO PIN 1 - - IN LO is tied to supply COMMON establishing the correct common mode voltage. If COMMON is not shorted to GND, the input voltage may ﬂoat with respect to the power supply and COMMON acts as a pre-regulator for the reference. If COMMON is shorted to GND, the input is single ended (referred to supply GND) and the pre-regulator is overridden. FIGURE 13. ICL7107 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP/GND 21 TO DISPLAY 0.22µF V0.01µF 0.047µF 470KΩ 25KΩ 0.1µF 1MΩ + IN 24KΩ V+ 100pF SET VREF = 100mV 100KΩ Since low TC zeners have breakdown voltages ~ 6.8V, diode must be plasced across the total supply (10V). As in the case of Figure 14, IN LO may be tied to either COMMON or GND FIGURE 14. ICL7107 WITH ZENER DIODE REFERENCE TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO DISPLAY 0.22µF 0.01µF 0.47µF 47KΩ 1KΩ 0.1µF 1.2V (ICL8069) 1MΩ + IN 10KΩ 15KΩ +5V 100pF SET VREF = 100mV 100kΩ - - An external reference must be used in this application, since the voltage between V+ and V- is insufﬁcient for correct operation of the internal reference. FIGURE 15. ICL7106 AND ICL7107: RECOMMENDED COMPONENT VALUES FOR 2.0V FULL-SCALE FIGURE 16. ICL7107 OPERATED FROM SINGLE +5V 2-43 ICL7106, ICL7107 Typical Applications (Continued) TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 GND 21 TO DISPLAY 0.22µF 47KΩ 0.47µF 0.1µF 100pF 100KΩ V+ TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP 21 TO BACKPLANE TO DISPLAY 0.22µF 0.01µF 0.47µF 47KΩ 9V ZERO ADJUST SILICON NPN MPS 3704 OR SIMILAR 0.1µF 100kΩ 1MΩ 100kΩ 220kΩ 100pF SCALE FACTOR ADJUST 22KΩ 100KΩ The resistor values within the bridge are determined by the desired sensitivity. A silicon diode-connected transistor has a temperature coefﬁcient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. FIGURE 18. ICL7106 USED AS A DIGITAL CENTIGRADE THERMOMETER +5V FIGURE 17. ICL7107 MEASUREING RATIOMETRIC VALUES OF QUAD LOAD CELL V+ 1 V+ 2 D1 TO LOGIC VCC 3 C1 4 B1 5 A1 6 F1 7 G1 8 E1 9 D2 10 C2 11 B2 12 A2 13 F2 14 E2 15 D3 16 B3 17 F3 O /RANGE 18 E3 19 AB4 20 POL U /RANGE CD4023 OR 74C10 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 TO CREF 34 LOGIC GND CREF 33 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 BP 21 V- 1 V+ 2 D1 3 C1 4 B1 5 A1 6 F1 TO LOGIC VCC 12KΩ 7 G1 8 E1 9 D2 10 C2 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 BP 21 V- COMMON 32 The LM339 is required to ensure logic compatibility with heavy display loading. + O /RANGE 11 B2 12 A2 13 F2 14 E2 15 D3 16 B3 + + - 17 F3 18 E3 19 AB4 20 POL U /RANGE CD4023 OR 74C10 + 33KΩ CD4077 FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL7106 OUTPUTS FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUT 2-44 ICL7106, ICL7107 Typical Applications (Continued) TO PIN 1 OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V - 26 G2 25 C3 24 A3 23 G3 22 BP 21 TO BACKPLANE TO DISPLAY 0.22µF 47KΩ 10µF 9V 100pF (FOR OPTIMUM BANDWIDTH) 0.47µF 1KΩ 0.1µF 1µF 10KΩ 4.3KΩ 0.22µF 1µF 10KΩ 1µF 22KΩ 470KΩ 2.2MΩ 1N914 100pF 100kΩ 10µF SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) 5µF CA3140 + 100kΩ AC IN Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 21. AC TO DC CONVERTER WITH ICL7106 +5V DM7407 ICL7107 130Ω LED SEGMENTS 130Ω 130Ω FIGURE 22. DISPLAY BUFFERING FOR INCREASED DRIVE CURRENT 2-45

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