P. H. Rehak Three beat-to-beat cardiotachometer designs driver/display Dipl.-Ing. P. H. Rehak, University Clinic of Surgery, Auenbruggerplatz 5, A~8036 Graz, Austria Abstract--The paper introduces three beat-to-beat cardiotachometers in addition to the four types described by MASON and SHOUP (1979). Two systems are semi-analogue and one all-digitaL A detailed description of the principles of operation including block diagrams is given. A portable low power heart rate monitor developed from the all-digital design is described. Keywords - -Beat - to -beat heart-rate measurement. Cardiotachometer, Portable heart-rete monitor 1 Introduction FOLLOWING the paper of MASON and SHOUP (1979) I want to introduce three other approaches to the design of a beat-to-beat cardiotachometer. Two into 60 is done by a table stored in a memory. The all-digital system was developed into a low-power single-supply instrument suitable for operation from batteries. reference volfoge conv. compl. ORS- pulse - - T Vin o.d.c. Vref I' (ADD 3501) stort . cony. control peak detektor reset Med. & Biol. Eng. & Comput., 1981, 19, 75 78 romp reset Fig. 1 Dual-slope a.d.c, cardio- tachometer systems are semi-analogue and one all-digital. In the semi-analogue systems the cardiac period (time be- tween two q.r.s, complexes) is measured by the well known technique using a ramp voltage. The voltage proportional to the heart period is converted to a digital number with the necessary division prepared by utilising special features of the selected analogue to digital conversion technique. In the digital system the cardiac period is measured in the same way as in the divide-by-N design described by MASON and SHOUP (1979). The division First received 29th November 1979 and in revised form 1 lth March 1980 0140-0118/81/010075 +04 S01 "50/0 �9 IFMBE: 1981 2 Semi-analogue cardiotachometer using a dual-slope analogue-to-digital converter (a.d.c.) Fig. 1 shows the block diagram of the whole system. A ramp generator produces a linearly increas- ing voltage, which is reset to zero at the moment a q.r.s, pulse occurs. The maximum value of the ramp voltage is proportional to the last heart period. It is stored in a peak detector. The necessary division to obtain the heart rate from the measured period is performed by using the following feature of a dual- slope analogue to digital converter: the digital output number (d.o.n.) is directly proportional to the input voltage and inversly proportional to the reference voltage d.o.n. = (Vi./Vr~j') X N (1) Medical & Biological Engineering & Computing January 1981 75 where N is the number of possible output states. For a 3 �89 a.d.c, chosen for this design, N is equal to 2000. Eqn. 1 shows that a division can be performed by interchanging V~, and V, el. To allow the inter- changing, an a.d.c, with external reference is required. Since the dividing analogue to digital conversion has to be started after each q.r.s, pulse, the a.d.c, must have the capability to perform one single conversion on command. One a.d.c, which meets this specification is the ADD 3501 from National Semiconductors. Assuming a maximum heart rate of 199.9, a resolu- tion of 0.1 beat per minute (b.p.m.) is possible. Then the digital output number (d.o.n.) has to be equal to ten times the heart rate (HR). With this condition and eqn. 1, an equation for the ratio between V, es and the ramp slope can be written as d.o.n. = 10 HR = (Vref/Kr x T) x 2000 (2) where K, is the slope of the ramp voltage in volts per second, and T is the heart period in seconds. Note that V~, and V,e I are interchanged. Since HR = 60/T (3) eqn. 2 can be written as 10 HR = (V, ef" HR/K , x 60) x 2000 (4) or Vref/r, = 0"3 S (5) Choosing a ramp slope of 1 V/s, a reference voltage of 300 mV is required. The control logic performs the ramp reset at the time a q.r.s, pulse occurs and starts analogue to digital conversion at the same time. Alter the conversion is completed, the peak detector is reset by the control logic. With the ADD 3501 the conversion requires about 200 ms. Therefore, the display is updated approxi- mately 200 ms after the last q.r.s, pulse. Errors: The total error of the system is the sum of the errors due to ramp nonlinearity, reference voltage drift, peak detector drift and the error of the a.d.c. itself. A careful design using high performance com- ponents in the analogue section should make it pos- sible to keep the total error below • 1 b.p.m, Although the resolution is 0.1 b.p.m, it is often useful to omit the least significant digit to avoid display instability due to the jitter produced from the q.r.s. detection circuit. 3 Semi-analogue cardiotachometer using a multiplying digital-to-analogue convertor (d.a.c.) This system works similar to the 1/t-clock cardio- tachometer described by MASON and SHOUP (1979). A presettable 3 -}-digit b.c.d, down counter contains the corresponding heart rate at virtually any time within the heart period. Its output is latched, decoded and displayed at the moment a q.r.s, pulse occurs. Fig. 2 shows the block diagram of the system. The measurement of the heart period is performed in the same way as in the dual-slope a.d.c.-type cardiotach- ometer. A storage of the peak ramp voltage is not necessary in this design. The ramp generator is con- nected to the (reference-) input of a 3 {-digit multiply- ing digital-to-analogue converter (AD 7525, Analog Devices). The output voltage of the d.a.c, is compared with a reference voltage by a comparator. The com- parator controls a gate which allows clock pulses from a clock generator to get to the down counter input whenever the d.a.c, output voltage is higher than the reference voltage. The b.c.d, parallel output of the down counter is fed to the digital input port of compQrator control �9 gate QRS- pulse Vref clock Vout �9 clock d.a.c. (AD 7525) b.c.d, in b.c.d, out down counter control Vin preset ~-~ ramp reset f latch/decoder/driver circuit 1 display Fig. 2 Multiplying d.a.c, cardiotachometer 76 Medical & Biological Engineering & Computing January 1981 the d.a.c, and to a latch/decoder/driver circuit as well. The driver output is connected to a digital display. Thus a closed control loop is constructed, which keeps the d.a.c, output at the reference voltage level. It will be shown subsequently that the digital input number (d.i.n.) of the d.a.c, can be equated to ten times the heart rate. The transfer equation of the AD 7525 circuit is Vow, = -V~, x (d.i.n./1000) (6) where d.i.n, is the b.c.d, coded digital input number. The reason for the negative sign in eqn. 6 is the current mode output of the AD 7525 itself. Convert- ing the output current into a voltage using an invert- ing operational amplifier results in a signal inversion. A decreasing ramp voltage compensates the negative sign. Therefore the d.a.c, input voltage is expressed by V/= -K , x t (7) where Kr is the ramp voltage slope in volts per second and t is the time elapsed in seconds after resetting the ramp. Using eqn. 6 and eqn. 7 the fol- lowing can be written Vo= = Kr x t(d.i.n./1000) (8) d.i.n. = (11300 Vo=,/K,) x (l/t) (9) For a resolution of 0.I b.p.m, the digital input number (the number to be displayed) has to be equal to ten times the heart rate (HR) in b.p.m. d.i.n. = 10 HR (10) Owing to the closed control loop the d.a.c, output voltage is equal to the reference voltage. Using this and eqn. 3, an equation for the ratio between V, el and K, can be expressed: :V re ; /K r = 0-6 s (11) Choosing a ramp voltage slope of 5 V/s means that a reference voltage of 3 V is required. Fig. 3 shows the shapes of the ramp voltage, the d.a.c, output voltage and the digital input number as functions of time. At the start of a cycle (heart period) the ramp voltage is zero and the digital input number of the d.a.c, is 1999b.c.d., the preset number of the down counter. Therefore the d.a.c, output voltage is zero (eqn. 6) and the comparator keeps the gate closed for the clock pulses. The decreasing ramp voltage causes the d.a.c, output voltage to increase until it reaches the reference voltage level. After this time, corresponding to a heart rate of 199-9 b.p.m, the closed control loop mechanism is activated. This keeps the d.a.c, output at the level of the reference voltage by gating the clock pulses into the down counter thus decreasing the digital input number properly. The effect is the same as in the 1/t-clock cardio- tachometer: the down counter contains the precal- culated heart rate at any moment of the heart period within the measurement range. At the moment a q.r.s. pulse occurs the ramp is reset and the b.c.d, output of the down counter (= d.i.n.) is stored into the latch, decoded and displayed. This can be done simultan- eously because resetting the ramp makes the d.a.c. output voltage equal to zero causing the comparator to inhibit the gate. Therefore, there is no need for a storage of the ramp voltage. After latching the counter output the counter is preset to 1999b.c.a. again. To insure the proper func- tion of the closed control loop a minimum clock frequency is required, which is calculated from the shortest time interval between-two consecutive coun- ter output states. This interval occurs between the counter outputs 1999b.c.a. and 1998b.r �9 Using eqn. 9 the time interval can be expressed by t, = 1000 V~u,/1999 Kr - 100 Vo.,/1998 K, (12) With the given values for V~, t / (= l/,es) and K, ti = 150 #s (13) The minimum clock frequency required is therefore fro,, = 1/t, = 6-66 kHz (14) The accuracy of the system depends on the ramp linearity, the stability of the reference voltage, the comparator hysteresis and the accuracy of the d.a.c. itself. As in the semi-analogue system previously described a total error of less than +1 b.p.m, is attainable. v o.o| o? Vout V ref d i.n. ~ time time Fig. 3 Ramp voltage, d.a.c, output voltage and digital input number as functions of time Medical & Biological Engineering & Computing January 1981 77 4 Digital cardiotachometer using division by table Assuming a range of 30 to 180 b.p.m, and a resolu- tion of 1 b.p.m, to be acceptable for most applica- tions only 150 different output numbers are required. where N is the binary coded output number of the counter and the memory address as well. and DN is the corresponding rounded-off heart rate number. Following this approach a tow power single 5 V ORS- pulse-'--' clock control ,[clock binory counter "l reset adress memory (r.o m.) doto display [s enGole latch/decoder/driver circuit Fig. 4 Basic division-by-table cardiotachometer The division can therefore be performed using a table which is stored in a memory. Of course it is possible to extend the range and improve the resolution, but a design with the given values seems to be a good compromise between performance and equipment. Fig. 4 shows the block diagram of the basic cardio- tachometer working upon this principle. The heart period is measured by a binary counter and a clock generator in the conventional way. The binary output of the counter is connected to the address input of a read only memory (r.o.m.), which contains the corresponding heart rate numbers either binary or b.c.d, coded. The data output of the r.o.m, js fed to a decoder/driver circuit connected to a digital display. If the heart rates are stored in the r.o.m, as binary numbers, 8-bit data words are enough but decoding is more difficult than with b.c.d. numbers. For the given range of 30 to 180 b.p.m, a memory with 1 k (1024) addresses is sufficient. Con- sidering that the lowest heart rate for a display reading of '30' is 29'5 b.p.m. (rounded-off numbers are displayed) the maximum heart period is T,,ax = 60/29"5 = 2.034 s (15) The clock frequency required is calculated from f~t = 1024/T,,a,: = 503"5 Hz (16) The maximum heart rate measurable is limited to that rate, by which the advance of the counter by one count results in a change greater than 1 b.p.m, of the corresponding rounded-off heart rate number. With the given values the maximum heart rate is limited to 186 b.p.m. This range can be extended by reducing the resolution. The memory has to be programmed with data words calculated from O.v = 60 . J~ , /N (17) supply heart rate monitor was developed. The range was extended to 380 b.p.m, with a reduced resolution of 5 b.p.m, between 185 and 380 b.p.m. Averaging of 2. 4. 8 and 16 hearl periods is provided. The memory consists of a 2716 e.p.r.o.m., which is a 16 k (2k • 8) type. The heart rate numbers are stored as b.c.d, numbers, two digits at the addresses 0 to 1023, the third at the addresses 1024 to 2047. The 2716 is powered only during the data transfer time, which is about 5 #s for each q.r.s, pulse. The entire equipment (without q.r.s, detection circuit) consists of 12 c.m.o.s, packages, the 2716, 3 transistors and a liquid crystal display. The supply current (including a 5 V regulator) is 120 #A, allowing an operation for about 3500 hours from one 9 V battery (IEC 6 F 22), because the regulator works with a input voltage down to 5-1 V (REHAK, 1980). 5 Conclusions In addition to the four beat-to-beat cardiotach- ometers described by MASON and SHOUP (1979) three further designs have been presented. The block dia- grams have been given and explained. A low power portable instrument developed from one of the described designs has been introduced. References MASON, C. A. and SHOUP, J. F. (1979) Comparison of four beat-to-beat cardiotachometer designs. Med. &Biol . En 9. & Comput., 17, 349 359. REHAK, P. H. (1980) Micropower voltage regulator with very low Vo, ~ - Vi,. Electron. Eng. 52, May-issue. 78 Medical & Biological Engineering & Computing January 1981