Stefan Doll-VHDL Verification Course-UPDATED

VHDL Verification Course Verification is an important part of any ASIC design cycle. It's important that complex designs are simulated fully before prototypes are built, as it's difficult to find bugs in silicon and going through additional layout cycles is costly and time consuming. VHDL is well suited for verification. This course is an introduction to VHDL verification techniques. It assumes some familiarity with VHDL. © Stefan Doll, [email protected] Table of Contents Basic Stimulus Generation Testbench Structure Definition of Terms Writing to Files Reading from Files More Reading from Files The World of Perl SRAM modeling Passive SRAM Model Signal Monitors Generating Clock and Reset Stimulus Approaches to Test Generation File Read Method VHDL pre-processing Method Test-specific Entities Configuration controlled Test Selection Using Transaction Logs Using Transaction Logs II Using Behavioural Models Recommended Directory Structure Test Strategy The End Sponsor: BIO-SMG http://www.stefanvhdl.com/vhdl/html/index.html [1/13/2009 3:54:26 PM] VHDL Verification Course Basic stimulus generation and verification First basic stimulus generation is demonstrated. A simple XOR build from AND and OR gates is used as an example. An extra term is added to deliberately introduce an error. y = tSU report "E@SIMPLE_SRAM: Data setup time violated" severity Error; The variable start_cycle will be assigned to the simulation time. This means it will contain the time at which WE_L was first asserted in the access cycle. (The contents of that variable will be used later.) The attribute 'last_event is very useful for testbenches, it returns the time which has expired since the last event of a signal. (Example: if WE_L was asserted at 35 ns, and the current simulation time is 73 ns, then WE_L'last_event will return 73 ns - 35 ns = 38 ns.) In this case the A'last_event returns the time A has been stable before WE_L was asserted. This is the actual setup time and should be greater or equal to tSU. If this is not the case, the assert statement will issue the message "E@SIMPLE_SRAM: Address setup time violated". The same mechanism is used to verify the setup time for the data lines. -- report action for transaction log print("I@SIMPLE_SRAM: "& hstr(D)& "h written to "& hstr(A)& "h"); In any case the access to the SRAM will be reported. The hstr function is part of the txt_util.vhd package, of course. It returns the value of a std_logic_vector in hex format. -- verify address assert A = wadd report "E@SIMPLE_SRAM: Address incorrect, expected "& str(wadd)& " received "& str(A) severity Error; Next the address is verified, if it's incorrect a message is issued which reports the expected and the actual value. This time it's in binary format, so that it's easier to identify which bit was corrupted. -- verify data for i in wdat'range loop if wdat(i) /= '-' and wdat(i) /= D(i) then print("E@SIMPLE_SRAM: Write Data Invalid, written data = "& str(D)& " expected data = "& str(wdat) ); http://www.stefanvhdl.com/vhdl/html/sram.html (2 of 4) [1/13/2009 3:54:41 PM] VHDL Verification Course exit; end if; end loop; Somewhat more effort is put into verifying the data bus. Bits which are marked with "-" (=don't care bits) in the expected data are not compared with the actual data. This can be useful especially when modeling devices with a SRAM like interface when not all control bits at a particular address are actually relevant. (Example: wdat="00010--" and D="0001011" => not error would be indicated.) The loop will go through all bits of the expected data word, compare or skip it and issue an error message when a discrepancy is found. In that latter case the loop is exited, to avoid reporting the same error several times. wait until WE_L = '1'; -- verify pulse width on WE_L assert now - start_cycle >= tW_WE report "E@SIMPLE_SRAM: WE_L pulse width violated" severity Error; -- verify address and data haven't changed during the cycle assert A'last_event >= (now - start_cycle) report "E@SIMPLE_SRAM: Address hold time violated" severity Error; assert D'last_event >= (now - start_cycle) report "E@SIMPLE_SRAM: Data hold time violated" severity Error; The cycle completes when WE_L is deasserted. Now it's possible to verify the pulse width by comparing the current time with the time at the beginning of the cycle (= start_cycle). The 'last_event attribute can not be used for this purpose since that would now refer to the time expired since WE_L returned to '1' (= 0 ns). It's now also possible to verify that A hasn't changed during the cycle. If that was the case then A'last_event would be smaller than the time which has expired since the beginning of the cycle (= now - start_cycle). The same steps are taken to verify that D hasn't changed. -- now make add_hold = (now - start_cycle) report "E@SIMPLE_SRAM: Data hold time violated" severity Error; -- now make sure the hold times are maintained add_hold = (now - start_cycle) report "E@SIMPLE_SRAM: Address hold time violated" severity Error; -- now make sure the hold times are maintained add_hold