1.Programming the ARM Microprocessor for Embedded SystemsAjay
[email protected] 0.1 2. Copyrights • This document is available under the terms of Creative Commons Attribution- NonCommercial-NoDerivs 2.5 License • In simpler terms, you may– Reproduce and redistribute this document as-is for non-commercial use Copyright (c) 2006 by Ajay Dudani2 May not be reproduced or redistributed for commercial use. 3. Goals • Develop a good understanding of execution of ARM processor required to develop and debug embedded software with or without an operating system • Students should have prior knowledge about programming, operating system concepts and understanding of embedded systemsCopyright (c) 2006 by Ajay Dudani3 May not be reproduced or redistributed for commercial use. 4. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • Embedded operating system • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani4 May not be reproduced or redistributed for commercial use. 5. Why ARM? • Low power consumption • Fast execution per Watt • Good backward compatibility • Inexpensive • Variety of core offerings • … and other advantages we will see in upcoming slidesCopyright (c) 2006 by Ajay Dudani5 May not be reproduced or redistributed for commercial use. 6. Why ARM? • And …Marketing ☺ Copyright (c) 2006 by Ajay Dudani6 May not be reproduced or redistributed for commercial use. 7. Detailed Outline • ARM Technology– History– The competition Copyright (c) 2006 by Ajay Dudani7 May not be reproduced or redistributed for commercial use. 8. Detailed Outline • ARM Tools and products– Microprocessors– Compilers and debuggers– Single board computers– Documents and reference text Copyright (c) 2006 by Ajay Dudani8 May not be reproduced or redistributed for commercial use. 9. Detailed Outline • ARM Processor– Programming model– General purpose registers– Program control registers– Pipelining– Memory protection Copyright (c) 2006 by Ajay Dudani9 May not be reproduced or redistributed for commercial use. 10. Detailed Outline • Toolchain– ARM Toolchain– GNU Toolchain– Others Copyright (c) 2006 by Ajay Dudani10 May not be reproduced or redistributed for commercial use. 11. Detailed Outline • ARM Instruction Set– Instruction set encoding– Conditional field– Data processing instructions– Branch instructions– Load-store instructions– Software interrupt instruction– Program status register instructions– Semaphore instructions– Coprocessor instructions– Extending instructions Copyright (c) 2006 by Ajay Dudani11 May not be reproduced or redistributed for commercial use. 12. Detailed Outline • ARM Thumb Mode– Why Thumb?– Instruction set encoding– Branch instructions– Data processing instructions– Load and store instructions– Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani12 May not be reproduced or redistributed for commercial use. 13. Detailed Outline • ARM Exceptions and Interrupts– Exception vector table– Exception modes– Exception and interrupt handling Copyright (c) 2006 by Ajay Dudani13 May not be reproduced or redistributed for commercial use. 14. Detailed Outline • ARM Firmware– Bootloader– Standalone code– Example of initialization Copyright (c) 2006 by Ajay Dudani14 May not be reproduced or redistributed for commercial use. 15. Detailed Outline • ARM Caches– Memory hierarchy– Cache policy– Flushing policy– Software performance Copyright (c) 2006 by Ajay Dudani15 May not be reproduced or redistributed for commercial use. 16. Detailed Outline • ARM MMU and MPU– Protected memory– Example of memory protection– Virtual memory concepts– Example of virtual memory system Copyright (c) 2006 by Ajay Dudani16 May not be reproduced or redistributed for commercial use. 17. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani17 May not be reproduced or redistributed for commercial use. 18. ARM Technology Overview • ARM: “The Architecture For The Digital World” • ARM is a physical hardware design and intellectual property company • ARM licenses its cores out and other companies make processors based on its cores • ARM also provides toolchain and debugging tools for its cores Copyright (c) 2006 by Ajay Dudani18 May not be reproduced or redistributed for commercial use. 19. ARM Technology Overview (2) Companies licensing ARM IP:3ComMotorolaAgilent TechnologiesPanasonicAlteraQualcommEpson SharpFreescale SanyoFijitsu Sun MicrosystemsNEC SonyNokia SymbianIntel Texas InstrumentsIBM ToshibaMicrosoft Wipro Source: ARM Website… and many more Copyright (c) 2006 by Ajay Dudani19 May not be reproduced or redistributed for commercial use. 20. ARM History • Acorn Computer Group developed world’s first RISC processor in 1985 • Roger Wilson and Steve Furber were the principle developers • ARM (Advanced RISC Machines) was a spin out from Acorn in 1990 with goal of defining a new microprocessor standard Copyright (c) 2006 by Ajay Dudani20 May not be reproduced or redistributed for commercial use. 21. ARM History (2) • Acorn Computer GroupSource: WikipediaCopyright (c) 2006 by Ajay Dudani21 May not be reproduced or redistributed for commercial use. 22. ARM History (3) • ARM delivered ARM6 in 1991– Introduced 32 bit addressing support– New instruction for program status registers– Variant used in Apple Newton PDA • By 1996 ARM7 was being widely used– Microsoft started port of WinCE to ARM– Added multimedia extensions • Exponential growth from then on… Copyright (c) 2006 by Ajay Dudani22 May not be reproduced or redistributed for commercial use. 23. ARM and StrongARM • Intel gained certain IP from ARM as part of lawsuit settlement and modified ARM architecture branding it as StrongARM • StrongARM name was changed to XScale– Processor SA1000 , SA1100 • XScale is close to ARMv5 instruction set • XScale division of Intel was sold to Marvel Inc. in 2006 Copyright (c) 2006 by Ajay Dudani23 May not be reproduced or redistributed for commercial use. 24. ARM Today • ARM7xxx– 3 stage pipeline– Integer processor– MMU support for WinCE, Linux and Symbian– Used in entry level mobiles, mp3 players, pagers • ARM9xxx– 5 stage pipeline– Separate data and instruction cache– Higher end mobile and communication devices– Telematic and infotainment systems– ARM and Thumb instruction setCopyright (c) 2006 by Ajay Dudani24 May not be reproduced or redistributed for commercial use. 25. ARM Today (2) • ARM11xxx– 7 stage pipeline– Trustzone security related extensions– Reduced power consumption– Speed improvements– More DSP and SIMD extensions– Used in PDA, smartphones, industrialcontrollers, mobile gamingCopyright (c) 2006 by Ajay Dudani25 May not be reproduced or redistributed for commercial use. 26. ARM Processor Family • ARM has devised a naming convention for its processors • Revisions: ARMv1, v2 … v6, v7 • Core implementation:– ARM1, ARM2, ARM7, StrongARM,ARM926EJ, ARM11, Cortex • ARM11 is based on ARMv6 • Cortex is based on ARMv7 Copyright (c) 2006 by Ajay Dudani26 May not be reproduced or redistributed for commercial use. 27. ARM Processor Family (2) • Differences between cores– Processor modes– Pipeline– Architecture– Memory protection unit– Memory management unit– Cache– Hardware accelerated Java– … and others Copyright (c) 2006 by Ajay Dudani27 May not be reproduced or redistributed for commercial use. 28. ARM Processor Family (3) • Examples:– ARM7TDMI• No MMU, No MPU, No cache, No Java, Thumbmode– ARM922T• MMU, No MPU, 8K+8K data and instruction cache,No Java, Thumb mode– ARM1136J-S• MMU, No MPU, configurable caches, withaccelerated Java and Thumb modeCopyright (c) 2006 by Ajay Dudani28 May not be reproduced or redistributed for commercial use. 29. ARM Processor Family (4) • Naming convention • ARM [x][y][z][T][D][M][I][E][J][F][S]– x – Family– y – memory management/protection– z – cache– T – Thumb mode– D – JTAG debugging– M – fast multiplier– I – Embedded ICE macrocell– E – Enhanced instruction (implies TDMI)– J – Jazelle, hardware accelerated Java– F – Floating point unit– S – Synthesizable version Copyright (c) 2006 by Ajay Dudani29 May not be reproduced or redistributed for commercial use. 30. Outline • ARM Technology • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani30 May not be reproduced or redistributed for commercial use. 31. ARM Tools & ProductsDisclaimer: All owners own their respective trademarks Copyright (c) 2006 by Ajay Dudani 31 May not be reproduced or redistributed for commercial use. 32. ARM Chips • ARM Ltd– Provides ARM cores– Intellectual property • Analog Devices– ADuC7019, ADuC7020, ADuC7021, ADuC7022, ADuC7024, ADuC7025,ADuC7026, ADuC7027, ADuC7128, ADuC7129 • Atmel– AT91C140, AT91F40416, AT91F40816, AT91FR40162 • Freescale– MAC7101, MAC7104, MAC7105, MAC7106 • Samsung– S3C44B0X, S3C4510B • Sharp– LH75400, LH75401, LH75410, LH75411 • Texas Instruments– TMS470R1A128, TMS470R1A256, TMS470R1A288 • And others…Copyright (c) 2006 by Ajay Dudani32 May not be reproduced or redistributed for commercial use. 33. ARM Development Tools • Compilers:– GNU Compiler– ADS from ARM (older version)– RVCT Real View compiler tools from ARM– 3rd Party • Debugging– GNU gdb– Lauterbach JTAG/Trace32 tools– ETM hardware debugging & profilingmodules– Windriver toolsCopyright (c) 2006 by Ajay Dudani33 May not be reproduced or redistributed for commercial use. 34. ARM Single Board Computers • TS-7200 ARM Single board computer– 200 MHz ARM9 processor with MMU– 32 MB RAM– 8 MB Flash– Compact flash– 10/100 Ethernet Copyright (c) 2006 by Ajay Dudani34 May not be reproduced or redistributed for commercial use. 35. ARM Single Board Computers (2) • Cirrus Logic ARM CS98712– 16 MB RAM– 1MB Flash– 1 Serial port– LED lights Copyright (c) 2006 by Ajay Dudani35 May not be reproduced or redistributed for commercial use. 36. ARM Single Board Computers (3) • LN24x0/LP64– 200 Mhz ARM9 processor– LCD controller– Touchscreen– USB, IrDA ports– HDD and CD-ROM support– Speaker– JTAG portsCopyright (c) 2006 by Ajay Dudani36 May not be reproduced or redistributed for commercial use. 37. Recommended Text • “ARM System Developer’s Guide”– Sloss, et. al.– ISBN 1-55860-874-5 • “ARM Architecture Reference Manual”– David Seal– ISBN 0-201-737191– Softcopy available at www.arm.com • “ARM system-on-chip architecture”– Steve Fuber– ISBN 0-201-67519-6Copyright (c) 2006 by Ajay Dudani37 May not be reproduced or redistributed for commercial use. 38. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani38 May not be reproduced or redistributed for commercial use. 39. ARM Design Philosophy • ARM core uses RISC architecture– Reduced instruction set– Load store architecture– Large number of general purpose registers– Parallel executions with pipelines • But some differences from RISC– Enhanced instructions for• Thumb mode• DSP instructions• Conditional execution instruction• 32 bit barrel shifterCopyright (c) 2006 by Ajay Dudani39 May not be reproduced or redistributed for commercial use. 40. ARM Programming Model • A=B+C • To evaluate the above expression– Load A to a general purpose register R1– Load B to a general purpose register R2– Load C to a general purpose register R3– ADD R1, R2, R3– Store R1 to A Copyright (c) 2006 by Ajay Dudani40 May not be reproduced or redistributed for commercial use. 41. Registers • ARM has a load store architecture • General purpose registers can hold data or address • Total of 37 registers each 32 bit wide • There are 18 active registers– 16 data registers– 2 status registers Copyright (c) 2006 by Ajay Dudani41 May not be reproduced or redistributed for commercial use. 42. Registers (2) • Registers R0 thru R12 are generalR0R1 purpose registersR2R3 • R13 is used as stack pointer (sp)R4R5R6 • R14 is used as link register (lr)R7R8 • R15 is used a program counter (pc) R9R10 • CPSR – Current program statusR11R12 register R13 (sp)R14 (lr)R15 (pc) • SPSR – Stored program status registerCPSRSPSRCopyright (c) 2006 by Ajay Dudani 42 May not be reproduced or redistributed for commercial use. 43. Registers (3) • Program status register– CPSR is used to control and store CPU states– CPSR is divided in four 8 bit fields• Flags• Status• Extension• Control Copyright (c) 2006 by Ajay Dudani43 May not be reproduced or redistributed for commercial use. 44. Registers (4) • Program status register flags– N:1 – Negative result– Z:1 – Result is zero– C:1 – Carry in addition operation– C:0 – Borrow in subtraction operation– V:1 – Overflow or underflow Copyright (c) 2006 by Ajay Dudani44 May not be reproduced or redistributed for commercial use. 45. Registers (5) • Program status register controls– I:1 – IRQ interrupts disabled– F:1 – FIQ interrupts disabled– T:0 – ARM Mode– T:1 – Thumb Mode Copyright (c) 2006 by Ajay Dudani45 May not be reproduced or redistributed for commercial use. 46. Registers (6) • Program status register control modes– 0b10000 – User mode– 0b10001 – FIQ mode– 0b10010 – IRQ mode– 0b10011 – Supervisor mode– 0b10111 – Abort mode– 0b11011 – Undefined mode– 0b11111 – System mode Copyright (c) 2006 by Ajay Dudani46 May not be reproduced or redistributed for commercial use. 47. Processor Modes • Processor modes are execution modes which determines active registers and privileges • List of modes– Abort mode– Fast interrupt mode– Interrupt mode– Supervisor mode– System mode– Undefined mode– User mode • All except User mode are privileged modes– User mode is used for normal execution of programs andapplications– Privileged modes allow full read/write to CPSRCopyright (c) 2006 by Ajay Dudani 47 May not be reproduced or redistributed for commercial use. 48. Banked Registers • Of total 37 registers only 18 are active in a given register mode User/System Supervisor Abort FIQIRQ Undefined R0 R1 R2 R3 R4 R5 R6 R7 R8 R8_fiq R9 R9_fiq R10R10_fiq R11R11_fiq R12R12_fiq R13 (sp) R13_svc (sp) R13_abt (sp) R13_fiq (sp) R13_irq (sp) R13_und (sp) R14 (lr) R14_svc (lr) R14_abt (lr) R14_fiq (lr) R14_irq (lr) R14_und (lr) R15 (pc) CPSR SPSR SPSR_svc SPSR_abt SPSR_fiq SPSR_irq SPSR_undCopyright (c) 2006 by Ajay Dudani 48 May not be reproduced or redistributed for commercial use. 49. Pipeline • Pipelining is breaking down execution into multiple steps, and executing each step in parallel • Basic 3 stage pipeline– Fetch – Load from memory– Decode – Identify instruction to execute– Execute – Process instruction and write backresultCopyright (c) 2006 by Ajay Dudani49 May not be reproduced or redistributed for commercial use. 50. Pipeline (2) •Fetch Decode Execute Cycle 1 ADDCycle 2 SUB ADDTime Cycle 3 CMP SUB ADD Copyright (c) 2006 by Ajay Dudani50 May not be reproduced or redistributed for commercial use. 51. Pipeline (3) • ARM7 has a 3 stage pipeline– Fetch, Decode, Execute • ARM9 has a 5 stage pipeline– Fetch, Decode, Execute, Memory, Write • ARM10 has a 6 stage pipeline– Fetch, Issue, Decode, Execute, Memory,Write Copyright (c) 2006 by Ajay Dudani51 May not be reproduced or redistributed for commercial use. 52. Pipeline (4) • In theory, each instruction is one instruction cycle • In practice, there is interdependency between instructions– Solution: instruction scheduling Copyright (c) 2006 by Ajay Dudani52 May not be reproduced or redistributed for commercial use. 53. Memory Protection • Two modes for ARM memory protection– Unprotected mode• No hardware protection, software does protection of databetween tasks– Protected mode• Hardware protects areas of memory and raises exceptionswhen policy is voilated • ARM divides memory to regions and programmer can set attributes on regions • ARM provides mechanisms to define and set attributes of regions programmaticallyCopyright (c) 2006 by Ajay Dudani 53 May not be reproduced or redistributed for commercial use. 54. Memory Management • ARM supports memory management and virtual memory • Programmatically access translation look- aside buffers • ARM memory management unit also supports Fast Context Switching Extensions that optimizes use of caches in multitasking environments • Details in later section Copyright (c) 2006 by Ajay Dudani54 May not be reproduced or redistributed for commercial use. 55. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani55 May not be reproduced or redistributed for commercial use. 56. Toolchain • GNU Tools– gcc – Front end to GNU compiler– binutils – Binary tools• ld – GNU Linker• as – GNU assembler• And others– gdb – GNU Debugger– uClib – Small footprint C LibraryCopyright (c) 2006 by Ajay Dudani56 May not be reproduced or redistributed for commercial use. 57. Toolchain (2) • GCC– Invoked language specific modules– Invoked assembler and linker– arm-elf-gcc command• arm-elf-gcc test.c –o test• arm-elf-gcc test.S –o test Copyright (c) 2006 by Ajay Dudani57 May not be reproduced or redistributed for commercial use. 58. Toolchain (3) • GCC ARM specific options– mapcs-frame: Generate ARM procedure call compliant stackframe– mbig-endian: Generate big endian code– mno-alignment-traps: Generate code that assumes thatMMU does not trap on handling misaligned data– mcpu=name : Specify CPU name; gcc can determine whatinstructions it can use to generate output accordingly– mthumb: Generate code for ARM Thumb mode– msoft-float: Generate code assuming floating point hardwareis not present. Do floating point operation optimization insoftware– Refer to GCC manual page for more on compiler options Copyright (c) 2006 by Ajay Dudani 58 May not be reproduced or redistributed for commercial use. 59. Inline assembly • Developer can insert ARM assembly code in C code – for exampleprintf (“Hello ARM GCC”);__asm__ (“ldr r15, r0”);printf (“Program may have crashed”); Above code will corrupt program counter, so useinline assembly carefullyAlso, it may lead to non portable codeCopyright (c) 2006 by Ajay Dudani59 May not be reproduced or redistributed for commercial use. 60. Inline assembly (2) • Developer can force use of certain registers using extended assemblyasm ( assembler template :output operands /* optional */ :input operands /* optional */ :list of clobbered registers /* optional */ );• Example: int a = 10, b; __asm__ (“mov %0, %1” : “=r”(b) : “=r”(a)); Copyright (c) 2006 by Ajay Dudani60 May not be reproduced or redistributed for commercial use. 61. Inline assembly (3) • Developer can request variable to be assigned to specific register register int regVar __asm__(“%r4”); • Can be used with local and global variables • Need –ffixed- compiler option for global variables • Refer to GCC Inline Assembly reference for more examples Copyright (c) 2006 by Ajay Dudani61 May not be reproduced or redistributed for commercial use. 62. GNU Toolchain • Reference:– www.gnuarm.org– www.sourceware.org/binutils/– www.gnu.org/software/gdb/– www.sourceware.org/insight/– www.uclibc.org– GCC improvements for ARM• www.inf.u-szeged.hu/gcc-arm/Copyright (c) 2006 by Ajay Dudani62 May not be reproduced or redistributed for commercial use. 63. ARM Toolchain • ADS: ARM Developer Suite is older version of compiler, assembler and linker tools from ARM • RCVT: Latest ARM compiler, assembler and linker Copyright (c) 2006 by Ajay Dudani63 May not be reproduced or redistributed for commercial use. 64. ARM Toolchain • ARM also provides support for RealView tools it acquired as part of Keil acquisition • JTAG Support: ARM provides debugging tools to be used with JTAG supported hardware • ETM Support: Embedded Trace Module is hardware debug unit that extends on-target debugging capabilities by providing extra memory and registers for debugging purpose • Refer to www.arm.com and www.keil.com/arm/ for details on ARM toolsCopyright (c) 2006 by Ajay Dudani64 May not be reproduced or redistributed for commercial use. 65. Other Toolchains • GNU X-Tools– www.microcross.com • IAR ARM Kit– www.iar.com • Intel Development Suite for XScale– www.intel.comCopyright (c) 2006 by Ajay Dudani65 May not be reproduced or redistributed for commercial use. 66. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani66 May not be reproduced or redistributed for commercial use. 67. ARM Instruction Set • Overview Copyright (c) 2006 by Ajay Dudani67 May not be reproduced or redistributed for commercial use. 68. ARM Instruction Set (2) • Condition fields Copyright (c) 2006 by Ajay Dudani68 May not be reproduced or redistributed for commercial use. 69. ARM Instruction Set (3) • Add • Subract • Multiply Copyright (c) 2006 by Ajay Dudani69 May not be reproduced or redistributed for commercial use. 70. ARM Instruction Set (4) • Bit shifting Copyright (c) 2006 by Ajay Dudani70 May not be reproduced or redistributed for commercial use. 71. ARM Instruction Set (5) • Status register operation Copyright (c) 2006 by Ajay Dudani71 May not be reproduced or redistributed for commercial use. 72. ARM Instruction Set (6) • Semaphore instruction Copyright (c) 2006 by Ajay Dudani72 May not be reproduced or redistributed for commercial use. 73. ARM Instruction Set (7) • Placeholder page Copyright (c) 2006 by Ajay Dudani73 May not be reproduced or redistributed for commercial use. 74. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani74 May not be reproduced or redistributed for commercial use. 75. Thumb Instruction Set • Overview of 16 bit mode Copyright (c) 2006 by Ajay Dudani75 May not be reproduced or redistributed for commercial use. 76. Thumb Instruction Set (2) • Thumb Instruction set details Copyright (c) 2006 by Ajay Dudani76 May not be reproduced or redistributed for commercial use. 77. Thumb Instruction Set (3) • Switching between ARM and Thumb mode Copyright (c) 2006 by Ajay Dudani77 May not be reproduced or redistributed for commercial use. 78. Outline • ARM Technology Overview • ARM Tools & Products • ARM Processor • ARM Toolchain • ARM Instruction set • Thumb instruction set • ARM exception and interrupts • ARM Firmware • ARM Caches • Memory management and protection • ARM Future development Copyright (c) 2006 by Ajay Dudani78 May not be reproduced or redistributed for commercial use. 79. Exceptions • Exception handling is a programming language or hardware mechanism to catch runtime errors • C++ and Java support exception handling in software1.void func()2.{3.try4.{5.int a = 100/0;6.}7.catch(...)8.{9.cout