PicoBlaze is an 8-bit microcontroller which can be synthesized in the Spartan 3 FPGA on the Digilent Starter Board. PicoBlaze is similar in architecture to many small microcontrollers but it is specifically designed and optimized for implementation in an Xilinx FPGA. Note there are also larger microprocessors that can be synthesized into FPGAs such as the 32-bit MicroBlaze microprocessor. PicoBlaze (and MicroBlaze) are referred to as soft core processors as they are synthesized from an HDL and use only the Programmable Logic Blocks and Routing of an FPGA for their implementation. A second type of FPGA processor termed hard core, such as the PowerPC, are physically incorporated in the architecture of some FPGAs. Introduction The process of implementing any soft core microcontroller or microprocessor in an FPGA will be similar to that described below for PicoBlaze. This tutorial assumes that you have downloaded the PicoBlaze.zip files from the R: drive or web page and extracted all of the files into your working directory. These files include everything needed to synthesize the example program. PicoBlaze (see Figure 1) consists of two key parts: 1) The Processor Core: KCPSM3 ( which stands for Ken Chapman Programmable State Machine version 3 ) 2) The Program Memory ( from which instructions are fetched and executed by the processor core.) Note: that the program memory is referred to as an Instruction ROM or Program ROM in Xilinx PicoBlaze documentation since the processor core cannot write to the Program Memory. Figure 1 Figure 1 shows the Input and Output Ports of KCPSM3, with their widths. These will usually correspond to internal signals within the top level module. As a result, there are two corresponding VHDL files that are used to construct the complete PicoBlaze with program: i) The PicoBlaze file, KCPSM3.vhd is optimized for Spartan 3 by calling design primitives LUTs, MUX, FFs etc.) specific to Spartan 3 and, as a result, this VHDL file should not be modified by the user. The KCPSM3 requires approximately 96 slices in a Spartan3. The Program Memory file, “name_rom”.vhd on the other hand, is a VHDL ROM file which contains the user’s desired program to be executed by the PicoBlaze core. This ROM File is generated automatically by the Assembler ( pBlazIDE or KCPSM3.exe) from your assembly language program. ( .psm file ) Note that the prefix for the .psm file must be 8 characters or less.) This Program Memory is implemented in a single Block RAM in the FPGA configured to function as a 1K×18-bit ROM. ii) The program to be executed is initialised in the Block RAM during the download of the overall design (including PicoBlaze and other user logic) and, as a result, is assembled prior to synthesis. Figure 2 ISE PicoBlaze Project Figure 3 PicoBlaze occupancy in an XC3S200 Figure 2 shows the Xilinx ISE Implementation Project Files for a simple PicoBlaze Project. These files are available in PicoBlaze.zip In addition to the PicoBlaze core file (kcpsm.vhd) and the ROM file (tut1_rom.vhd) there is a VHDL file to drive the seven segment display on the S3 Starter Board and the UCF file for the S3 Board. The toplevel file should be be mainly structural in content, instantiating the components and linking the processor to the ROM and the IO, but the Inputs and Outputs will require a Selection Statement. Figure 3 show how little space PicoBlaze takes up in the Spartan3 FPGA. Figure 4 PicoBlaze.zip Files The Files provide .psm file and compile it into a VHDL ROM file it is best to use the application pBlazeIDE. The User Interface of this program is shown in Figure 5. This application is extremely useful as it allows the designer to fully simulate the assemble code and check its operation. In most cases the actual programmed processor will perform as the simulator predicts. ‘myparts.vhd’ is a library file which contains the component declarations. S3_Board_UCF is the ucf file for the Board and maps the Ports of the VHDL entity onto the correct FPGAS pins. Figure 5 pBlazeIDE User Interface Files Programming PicoBlaze Programming the processor in Assemble Language is interesting and informative. A Block diagram of PicoBlaze is given in Figure 6. You can see that the hardware resources are very limited. There are only 16 Registers and 2 Flags, There are however 256 x 8 bit I/O connections. 64 Byte Scratchpad RAM The Instruction Set, which is also very limited (See Figure 7) can be split into seven groups: Figure 6 Figure 7 PicoBlaze Instruction Set Files Example .psm File VHDL "S3_template_ROM.vhd", "tut1_rom.vhd", "tut1_rom" This first line creates the VHDL rom file (tut1_rom.vhd) with the entity named, “tut1_rom” from the template rom file (S3_template_rom.vhd) and the psm file. BUTTONS_port SWITCHES_port char21 char43 LEDS_port DSIN DSIN $02 $03 ; this is the PORT_ID allocated to the Buttons ; this is the PORT_ID allocated to the Switches ; this is the PORT_ID allocated to two lower SSDs ; this is the PORT_ID allocated to two upper SSDs ; this is the PORT_ID allocated to the LEDs DSOUT $04 DSOUT $05 DSOUT $06 The next set-of-lines allocate the I/O Port numbers to the input and output objects on the board. These must correspond with the associate ports in the top level VHDL file: case port_id is when x"02" => in_port in_port