Performance Analysis of Different Arbitration Algorithms of the AMBA AHB Bus Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti.

Slide 1 Performance Analysis of Different Arbitration Algorithms of the AMBA AHB Bus Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti DAC 2004, June 7-11, 2004 San Diego, California, USA Slide 2 2015/6/28 Abstract  Bus performances are extremely important in a platform-based design. System Level analysis of bus performances gives important information for the analysis and choice between different architectures driven by functional, timing and power constraints of the System-on-Chip. This paper presents the effect of different arbitration algorithms and bus usage methodologies on the bus AMBA AHB performances in terms of effective throughput and power dissipation. SystemC and VHDL models have been developed and simulations have been performed. Slide 3 2015/6/28 Outline  Abstract  What’s the problem  Introduction  AMBA Bus and SystemC models  Simulations and results  Inter-burst idle insertion  Arbitration algorithms  Conclusion Slide 4 2015/6/28 What’s the problem  System-level design and IP modeling is the key to fast SoC innovation  Innovate quickly  High level of abstraction  Fast simulation  IP reuse Slide 5 2015/6/28 Introduction  Use SystemC to quickly try out different design alternatives:  to confirm the best possible architecture  HW/SW partition  performance parameters  Power consumption Slide 6 2015/6/28 AMBA Bus and SystemC models  AMBA AHB can be decomposed in the following main blocks:  One arbiter  A decoder  Some multiplexing logic Slide 7 2015/6/28 Arbitration algorithms  Priority with break  Priority  Priority with waiting time control  Short Job First  Short Job First with waiting time control Slide 8 2015/6/28 Experiment environment introduction  Three masters and one slave: M1, M2 and DM (default master)  Transmits sequences of 512 bytes for a total of 5k bytes for each master  M1 transmits each packet of 512 bytes in different ways:  1 burst of 128 beats  2 bursts of 64 beats  4 bursts of 32 beats  8 bursts of 16 beats  16 bursts of 8 beats  M2 transmits 10 bursts of 128 beats each  Idle period of a length 4, 8, 16  Data bus : 32 bit Slide 9 2015/6/28 Important characteristic  M1 intentionally divides its transmission in bursts to enable the use of the bus by other master during its idle periods Slide 10 2015/6/28 Results  There is no inter-burst of master that bursts length is 128 beats  Waiting time is not effected by the inter- burst idle length Slide 11 2015/6/28 Results (cont.)  Input signals :  HSELx  HWRITE  HTRANS  HSIZE  HBURST  HRESET  HMASTER  HMASTLOCK  Output signals  HREADY  HSPLIT Slide 12 2015/6/28 Results (cont.)  Results in table 1-5 are useful to evaluate the bus performance  High priority master use short burst the low priority one : Waiting time decrease Switching activity increases Slide 13 2015/6/28 Results (cont.)  Traffic generator  HIGH: random sequence of 8 or 16 beats bursts  LOW: random sequence of single or 4 beats bursts  Priority order : M1 high.. M5 low  Algo. 2 penalize low priority master  Algo. 5 penalize long length burst Slide 14 2015/6/28 Conclusion  SystemC accurate model of the AMBA AHB bus  Models are used to evaluate the performance  A reduction of bus power dissipation of more than 22%