Microfluidic Biochips: Design, Programming, and Optimization Bill Thies Joint work with Vaishnavi Ananthanarayanan, J.P. Urbanski, Nada Amin, David Craig,

Slide 1 Microfluidic Biochips: Design, Programming, and Optimization Bill Thies Joint work with Vaishnavi Ananthanarayanan, J.P. Urbanski, Nada Amin, David Craig, Jeremy Gunawardena, Todd Thorsen, and Saman Amarasinghe Indian Statistical Institute March 2, 2011 Slide 2 Microfluidic Chips Idea: a whole biology lab on a single chip –Input/output –Sensors: pH, glucose, temperature, etc. –Actuators: mixing, PCR, electrophoresis, cell lysis, etc. Benefits: –Small sample volumes –High throughput –Geometrical manipulation –Portability Applications: –Biochemistry - Cell biology –Biological computing 1 mm 10x real-time Slide 3 Application to Rural Diagnostics Disposable Enteric Card PATH, Washington U. Micronics, Inc., U. Washington Targets: - E. coli, Shigella, Salmonella, C. jejuni DxBox U. Washington, Micronics, Inc., Nanogen, Inc. Targets: - malaria (done) - dengue, influenza, Rickettsial diseases, typhoid, measles (under development) CARD Rheonix, Inc. Targets: - HPV diagnosis - Detection of specific gene sequences Slide 4 Moore’s Law of Microfluidics: Valve Density Doubles Every 4 Months Source: Fluidigm Corporation (http://www.fluidigm.com/images/mlaw_lg.jpg) Slide 5 Moore’s Law of Microfluidics: Valve Density Doubles Every 4 Months Source: Fluidigm Corporation (http://www.fluidigm.com/didIFC.htm) Slide 6 Current Practice: Manage Gate-Level Details from Design to Operation For every change in the experiment or the chip design: 1. Manually draw in AutoCAD 2. Operate each gate from LabView fabricate chip Slide 7 Abstraction Layers for Microfluidics C x86 Pentium III, Pentium IV Silicon Analog transistors, registers, … Fluidic Instruction Set Architecture (ISA) - primitives for I/O, storage, transport, mixing Protocol Description Language - architecture-independent protocol description Fluidic Hardware Primitives - valves, multiplexers, mixers, latches chip 1chip 2chip 3 Slide 8 Abstraction Layers for Microfluidics Fluidic Instruction Set Architecture (ISA) - primitives for I/O, storage, transport, mixing Protocol Description Language - architecture-independent protocol description Fluidic Hardware Primitives - valves, multiplexers, mixers, latches chip 1chip 2chip 3 BioCoder Language [J.Bio.Eng. 2010] Contributions Optimized Compilation [Natural Computing 2007] Demonstrate Portability [DNA 2006] Micado AutoCAD Plugin [MIT 2008, ICCD 2009] Digital Sample Control Using Soft Lithography [Lab on a Chip ‘06] Slide 9 Continuous flow of fluids (or droplets) through fixed channels [Whitesides, Quake, Thorsen, …] Pro: –Smaller, more precise sample sizes –Made-to-order availability [Stanford] –More traction in biology community Droplets vs. Continuous Flow Digital manipulation of droplets on an electrode array [Chakrabarty, Fair, Gascoyne, Kim, …] Pro: –Reconfigurable routing –Electrical control –More traction in CAD community Source: Chakrabarty et al, Duke University Slide 10 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer 0. Start with mask of channels Slide 11 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer 1. Deposit pattern on silicon wafer Slide 12 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer 2. Pour PDMS over mold - polydimexylsiloxane: “soft lithography” Thick layer (poured) Thin layer (spin-coated) Slide 13 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer 3. Bake at 80° C (primary cure), then release PDMS from mold Slide 14 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer 4a. Punch hole in control channel 4b. Attach flow layer to glass slide Slide 15 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer 5. Align flow layer over control layer Slide 16 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer 6. Bake at 80° C (secondary cure) Slide 17 Primitive 1: A Valve (Quake et al.) Control Layer Flow Layer pressure actuator 7. When pressure is high, control channel pinches flow channel to form a valve Slide 18 Primitive 2: A Multiplexer (Thorsen et al.) flow layer control layer Bit 2Bit 1Bit 0 0 1 0 1 0 1 Input Output 0 Output 7 Output 6 Output 5 Output 4 Output 3 Output 2 Output 1 Control lines can cross flow lines - Only thick parts make valves Logic is not complimentary To control n flow lines, need 2 log 2 n control lines Slide 19 Primitive 2: A Multiplexer (Thorsen et al.) Bit 2Bit 1Bit 0 0 1 0 1 0 1 Input Output 0 Output 7 Output 6 Output 5 Output 4 Output 3 Output 2 Output 1 Example: select 3 = 011 flow layer control layer Control lines can cross flow lines - Only thick parts make valves Logic is not complimentary To control n flow lines, need 2 log 2 n control lines Slide 20 Primitive 2: A Multiplexer (Thorsen et al.) Bit 2Bit 1Bit 0 0 1 0 1 0 1 Input Output 0 Output 7 Output 6 Output 5 Output 4 Output 3 Output 2 Output 1 Example: select 3 = 011 flow layer control layer Control lines can cross flow lines - Only thick parts make valves Logic is not complimentary To control n flow lines, need 2 log 2 n control lines Slide 21 Primitive 2: A Multiplexer (Thorsen et al.) Bit 2Bit 1Bit 0 0 1 0 1 0 1 Input Output 0 Output 7 Output 6 Output 5 Output 4 Output 3 Output 2 Output 1 Example: select 3 = 011 flow layer control layer Control lines can cross flow lines - Only thick parts make valves Logic is not complimentary To control n flow lines, need 2 log 2 n control lines Slide 22 Primitive 3: A Mixer (Quake et al.) 1. Load sample on bottom 2. Load sample on top 3. Peristaltic pumping Rotary Mixing Slide 23 Primitive 4: A Latch (Our contribution) Purpose: align sample with specific location on device –Examples: end of storage cell, end of mixer, middle of sensor Latches are implemented as a partially closed valve –Background flow passes freely –Aqueous samples are caught Sample Latch Slide 24 Primitive 4: A Latch (Our contribution) Purpose: align sample with specific location on device –Examples: end of storage cell, end of mixer, middle of sensor Latches are implemented as a partially closed valve –Background flow passes freely –Aqueous samples are caught Sample Latch Slide 25 Primitive 5: Cell Trap Several methods for confining cells in microfluidic chips –U-shaped weirs- C-shaped rings / microseives –Holographic optical traps- Dialectrophoresis In our chips: U-Shaped Microseives in PDMS Chambers Source: Wang, Kim, Marquez, and Thorsen, Lab on a Chip 2007 Slide 26 Primitive 6: Imaging and Detection As PDMS chips are translucent, contents can be imaged directly –Fluorescence, color, opacity, etc. Feedback can be used to drive the experiment Slide 27 Abstraction Layers for Microfluidics Fluidic Instruction Set Architecture (ISA) - primitives for I/O, storage, transport, mixing Protocol Description Language - architecture-independent protocol description Fluidic Hardware Primitives - valves, multiplexers, mixers, latches chip 1chip 2chip 3 Slide 28 Driving Applications 1. What are the best indicators for oocyte viability? -With Mark Johnson’s and Todd Thorsen’s groups -During in-vitro fertilization, monitor cell metabolites and select healthiest embryo for implantation 2. How do mammalian signal transduction pathways respond to complex inputs? -With Jeremy Gunawardena’s and Todd Thorsen’s groups -Isolate cells and stimulate with square wave, sine wave, etc. Slide 29 Driving Applications 1. What are the best indicators for oocyte viability? -With Mark Johnson’s and Todd Thorsen’s groups -During in-vitro fertilization, monitor cell metabolites and select healthiest embryo for implantation 2. How do mammalian signal transduction pathways respond to complex inputs? -With Jeremy Gunawardena’s and Todd Thorsen’s groups -Isolate cells and stimulate with square wave, sine wave, etc. Video courtesy David Craig Slide 30 CAD Tools for Microfluidic Chips Goal: automate placement, routing, control of microfluidic features Why is this different than electronic CAD? Slide 31 CAD Tools for Microfluidic Chips Goal: automate placement, routing, control of microfluidic features Why is this different than electronic CAD? 1. Control ports (I/O pins) are bottleneck to scalability –Pressurized control signals cannot yet be generated on-chip –Thus, each logical set of valves requires its own I/O port 2. Control signals correlated due to continuous flows  Demand & opportunity for minimizing control logic pipelined flowcontinuous flow Slide 32 Our Technique: Automatic Generation of Control Layer Slide 33 1. Describe Fluidic ISA Slide 34 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA Slide 35 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA Slide 36 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves Slide 37 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves Slide 38 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing Slide 39 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing Slide 40 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports Slide 41 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports Slide 42 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports Slide 43 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI Slide 44 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI Slide 45 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI Slide 46 Our Technique: Automatic Generation of Control Layer 1. Describe Fluidic ISA 2. Infer control valves 3. Infer control sharing 4. Route valves to control ports 5. Generate an interactive GUI Slide 47 1. Describe a Fluidic ISA Hierarchical and composable flow declarations Sequential flow P 1  P 2 AND-flow F 1 Λ F 2 OR-flow F 1 \/ F 2 Mixing mix(F) Pumped flow pump(F) P 1 P 2 F1F1 F2F2 F1F1 F2F2 or F F F1F1 F2F2 Slide 48 1. Describe a Fluidic ISA Slide 49 mix-and-store (S 1, S 2, D) { 1. in 1  top  out 2. in 2  bot  out 3. mix(top  bot-left  bot-right  top) 4. wash  bot-right  top  bot-left  store } 50x real-time Slide 50 2. Infer Control Valves Slide 51 Slide 52 Slide 53 3. Infer Control Sharing Slide 54 Slide 55 Slide 56 Slide 57 Slide 58 Slide 59 Slide 60 Slide 61 Slide 62 Column Compatibility Problem - NP-hard - Reducible to graph coloring Slide 63 3. Infer Control Sharing Column Compatibility Problem - NP-hard - Reducible to graph coloring Slide 64 3. Infer Control Sharing Column Compatibility Problem - NP-hard - Reducible to graph coloring Slide 65 3. Infer Control Sharing Column Compatibility Problem - NP-hard - Reducible to graph coloring Slide 66 3. Infer Control Sharing Column Compatibility Problem - NP-hard - Reducible to graph coloring Slide 67 4. Route Valves to Control Ports Build on recent algorithm for simultaneous pin assignment & routing [Xiang et al., 2001] Idea: min cost - max flow from valves to ports Our contribution: extend algorithm to allow sharing – Previous capacity constraint on each edge: – Modified capacity constraint on each edge:  Solve with linear programming, allowing sharing where beneficial f 1 + f 2 + f 3 + f 4 + f 5 + f 6 ≤ 1 max(f 1, f 4 ) + max(f 2, f 3 ) + f 5 + f 6 ≤ 1 Slide 68 4. Route Valves to Control Ports Build on recent algorithm for simultaneous pin assignment & routing [Xiang et al., 2001] Idea: min cost - max flow from valves to ports Our contribution: extend algorithm to allow sharing – Previous capacity constraint on each edge: – Modified capacity constraint on each edge:  Solve with linear programming, allowing sharing where beneficial f 1 + f 2 + f 3 + f 4 + f 5 + f 6 ≤ 1 max(f 1, f 4 ) + max(f 2, f 3 ) + f 5 + f 6 ≤ 1 Slide 69 Micado: An AutoCAD Plugin Implements ISA, control inference, routing, GUI export –Using slightly older algorithms than presented here [Amin ‘08] –Parameterized design rules –Incremental construction of chips Realistic use by at least 3 microfluidic researchers Freely available at: http://groups.csail.mit.edu/cag/micado/ Slide 70 Cell Culture with Waveform Generator Courtesy David Craig Slide 71 Cell Culture with Waveform Generator Courtesy David Craig Slide 72 Embryonic Cell Culture Courtesy J.P. Urbanski Slide 73 Embryonic Cell Culture Courtesy J.P. Urbanski Slide 74 Metabolite Detector Courtesy J.P. Urbanski Slide 75 Metabolite Detector Courtesy J.P. Urbanski Slide 76 Open Problems Automate the design of the flow layer –Hardware description language for microfluidics –Define parameterized and reusable modules Replicate and pack a primitive as densely as possible –How many cell cultures can you fit on a chip? Support additional primitives and functionality –Metering volumes –Sieve valves –Alternate mixers –Separation primitives –… Slide 77 Conclusions: Microfludics CAD Microfluidics represents a rich new playground for CAD researchers Two immediate goals: –Enable designs to scale –Enable non-experts to design own chips Micado is a first step towards these goals –Hierarchical ISA for microfluidics –Inference and minimization of control logic –Routing shared channels to control ports –Generation of an interactive GUI http://groups.csail.mit.edu/cag/micado/ Courtesy J.P. Urbanski Slide 78 Abstraction Layers for Microfluidics Fluidic Instruction Set Architecture (ISA) - primitives for I/O, storage, transport, mixing Protocol Description Language - architecture-independent protocol description Fluidic Hardware Primitives - valves, multiplexers, mixers, latches chip 1chip 2chip 3 Slide 79 Toward “General Purpose” Microfluidic Chips Slide 80 A Digital Architecture Recent techniques can control independent samples –Droplet-based samples –Continuous-flow samples –Microfluidic latches In abstract machine, all samples have unit volume –Input/output a sample –Store a sample –Operate on a sample Challenge for a digital architecture: fluid loss –No chip is perfect – will lose some volume over time –Causes: imprecise valves, adhesion to channels, evaporation,... –How to maintain digital abstraction? [Fair et al.] [Our contribution] Slide 81 Maintaining a Digital Abstraction Slide 82 Instruction Set Architecture (ISA) High-Level Language Hardware Electronics Microfluidics Replenish charge (GAIN) Loss of charge Randomized Gates [Palem] Soft error Handling? Replenish fluids? - Maybe (e.g., with water) - But may affect chemistry Loss of fluids ? ? ? ? ? ? Expose loss in ISA - Compiler deals with it Expose loss in language - User deals with it Slide 83 Towards a Fluidic ISA Microfluidic chips have various mixing technologies –Electrokinetic mixing –Droplet mixing –Rotary mixing Common attributes: –Ability to mix two samples in equal proportions, store result Fluidic ISA: mix (int src 1, int src 2, int dst) –Ex: mix(1, 2, 3) –To allow for lossy transport, only 1 unit of mixture retained [Quake et al.] [Fair et al.] [Levitan et al.] Storage Cells 1 2 3 4 Mixer Slide 84 Implementation: Oil-Driven Chip InputsStorage CellsBackground PhaseWash PhaseMixing Chip 128Oil—Rotary Slide 85 Implementation: Oil-Driven Chip InputsStorage CellsBackground PhaseWash PhaseMixing Chip 128Oil—Rotary mix (S 1, S 2, D) { 1. Load S 1 2. Load S 2 3. Rotary mixing 4. Store into D } 50x real-time Slide 86 Implementation 2: Air-Driven Chip InputsStorage CellsBackground PhaseWash PhaseMixing Chip 128Oil—Rotary Chip 2432AirWaterIn channels Slide 87 Implementation 2: Air-Driven Chip mix (S 1, S 2, D) { 1. Load S 1 2. Load S 2 3. Mix / Store into D 4. Wash S 1 5. Wash S 2 } InputsStorage CellsBackground PhaseWash PhaseMixing Chip 128Oil—Rotary Chip 2432AirWaterIn channels 50x real-time Slide 88 “Write Once, Run Anywhere” Example: Gradient generation Hidden from programmer: –Location of fluids –Details of mixing, I/O –Logic of valve control –Timing of chip operations 450 Valve Operations Fluid yellow = input (0); Fluid blue = input(1); for (int i=0; i