Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 4 Optimizing Power @ Design Time Circuits Dejan Marković Borivoje Nikolić.

Slide 1Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 4 Optimizing Power @ Design Time Circuits Dejan Marković Borivoje Nikolić Slide 2Low Power Design Essentials ©2008 4.2 Chapter Outline  Optimization framework for energy-delay trade-off  Dynamic power optimization –Multiple supply voltages –Transistor sizing –Technology mapping  Static power optimization –Multiple thresholds –Transistor stacking Slide 3Low Power Design Essentials ©2008 4.3 Energy/Power Optimization Strategy  For given function and activity, an optimal operation point can be derived in the energy-performance space  Time of optimization depends upon activity profile  Different optimizations apply to active and static power Fixed Activity Variable Activity No Activity - Standby Active Design timeRun timeSleep Static Slide 4Low Power Design Essentials ©2008 4.4 Maximize throughput for given energy or Minimize energy for given throughput Delay Unoptimized design E max D max D min Energy/op E min Energy-Delay Optimization and Trade-off Trade-off space Other important metrics: Area, Reliability, Reusability Slide 5Low Power Design Essentials ©2008 4.5 The Design Abstraction Stack Logic/RT (Micro-)Architecture Software Circuit Device System/Application This Chapter A very rich set of design parameters to consider! It helps to consider options in relation to their abstraction layer sizing, supply, thresholds logic family, standard cell versus custom Parallel versus pipelined, general purpose versus application specific Bulk versus SOI Choice of algorithm Amount of concurrency Slide 6Low Power Design Essentials ©2008 4.6 Architecture Micro-Architecture Circuit (Logic & FFs) Optimization Can/Must Span Multiple Levels Design optimization combines top-down and bottom-up: “meet-in-the-middle” Slide 7Low Power Design Essentials ©2008 4.7 topology A Delay Energy/op Globally optimal energy-delay curve for a given function Energy-Delay Optimization topology B topology A topology B Delay Energy/op Slide 8Low Power Design Essentials ©2008 4.8 Some Optimization Observations ∂E / ∂A ∂D / ∂A A=A 0 SA=SA= SBSB SASA f (A 0,B) f (A,B 0 ) Delay Energy D0D0 (A 0,B 0 ) Energy-Delay Sensitivities [Ref: V. Stojanovic, ESSCIRC’02 ] Slide 9Low Power Design Essentials ©2008 4.9 ∆E = S A ∙(  ∆D) + S B ∙∆D On the optimal curve, all sensitivities must be equal Finding the Optimal Energy-Delay Curve f (A 0,B) f (A,B 0 ) Delay Energy D0D0 (A 0,B 0 ) ∆D f (A 1,B) Pareto-optimal: the best that can be achieved without disadvantaging at least one metric. Slide 10Low Power Design Essentials ©2008 4.10  Reducing voltages –Lowering the supply voltage (V DD ) at the expense of clock speed –Lowering the logic swing (V swing )  Reducing transistor sizes (C L ) – Slows down logic  Reducing activity (  ) –Reducing switching activity through transformations –Reducing glitching by balancing logic Reducing Active Energy @ Design Time Slide 11Low Power Design Essentials ©2008 4.11  Downsizing and/or lowering the supply on the critical path lowers the operating frequency  Downsizing non-critical paths reduces energy for free, but –Narrows down the path delay distribution –Increases impact of variations, impacts robustness t p (path) # of paths target delay t p (path) # of paths target delay Observation Slide 12Low Power Design Essentials ©2008 4.12 topology A topology B Delay Energy/op  Reference case –D min sizing @ V DD max, V TH ref minimize Energy (V DD, V TH, W) subject toDelay (V DD, V TH, W) ≤ D con Constraints V DD min < V DD < V DD max V TH min < V TH < V TH max W min < W Circuit Optimization Framework [Ref: V. Stojanovic, ESSCIRC’02 ] Slide 13Low Power Design Essentials ©2008 4.13 i i+1 CwCw CiCi CiCi C i+1 Optimization Framework: Generic Network V DD,i+1 V DD,i Gate in stage i loaded by fanout (stage i+1) Slide 14Low Power Design Essentials ©2008 4.14 Fit parameters: V on,  d, K d,  Alpha-power based Delay Model V DD ref = 1.2V, technology 90 nm Slide 15Low Power Design Essentials ©2008 4.15  Parasitic delay p i – depends upon gate topology  Electrical effort f i ≈ S i+1 /S i  Logical effort g i – depends upon gate topology  Effective fanout h i = f i g i For Complex Gates [Ref: I. Sutherland, Morgan-Kaufman’99] Combined with Logical Effort Formulation Slide 16Low Power Design Essentials ©2008 4.16 = energy consumed by logic gate i Dynamic Energy i i+1 CwCw CiCi CiCi C i+1 V DD,i+1 V DD,i Slide 17Low Power Design Essentials ©2008 4.17  for equal h (D min )  for equal h (D min ) max at V DD (max) (D min ) max at V DD (max) (D min ) Depends on Sensitivity (  E/  D) Optimizating Return on Investment (ROI)  Gate Sizing  Supply Voltage Slide 18Low Power Design Essentials ©2008 4.18  Properties of inverter chain –Single path topology –Energy increases geometrically from input to output Example: Inverter Chain 1 S 1 = 1 S2S2 … SNSN S3S3  Goal –Find optimal sizing S = [S 1, S 2, …, S N ], supply voltage, and buffering strategy to achieve the best energy-delay tradeoff Slide 19Low Power Design Essentials ©2008 4.19  Variable taper achieves minimum energy  Reduce number of stages at large d inc [Ref: Ma, JSSC’94] Inverter Chain: Gate Sizing 1234567 0 5 10 15 20 25 stage effective fanout, h 0% 1% 10% 30% d inc = 50% nom opt Slide 20Low Power Design Essentials ©2008 4.20  V DD reduces energy of the final load first  Variable taper achieved by voltage scaling Inverter Chain: V DD Optimization 1234567 0 0.2 0.4 0.6 0.8 1.0 stage V DD / V DD nom 0% 1% 10% 30% d inc = 50% nom opt Slide 21Low Power Design Essentials ©2008 4.21  Parameter with the largest sensitivity has the largest potential for energy reduction  Two discrete supplies mimic per-stage V DD Inverter Chain: Optimization Results 50 inc 010203040 0 20 40 60 80 100 d (%) energy reduction (%) 01020304050 0 0.2 0.4 0.6 0.8 1.0 d inc (%) Sensitivity (norm) cV DD S gV DD 2V DD Slide 22Low Power Design Essentials ©2008 4.22  Tree adder –Long wires –Re-convergent paths –Multiple active outputs Example: Kogge-Stone Tree Adder [Ref: P. Kogge, Trans. Comp’73] Slide 23Low Power Design Essentials ©2008 4.23 sizing: E (-54%) d inc =10% reference D=D min 2V dd : E (-27%) d inc =10% Tree Adder: Sizing vs. Dual-V DD Optimization  Reference design: all paths are critical  Internal energy  S more effective than V DD –S: E(-54%), 2V dd : E(-27%) at d inc = 10% Slide 24Low Power Design Essentials ©2008 4.24 Tree Adder: Multi-dimensional Search  Can get pretty close to optimum with only 2 variables  Getting the minimum speed or delay is very expensive Energy / E ref Delay / D min 0.40.60.811.21.41.61.82 0 0.2 0.4 0.6 0.8 1 Reference S, V DD V DD, V TH S, V TH S, V DD, V TH Slide 25Low Power Design Essentials ©2008 4.25  Block-level supply assignment –Higher throughput/lower latency functions are implemented in higher V DD –Slower functions are implemented with lower V DD –This leads to so-called “voltage islands” with separate supply grids –Level conversion performed at block boundaries  Multiple supplies inside a block –Non-critical paths moved to lower supply voltage –Level conversion within the block –Physical design challenging Multiple Supply Voltages Slide 26Low Power Design Essentials ©2008 4.26 V 1 = 1.5V, V TH = 0.3V Using Three V DD ’s + V 2 (V) V 3 (V) 0.40.60.811.21.4 0.4 0.6 0.8 1 1.2 1.4 V 2 (V) V 3 (V) Power Reduction Ratio 0 0.5 1 1.5 0 0.5 1 1.5 0.4 0.5 0.6 0.7 0.8 0.9 1 [Ref: T. Kuroda, ICCAD’02] © IEEE 2002 Slide 27Low Power Design Essentials ©2008 4.27 1.0 0.5 VDD Ratio 1.0 0.4 0.51.01.5 V 1 (V) P Ratio V2/V1V2/V1 P2/P1P2/P1 { V 1, V 2 } V2/V1V2/V1 V3/V1V3/V1 { V 1, V 2, V 3 } 0.51.01.5 V 1 (V) P3/P1P3/P1 V2/V1V2/V1 V3/V1V3/V1 V4/V1V4/V1 0.51.01.5 V 1 (V) P4/P1P4/P1 { V 1, V 2, V 3, V 4 } [Ref: M. Hamada, CICC’01] Optimum Number of V DD ’s  The more V DD ’s the less power, but the effect saturates  Power reduction effect decreases with scaling of V DD  Optimum V 2 /V 1 is around 0.7 © IEEE 2001 Slide 28Low Power Design Essentials ©2008 4.28  Two supply voltages per block are optimal  Optimal ratio between the supply voltages is 0.7  Level conversion is performed on the voltage boundary, using a level-converting flip-flop (LCFF)  An option is to use an asynchronous level converter –More sensitive to coupling and supply noise Lessons: Multiple Supply Voltages Slide 29Low Power Design Essentials ©2008 4.29 i1o1 V DDH V DDL V SS Conventional V DDH circuitV DDL circuit i2o2 i1o1 V DDH V DDL V SS Shared N-well V DDH circuitV DDL circuit i2o2 Distributing Multiple Supply Voltages Slide 30Low Power Design Essentials ©2008 4.30 V DDH circuit V DDH V DDL V SS N-well isolation V DDL circuit (a) Dedicated row (b) Dedicated region V DDH Row V DDH Region V DDL Region Conventional V DDL Row Slide 31Low Power Design Essentials ©2008 4.31 V DDH circuit V DDH V DDL V SS Shared N-well V DDL circuit (a) Floor plan image V DDL circuit V DDH circuit Shared N-Well [Shimazaki et al, ISSCC’03] Slide 32Low Power Design Essentials ©2008 4.32 Lower V DD portion is shared [Ref: M. Takahashi, ISSCC’98] “Clustered voltage scaling” Example: Multiple Supplies in a Block FF CVS Structure Conventional Design Critical Path Level-Shifting F/F Critical Path FF © IEEE 1998 Slide 33Low Power Design Essentials ©2008 4.33 Pulsed Half-Latch versus Master-Slave LCFFs  Smaller # of MOSFETs / clock loading  Faster level conversion using half-latch structure  Shorter D-Q path from pulsed circuit [Ref: F. Ishihara, ISLPED’03] Level Converting Flip-Flops (LCFFs) Master-Slave Pulsed Half-Latch © IEEE 2003 Slide 34Low Power Design Essentials ©2008 4.34  Pulsed precharge LCFF (PPR) –Fast level conversion by precharge mechanism –Suppressed charge/discharge toggle by conditional capture –Short D-Q path [Ref: F. Ishihara, ISLPED’03] Dynamic Realization of Pulsed LCFF Pulsed Precharge Latch © IEEE 2003 Slide 35Low Power Design Essentials ©2008 4.35 carry gen. partial sum gp gen. 5:1 MUX ain bin carry s0/s1 sum sumb (long loop-back bus) clk clock gen. : V DDH circuit : V DDL circuit INV1 INV2 0.5pF sum sel. 2:1 MUX 9:1 MUX logical unit 9:1 MUX ain0 Case Study: ALU for 64-bit  Processor [Ref: Y. Shimazaki, ISSCC’03] © IEEE 2003 Slide 36Low Power Design Essentials ©2008 4.36 sum keeper pc sumb V DDH V DDL INV1INV2 domino level converter (9:1 MUX) ain0 sel (V DDH ) V DDH V DDL  INV2 is placed near 9:1 MUX to increase noise immunity  Level conversion is done by a domino 9:1 MUX Low-Swing Bus and Level Converter [Ref: Y. Shimazaki, ISSCC’03] © IEEE 2003 Slide 37Low Power Design Essentials ©2008 4.37 Single-supply Shared well (V DDH =1.8V) Energy [pJ] T CYCLE [ns] Room temperature 200 300 400 500 600 700 800 0.60.81.01.21.41.6 1.16GHz V DDL =1.4V Energy:-25.3% Delay :+2.8% V DDL =1.2V Energy:-33.3% Delay :+8.3% Measured Results: Energy and Delay [Ref: Y. Shimazaki, ISSCC’03] © IEEE 2003 Slide 38Low Power Design Essentials ©2008 4.38 Practical Transistor Sizing  Continuous sizing of transistors only an option in custom design  In ASIC design flows, options set by available library  Discrete sizing options made possible in standard-cell design methodology by providing multiple options for the same cell –Leads to larger libraries (> 800 cells) –Easily integrated into technology mapping Slide 39Low Power Design Essentials ©2008 4.39 Larger gates reduce capacitance, but are slower Technology Mapping a b c slack=1 d f Slide 40Low Power Design Essentials ©2008 4.40  (a) Implemented using 4 input NAND + INV  (b) Implemented using 2 input NAND + 2-input NOR Library 1: High-Speed Technology Mapping Example: 4-input AND Gate type Area (cell unit) Input cap. (fF) Average delay (ps) INV31.87.0 + 3.8 C L 12.0 + 6.0 C L NAND242.010.3 + 5.3 C L 16.3 + 8.8 C L NAND452.013.6 + 5.8 C L 22.7 + 10.2 C L NOR232.210.7 + 5.4 C L 16.7 + 8.9 C L Library 2: Low-Power (delay formula: C L in fF) (numbers calibrated for 90 nm) Slide 41Low Power Design Essentials ©2008 4.41 Technology Mapping – Example 4-input AND (a) NAND4 + INV (b) NAND2 + NOR2 Area811 HS: Delay (ps)31.0 + 3.8 C L 32.7 + 5.4 C L LP: Delay (ps)53.1 + 6.0 C L 52.4 + 8.9 C L Sw Energy (fF)0.1 + 0.06 C L 0.83 + 0.06 C L  Area –4-input more compact than 2-input (2 gates vs. 3 gates)  Timing –both implementations are 2-stage realizations –2 nd stage INV (a) is better driver than NOR2 (b) –For more complex blocks, simpler gates will show better performance  Energy –Internal switching increases energy in the 2-input case –Low-power library has worse delay, but lower leakage (see later) Slide 42Low Power Design Essentials ©2008 4.42  Technology mapping  Gate selection  Sizing  Pin assignment  Logical Optimizations  Factoring  Restructuring  Buffer insertion/deletion  Don’t care optimization Gate-Level Tradeoffs for Power Slide 43Low Power Design Essentials ©2008 4.43 Logic restructuring to minimize spurious transitions Buffer insertion for path balancing Logic Restructuring 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 2 3 Slide 44Low Power Design Essentials ©2008 4.44 Idea: Modify network to reduce capacitance Caveat: This may increase activity! p a = 0.1; p b = 0.5; p c = 0.5 Algebraic Transformations a b c f f a a b c p 1 =0.05 p 2 =0.05 p 3 =0.075 p 4 =0.75 p 5 =0.075 Slide 45Low Power Design Essentials ©2008 4.45  Joint optimization over multiple design parameters possible using sensitivity-based optimization framework –Equal marginal costs ⇔ Energy-efficient design  Peak performance is VERY power inefficient –About 70% energy reduction for 20% delay penalty –Additional variables for higher energy-efficiency  Two supply voltages in general sufficient; 3 or more supply voltages only offer small advantage  Choice between sizing and supply voltage parameters depends upon circuit topology  But … leakage not considered so far Lessons from Circuit Optimization Slide 46Low Power Design Essentials ©2008 4.46  Considering leakage as well as dynamic power is essential in sub-100 nm technologies  Leakage is not essentially a bad thing –Increased leakage leads to improved performance, allowing for lower supply voltages –Again a trade-off issue … Considering Leakage @ Design Time Slide 47Low Power Design Essentials ©2008 4.47 Must adapt to process and activity variations TopologyInvAddDec (E Lk /E Sw ) opt 0.80.50.2 Leakage – Not Necessarily a Bad Thing Optimal designs have high leakage (E Lk /E Sw ≈ 0.5) 10 -2 10 10 0 1 0 0.2 0.4 0.6 0.8 1 E static /E dynamic E norm V th ref -180mV 0.81V DD max V th ref -140mV 0.52V DD max Version 1 Version 2 [Ref: D. Markovic, JSSC’04] © IEEE 2004 Slide 48Low Power Design Essentials ©2008 4.48  Switching energy  Leakage energy with: I 0 (  ): normalized leakage current with inputs in state  Refining the Optimization Model Slide 49Low Power Design Essentials ©2008 4.49  Using longer transistors –Limited benefit –Increase in active current  Using higher thresholds –Channel doping –Stacked devices –Body biasing  Reducing the voltage!! Reducing Leakage @ Design Time Slide 50Low Power Design Essentials ©2008 4.50  10% longer gates reduce leakage by 50%  Increases switching power by 18% with W/L = const.  Doubling L reduces leakage by 5x  Impacts performance – Attractive when don’t have to increase W (e.g. memory) Longer Channels 100110120130140150160170180190200 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Transistor length (nm) 1 2 3 4 5 6 7 8 9 10 90 nm CMOS Switching energy Leakage power Normalized switching energy Normalized leakage power Slide 51Low Power Design Essentials ©2008 4.51  There is no need for level conversion  Dual thresholds can be added to standard design flows –High-V Th and Low-V Th libraries are a standard in sub-0.18  m processes –For example: can synthesize using only high-V Th and then only in-place swap in low-V Th cells to improve timing. –Second V Th insertion can be combined with resizing  Only two thresholds are needed per block –Using more than two yields small improvements Using Multiple Thresholds Slide 52Low Power Design Essentials ©2008 4.52 V DD = 1.5V, V TH.1 = 0.3V Three V TH ’s + V TH.3 (V) V TH.2 (V) 0.40.60.811.21.4 0.4 0.6 0.8 1 1.2 1.4 Leakage Reduction Ratio V TH.3 (V) V TH.2 (V) 0 0.5 1 1.5 0 0.5 1 1.5 0 0.2 0.4 0.6 0.8 1 Impact of third threshold very limited [Ref: T. Kuroda, ICCAD’02 ] © IEEE 2002 Slide 53Low Power Design Essentials ©2008 4.53 Using Multiple Thresholds FF  Cell-by-cell V TH assignment (not at block level)  Achieves all-low-V TH performance with substantial leakage reduction in leakage Low V TH High V TH [Ref: S. Date, SLPE’94 ] Slide 54Low Power Design Essentials ©2008 4.54 Shaded transistors are low threshold Low-threshold transistors used only in critical paths Dual-V T Domino P1P1 Inv 1 Inv 2 Inv 3 D n+1 Clk n Clk n+1 DnDn … Slide 55Low Power Design Essentials ©2008 4.55  Easily introduced in standard cell design methodology by extending cell libraries with cells with different thresholds –Selection of cells during technology mapping –No impact on dynamic power –No interface issues (as was the case with multiple V DD ’s)  Impact: Can reduce leakage power substantially Multiple Thresholds and Design Methodology Slide 56Low Power Design Essentials ©2008 4.56 High-V TH Only Low-V TH Only Dual V TH Total Slack-53 psec0 psec Dynamic Power 3.2 mW3.3 mW3.2 mW Static Power 914 nW3873 nW1519 nW All designs synthesized automatically using Synopsys Flows [Courtesy: Synopsys, Toshiba, 2004] Dual-V TH Design for High-Performance Design Slide 57Low Power Design Essentials ©2008 4.57 Example: High- vs. Low-Threshold Libraries Leakage Power (nW) Selected combinational tests 130 nm CMOS [Courtesy: Synopsys 2004] Slide 58Low Power Design Essentials ©2008 4.58 Complex Gates Increase I on /I off Ratio  I on and I off of single NMOS versus stack of 10 NMOS transistors  Transistors in stack are sized up to give similar drive No stack Stack 00.10.20.30.40.50.60.70.80.91 0 0.5 1 1.5 2 2.5 3 V DD (V) I off (nA) No stack Stack 00.10.20.30.40.50.60.70.80.91 0 20 40 60 80 100 120 140 I on (  A) V DD (V) (90nm technology) Slide 59Low Power Design Essentials ©2008 4.59 Complex Gates Increase I on /I off Ratio Stacking transistors suppresses submicron effects  Reduced velocity saturation  Reduced DIBL effect  Allows for operation at lower thresholds Stack No stack Factor 10! 00.10.20.30.40.50.60.70.80.91 0 0.5 1 1.5 2 2.5 3 3.5 x 10 5 V DD (V) I on /I off ratio (90nm technology) Slide 60Low Power Design Essentials ©2008 4.60  Example: 4-input NAND With transistors sized for similar performance: Leakage of Fan-in(2) = Leakage of Fan-in(4) x 3 (Averaged over all possible input patterns) Fan-in (2)Fan-in (4) versus Complex Gates Increase I on /I off Ratio Slide 61Low Power Design Essentials ©2008 4.61 Example: 32 bit Kogge-Stone Adder [Ref: S.Narendra, ISLPED’01] % of input vectors Standby leakage current (  A) factor 18 Reducing the threshold by 150 mV increases leakage of single NMOS transistor by factor 60 © Springer 2001 Slide 62Low Power Design Essentials ©2008 4.62  Circuit optimization can lead to substantial energy reduction at limited performance loss  Energy-delay plots the perfect mechanisms for analyzing energy-delay trade-off’s.  Well-defined optimization problem over W, V DD and V TH parameters  Increasingly better support by today’s CAD flows  Observe: leakage is not necessarily bad – if appropriately managed. Summary Slide 63Low Power Design Essentials ©2008 4.63 Books:  A. Bellaouar, M.I Elmasry, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academic Publishers, 1 st Ed, 1995.  D. Chinnery, K. Keutzer, Closing the Gap Between ASIC and Custom, Springer, 2002.  D. Chinnery, K. Keutzer, Closing the Power Gap Between ASIC and Custom, Springer, 2007.  J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2 nd ed, Prentice Hall 2003.  I. Sutherland, B. Sproul, D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan- Kaufmann, 1 st Ed, 1999. Articles:  R.W. Brodersen, M.A. Horowitz, D. Markovic, B. Nikolic, V. Stojanovic, “Methods for True Power Minimization,” Int. Conf. on Computer-Aided Design (ICCAD), pp. 35-42, Nov. 2002.  S. Date, N. Shibata, S.Mutoh, and J. Yamada, "IV 30MHz Memory-Macrocell-Circuit Technology with a 0.5urn Multi-Threshold CMOS," Proceedings of the 1994 Symposium on Low Power Electronics, San Diego, CA, pp. 90-91, Oct. 1994.  M. Hamada, Y. Ootaguro, T. Kuroda, “Utilizing Surplus Timing for Power Reduction,” IEEE Custom Integrated Circuits Conf., (CICC), pp. 89-92, Sept. 2001.  F. Ishihara, F. Sheikh, B. Nikolic, “Level conversion for dual-supply systems,” Int. Conf. Low Power Electronics and Design, (ISLPED), pp. 164-167, Aug. 2003.  P.M. Kogge and H.S. Stone, “A Parallel Algorithm for the Efficient Solution of General Class of Recurrence Equations,” IEEE Trans. Comput., vol. C-22, no. 8, pp. 786-793, Aug 1973.  T. Kuroda, “Optimization and control of V DD and V TH for low-power, high-speed CMOS design,” Proceedings ICCAD 2002, pp., San Jose, Nov. 2002. References Slide 64Low Power Design Essentials ©2008 4.64 Articles (cont.):  H.C. Lin and L.W. Linholm, “An Optimized Output Stage for MOS Integrated Circuits,” IEEE J. Solid-State Circuits, vol. SC-10, no. 2, pp. 106-109, Apr. 1975.  S. Ma and P. Franzon, “Energy Control and Accurate Delay Estimation in the Design of CMOS Buffers,” IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1150-1153, Sept. 1994.  D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, “Methods for True Energy- Performance Optimization,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.  MathWorks, http://www.mathworks.com  S. Narendra, S. Borkar, V. De, D. Antoniadis, A. Chandrakasan, “Scaling of stack effect and its applications for leakage reduction,” Int. Conf. Low Power Electronics and Design, (ISLPED), pp. 195-200, Aug. 2001.  T. Sakurai and R. Newton, “Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.  Y. Shimazaki, R. Zlatanovici, B. Nikolic, “A shared-well dual-supply-voltage 64-bit ALU,” Int. Conf. Solid-State Circuits, (ISSCC), pp. 104-105, Feb. 2003.  V. Stojanovic, D. Markovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, “Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization,” European Solid- State Circuits Conf., (ESSCIRC), pp. 211-214, Sept. 2002.  M. Takahashi et al., “A 60mW MPEG video codec using clustered voltage scaling with variable supply-voltage scheme,” IEEE Int. Solid-State Circuits Conf., (ISSCC), pp. 36-37, Feb. 1998. References