G@1 Frecluency Synthcsizcr 1 .. i.. ... Objectirres.. 15.2 Discussion Of Fundamentals... 15.3 Equipments Required. 5.4 Experiments And Records... .. 5.1 1 5- 1 15-1 ' .. 15-19 1 1 5- 1 9 Experiment 15-1 Typical Freque'tcy Synthesizer Experiment 15-2 Frequency Synthesizer with Prescaler Experiment 15-3 Frequency Synthesizer with Frequency Conv'erier 15.5 Questions 15-34 Frequency SynthesiZer oBtEcTryES 1. To study the principle of frequency synthesizeis. 2. To measure the characteristics of frequency synthesizers. DISCUSSION OF FUNDAMENTAIS Basically a frequency synthesizer is a frequency source whose output signal frequency is equal to the input reference frequency multiplied by an integer rmber. Figure 15-1 shows a typical frequency ,synthesizer, which consists of a phase-locked loop (PLL), voltage-controlled osciltator (vco), phase n detector and divide-by-N counter. The phase detector in the PLL of Figure 1b-1 produces an average voltage value, which is oroportional to the difference between the input reference frequency fsgp dhd the output frequency of divide-by-N counter f6/N. The divide-by-N counter is generally preset by thumbwheel switches or controlled with an MPU software. This counter produces an output pulse every N input pulses. The output voltage of the phase detector is applied to the input of the voltage-controlled oscillator (vco) after filtering by a low pass filter (LpF) tc control the Vco output frequency f6,, so that the output frequency is equal to N times the input reference frequency in locking. Figure 15-1 Block diagrarn of typical frequency synthesizer t5- r Unlt l5 \MrenthePLLoperatesinlock,therelationshipbetweenreferenceand bY counter outPut can be exPressed fP=f*=fo111 or the equivalent equation fo=Nfn It is by the reference frequency is determined evident that the output other words' a frequency preset counter value N' ln frequency fp and the synthesizerisafrequencygeneratorwhoseoutputfrequencyisequaltothe inputreferencefrequencymultipliedbyanintegerN.Thereforeastableand precisionreferencefrequencyisrequiredforanexcellentfrequency is employed' synthesizers. Usually a crystaloscillator Various FrequencY SYnthesizers synthesizers available There are many tYPes of frequency in practical applications' Theseare: SYnthesizer 'r ypical F requencY 1.'ly il;;;-;;;*, rjirect frequencv svnthesizer' rhe tne orocx diasram of ia fha -:-^..il PLL circuit is fp to the reference input of the lne ;;;;-tr"or"n", previously' the tlivided by M' As mentioned fx crystal oscillator frequency the synthesizer is ealculated by frequency of the frequency output equation fo=N'fn 'nthesizei Frequency SynllqqEgl rnce and fo=Nfn Figure 15-2 Block diagram of typical frequency synthesizer reference frequency lual to the stable and frequency The main disaclvantage of the typical frequency synthesizer is the frequency limitation of programmable divider. The maximum operating frequency of programmable dividers available in market is only several tens of MHz. This limits the maximum output frequency of frequency synthesizer. To overcome this disadvantage the following types of frequency synthesizer may be selected. 2. r practical Frequency Synthesizer with Frequency JVlultiplier A frequency multiplier witlr a multiplication H is used in the type of frequency synthesizer shown in Figure 15-3. From the block diagram, the output signal frequency is calculated by fo = N (Hfn) xizer. The cuit is the viously, the However this frequency synthesizer has two disadvantages: (1) an additional frequency-selective circuit is required, and (2) a small variation in VCO output frequency will result in a unbearable variation in synthesizer output frequency. Frequency Multiplier (xH) ed by the fo=N(l-ifn) Figure 15-3 Frequency synthesizer with a frequency multiplier I 5-3 l.'|!'fu Unltl$ " .. , , ', Frequencl[ Jlnlheshel ": 3. Frequency $yntheoizor with Prescaler synthesizer with a Figure 15-4 showa the block diagram of the frequency (synthesizer prescaler, The prescaler introducing between vco output the input frequency output) and divide-by-N divider input is used to lower of the divider in an allowable range' Figure 15'4 Freqpency synthesizer with prescaler ! is manufactured in Basically the prescaler, a $tpe of frequency divider, ECLtechnologyandcanop-erateatmuchhighfrequency(uptoGHz). 15-4 is given by The output signal frequency of the synthesizer in Figure fo= N(P'fn) at a higher since fq is the VCO output, therefore the VCO must operate frequ.encycomparedwiththesetwotypesdiscussedabove. uency Synthesizer with F roquency Go nverter using in Generally there are hrvo types of the frequency conversion F req freqr"ency synthesizers, These are rising conversion and lowering conversion. Figure 15-5 shows the- frequency synthesizer with rising frequency frequency by converter. The VCO output frequency is converted to higher is expressed as the mixer and local oscillator circuit. The output frequency l5-4 hesizer lryqlolgv- srr$gggqr fe'=f1+frlf* with a resizer luency fo'=fr+111* =1tl(Pfn) where fs r€presents the output frequenc5'of local oscillator. r:igure olP 15-5 Frequency synthesizel with rising frequency converter The first problem encountered irr this frequency synthesizer is similar to the type of frequency synthesizer with frequency multiplier due ured in lz). en by to a frequency-selective circuit is needed at output stage. ln addition, the local oscillator is located outside the PLL circuit so that the PLL cannot correct the frequency deviation caused by the local oscillator. Figure 15-6 shows the frequency synthesizer with lowering frequency converter. The mixer is inside the PLL circuit so that the frequency deviation of local oscillator can be corrected by PLL. The output frequency, Lhigher fe= f1+\lfs, is from the VCO output directly so that the VCO must operate at higher frequencies. slng rn lwering quency mcy by ;sed as Figure 15-6 Frequency synthesizer with lowering frequency converter r 5-5 Unit ti Transfer Function and Transient Response FrequoncY SYnthosiror is an important The analysis of transfer function or transient response to the block technique in designing frequency synthesizers. Referring diagramofbasicfrequencysynthesizershowninFigurelS.T,the transfer function' characteristic of each block is expressed by its own Ve(s):Vd(s)F(s) 0n(s) 0o(s)=KoVe(s)/s 0N(s)=0o(s)A''l Figure 15.7 Transfer function of a frequency svnthesizer 0o is the phase of ln Figure 15-7, 0n is the phase of the reference signal and is directly the VCO output signal. The output of the phase comparator by the proportional to the difference between these two phases multiplied conversion gain Ko and can be expressed as Vo=Ko(0n-0N)=KoAg the lowpass filter The voltag€ Vo csused by thq phase error A0 runs through in order to filter the high-frequency components out. The VCO output andrthe conversion frequency is determined by the LPF output voltage V" gain l$. roo=KoxV. I Replacing coo bY d0Jdt gives l5-6 nthosizor Frequencv Svnthesizer d0s/dt=l$xV" mportant Laplace transform of the above equation is he block *7, the €(d0"1dt)=s0u(s)= KoxVu(s) Therefore 0o(s)=(ft.V rVe(s)/s (s)ls. ln short, the phase of VCO output is directly proportionalto the controlvoltage V" multiplied by an integer constant. dfo Ljplace transforms of the blocks in Figure 15-7 can be expressed as Vo(s)=Ko [0n(s)- eN(s) I V"(s)=F(s).Vo(s) 06(s)=[lG.V"(s)l/s 0x(s)= [Oo(s]l / N The transfer function of the frequency synthesizer is therefore expressed by phase of s directly H(s) d = 0 o(s) KoKoF(s) = by the 0 n(s) s + KoKoF(s)/N 'H(s) depends on the lowpass filter (LPF) transfer function F(s). There are two types of LPF usually available in this application. Type I and ll of RC lowpass filter:'re shown in Figures 15-8 and 15-9, respectively. rass filter O output mversion r5.7 treqgglgy_gynllgsge-1 Figure 15-8 Type I of RC lowpass filter R1 Figure 15-9 Type ll of RC lowpass filter The transfer function of type I lowpass filter can be expressed by F(s)= b.= Vin '1 1+s r where = RC. lf the RC lowpass filter of Figure 15-8 is used as the loop filter of the frequency synthesizer, the transfer function of the frequency synthesizer can be expressed as r iynthesizgl Frequency Synthesizer rut$r H1(s)= "r+I*KoKo tNz :'.rffioducing the damping ratio d into the above equation, becomes H,,(s)=oo(s)= Nri = 0,(s) s2 +2dtrtn +o I = UUrete 0n = d=2 Fedacing the loop filter by the RC lowpass filter of Figure 15-9, the transfer of loop filter is given by 1 F(s)=ffi *FIe rr = RrC and tz = RzC. The transfer function of the synthesizer Nrrrf Hz(s) = s the loop fiequency lt+rrs1 s'+2dqs+t^t1 flrcte 0n= KoKq N(r' + rr) l5-9 FrequoncY SYnthoelzor Unit {5 o ^ -1 l!-*"-",f =;lK*"t'' . "l Thetransferfunctionoffrequencysynthesizer,H(s),isasecond-order function'$imilartoanysecond-ordersystems,timerJelayisintroduced the output' and overshoot may be occurred at between input and output, MewthestepresponseoffrequencysynthesizershowninFigure15-10 Thefrtistheidealoutputfrequencychangethatfollo.lvsastepchangeinthe inputfrequency,whilethefoisthepracticalresponseofoutputfrequency' of frequency synthesizer Figure 15-10 Transient response how the synthesizer - the settling time or The loop filter decides two things for manycyclestheloopisgoingtoaverage,andthedampingortheabilityof thelooptoacceptnewchangeswithoutexcessiveovershootorpossible filter of Figure 15-9 (Type ll)' oscillation. lf the loop filter is the Rc lowpass thesettlingtimeoftheloopissetbyRlandCl'ToolonganRlCltime fast input frequency changes' constant makes the loop too slow in following ToosmalltheRlCltimeconstantwillnotaverageenoughinputcyclesand jumpstheVCooutputaroundviolently.Thedampingissetbytheratioof RltoR2.SmallorzeroR2(Typel)valuesmaketheloopbounce, overshoot,orevenoscillate'ToolargetheR2valuemakesthelooptake frequency' too long to read just to a new input t5-10 Unit 15 FtgqUqLUy__syttllp$aqt Practical Circuit Description Figure 15-13 shows the entire circuit on the pLL Frequency synthesizer Module. lt consists of the following sections: l.Reference Frequency section 2.PLL section 3.Divide-by-N Device section 4.Divide-by-1 0 Device section S.Offset OSC section 1. Reference Frequency section The reference frequency seclion consists of a crystal reference oscillator and a frequency divider. The 1-MHz quartz (x'TAt.1) and the Nor gate (u4a, 74HC04) form the precision oscillator. Three BCD counters (U1-U2-U3, 74LS90) are connected to construct a divide-by-1000 divider. The output signal of reference oscillator is connected to the input of the divide-by-10O0 divider via Nor buffers (U4b and u4c). The output to signal frequency of the divider at U1 oA is therefore equal 1000KHz+1000=1 KHz Another output frequency from 1000KHz+100=10KHz. Besides the additional JK frip-flop (U5a, 1t2T4Ls76) is constructed as a divide-by-2 divider and its output frequency at e may be fe=g.56Hz or u2 eA is SKHz when its clock input connected transistor u6. to 2 or 1, respectively. The Q1 is interfacing the TTL output of USa to the cMos input of 15- 12 yr{!esizer ynthesizer I 11 il rtt t'jj*I"' irS&r Ecc.l -= ua 74HCO4 RJ JLTPII RI CJi(nP ti( 2.2X nl G! l oscillator NOT gate counters 100 divider. F.bEFilq$q +la/ fr vnr 11 l.=J '33t a. o tt Rtt IK 57 s-2 - rput of the nt RE 22r O{ he output equal to Cl0 O.ls T +5v 1",. l't r! 0=10KHz. rcted as a 3.5KHz or 1z.tx ult lt' utz 7+HCO+ urz F7x-foil I ely. The x'rA[2 S input of .+A GilD +lll ooo _Llr@ .:rtli lr ,: cl2 ; N Dido OlL.a OllC Figure 15-13 KL-93005 module Unit 15 Frequency Synthesizer 2, PLL section PLL circuit consists of a phase comparator, lock indicator, VCO, and LPF The UG (CD4046) containing turo phase comparators ancl a VCO is the heart of PLL. The CD4046 has two possible phase comparators. One is an Exclusive'OR System that offers good noise performance, but is harmonic Sensitive and must have square waves on both pins 3 and 14' It is limited to a narrow frequency range. The other system is a logic frequency/phase comparator that operates over a wide frequency range (1000:1 or beyond), accepts any input duty cycle, and is not harmonic sensitive. lt has relatively poor noise rejection' This system of the wideband phase comparator is selected in the P[-L section. Two input signals of the phase comparator are: (1) the reference signal fp on TP4, and (2) the feedback signal fp coming from the programmable divider output on TP8. The wideband phase comparator provides a tri-state sample-and-hold outp.rt on pin 13 for the loop filter. lf the input frequency is higher than the VCO frequency, a steady high output results. lf the input frequency is lower than the VCO frequency, a steady low orrtput results. lf the two frequencies are identical, the phase comparator outputs a pulse proportional to the phase difference. This pulse is positive going for lagging VCO phase and is negative going for leading VCO phase as shown in Figure 15'14. lf the reference signal leads the feedback signal, the phase comparator outputs a high pulse charging the capacitor C8. lf ihe reference signal phase lags behind the feedback signal, the phase comparator outputs a low pulse discharging the capacitor C8. lf the twrr phases are equal exactly, the output of phase comparator presents high impedance and the charges on capacitor CB are held. The loop filter, constructed by resistors RG and R7 and the capacitor C8, determines two things: (1) the settling time, or how many cycles the loop is going to average, and (2) the damping, or the ability of the loop to accept new changes without excessive over shoot or possible oscillation. The l5-14 Unit l5 Fr qqe1qy_ _Sy{legi1e,r During the PLL locked, UO pin 1 presents a high level which enables the transistor Q2 conducting and turning on the lock indicator and turn the lock indicator LED1 off if the PLL unlocked. LED1. On the other hand, a low level will appear at U6 pin 1 to disable the transistor Q2 The VCO frequency extremes are determined by the capacitor (C4, C5, or C6) between pins 6 and 7, the maximum frequency resistor (VR2) on pin 11, and the minimum frequency resistor (VR1) on pirr 12. Expressing in equation form gives fi,rrru= frvrex= 1 A/R2(C4-6+32PF) A/R1 (C4-6+32pF)+fn,rrr.r 1 fo=(furnx-furr.r)/2 where funx-turrH is referred to the lock or tracking range of VCO. +N Device section The VCC output signal is connected to the cascaded programmable divider (U10, U9, U8, SN74192) via the level shifter Q4 that converts CMOS level (VCO outpui) to TTL level (divider input). Each synchronous up/down decade counter SN74192 is used as a down counter whose outputs are preset by thumbwheel BCD outputs and load input signal. BCD inputs , When a low (0) presents at load control input (pin 11), the BCD inputs (pins 15, 1, 10, and 9; thumbwheel BCD outputs) are loaded into the decade counter. When input oulses reach at the down-count input (pin 4), the counter counts down and the borrow output (pin 13) produces a pulse as the counter underflows. Fer example, the three down counters U8, U9, and U10 are presetto2,1, and 3 by the hundreds, tens, and units thumbwheels, respectively. Each input pulse to the units counter U10 pin 4 results in a decrement of counter values. After 213 input pulses, an output pulse erppears at U8 pin 13 (borrow output). The borrow output pulse (low) is connected to the l5- l6 hesizer setfling time of the loop is set by R6 and rd LPF. ) is the C8. Too long an RC constant makes the loop too slow in following fast input frequency changes. Too small an RC constant won't average enough input cycles and jumps the . One \lCO output around violently. The damping of the loop is set by the ratio but is rnd 14. d b R6 to R7. Small or zero R7 values make the loop bounce, overshoot, gTen oscillate. Too large an R7 makes the loop take too long to read just a new input frequencY. a logic I range rrmonic of the ignal fp nmable rides a e input results. D tr3l dy low parator ulse is rtshffi l-13) leading parator , signal tputs a ,q!d r equal rnd the Ffu lHd Llrdf lftr) tor C8, loop is accept F€tre 1Fl4 Phase corhparator waveforms n. The I_q-t5 1!y4!hesizer thesizer enables the lod inputs of these three counters to reload the value 213 into the counters and then the counting sequence runs repeatedly. emmple, the cascaded decade counter is a divide-by-2l3 counter. D1. On the ln this fansistor Q2 Fgure 15-15 shows the operation of BCD thumbwheel. r (C4, C5, or lf the tr.rnbwheel is switched to the decimal figure 5, the outputs C= A=1 and yR2) on pin F84, therefore the BCD value 0101 is loaded into the programrnable xpressing in oounter SN74192. Ttre output pulse of the programmable divider (U10-U9-U8) is sent to the lput ilIse of phase comparator via a JK flip-flop (Usb). The reason is that the width is too narrow to drive the phase comparator. For the same reason, a JK flip-flop (U5a) is added to the reference frequency section. ogrammable tat converts J as a down rts and load mntrol input CD outputs) each at the lnow output @t*rr eset to 2, 1, X = output connected to common 0 = open vely. Each input lcrement of rears at U8 ected to the circuit Fgtre 1.}15 BCD thumbwheel operation l5-17 Unit t5 Frequency Synthesizer 4. +10 Device section A frequency synthesizer with precaler is simply made by adding a frequency divider (prescaler) to the input of the programmable divider in typical frequency synthesizer circuit. The use of prescaler promotes the output signal frequency fo of the synthesizer but keeps the input frequency to the programmable divider compared with typical frequency syntnesizer. ln Figure 15-13, the decade counter U7 (SN7490) serves as a prescaler with the scale of step 10. By the use of precaler the frequency lF will be increased to 10 times the reference frequency. Offset OSC section See Figure 15-13. The D flip-flop (U11, SN7474) serves as a mixer. The inverters (U12) and crystal (X'TALZ) form a local oscillator whose output is connected to the D input of the mixer. The VCO output frequency fo is shifted to a lower frequency via the mixer for suitable the programmable divider calculated by input. The output signal frequency of the mixer is f6,r=f9-fL where fr is the local oscillator frequency. l5-18 rthesizer Froqualtcy Sytttltcsizcr REQLIRED rdding a livider in rotes the '-, lsth.h KL-92001 8-!$dure KL-93005 S -@sc*hrccope re input equency r) serves rT5.L\-D RECORDS $.prcat Freq u e n c y S ynth -nl' -re cors,truct es i z e equency r a typical frequency synthesizer, the following circuit a Eec$oms are necessary. mtxer. ,L. rr whose Rderence Freq uency section ) output table the fl-L section DnurGby-N Device section mixer is L.m,te these sections on the PLL Frequency Synthesizer Module. I. :ffirence tfrequency measurement lit , Ftace a jumper in position 2. ilE L}ilng the scope, measure and record the lreqrncies on the test points in Table 15-1 . waveforms and $, tmas.rng VCO input voltage vs output frequency characteristic '"; Renroue the jumper from position 2. With power off, set VR1 lCKn and VR2 to 1.4MQ using DMM. d^ to mre j'rnnpers in positions Errrmrrd {VCO 3 and 6. Conne,:t scope CH1 lN to OUT OUT). Connect dc povver supply 0-15VDC from ,ift-92CI01 to TP6 (VCO lN). Measure and record tlre waveforms and iery-rencbs for difierent dc input voltages in Table 15-2. vottage-frequency characteristic in Figure 1 5-1 6 according u Fre esults in Table 15-2. srtrce a jumper in posrtion 7 (VR2 connected). Repeat steps (2) rm 3 recorC the results in Table 15-3 and rlot the characteristic in Fgue iF17 i5- le Unit l5 Frequency Synthosizor 4. Measuring the sigr,al frequencies of phase comparator (1) Place jumpers in positions 2, 3, 6, 7, and 11. (2) Measure and record the frequencies on TP4, TP8, and ouT for various BCD thumbwheel setting values in Table 15-4. (3) (4) 4. Repeat step (2). Remove the jumper from position 4 to position 5. Repeat step (2). Remove the jumper from position 3 to position programmable divider 5. Measuring (1) Place jumpers in 2,3,6,7, and 11 positions. on u10 pin4 (fin), TP7 (fout), (2) Measure and record the frequencies and TP8 for various BCD thumbwheel setting values in Table 15-5. Calculate and record the ratio of fin to fout in Table 15-5. (3) Remove the jumper from position 3 to position 4. (4) Remove the jumper from position 4 to position 5' Repeat step (2)' Repeat step (2). 6. Measuring transient response of frequency synthesizer (1) 2,5,6,7, and 11 positions. (2) Connect scope input to TP6. Measure and record the transient ' response curve of the frequency synthesizer for each sudden change in input frequency in Table 15-6. Measure and record the Place jumpers in settling time for each transition in Table 15-6. To produce a sudden change in input frequency, from 300KHz to 400KHz for example, first set BCD value to 300 (300KHz) and then switch hundreds thumbwheel to 4 (400KHz) suddenly. (3) Connect a 1OpF capacitor between TP6 and ground. Repeat step (2) and record the results in Table 15-7. I s-20 Synthesizor nd OUT for Et step (2). M Pos: 20,00,tts CUHSOF Type at step (2). Source ru Delta 1,000ms 1.000l,Hr VW7 I (fout), Cursor 1 r Table 15-5. -1,020ms Cursol ? -20,1]0r's nt nt step (2). step (2). n 300KHz to Fts) and then r5-2r Unit 15 Frequency Synthesizer Experiment 15-2 Frequency Synthesizer withPrescaler 1. Place jumpers in positions 2, 3, 6, 7, B, and fn=Q.5KH2, P=10. 12. This step constructs a frequency synthesizer with prescaler as shown in Frgure 15-4, and sets 2. Measure and record the signal frequencies on OUT, U7 pin1, and U7 pin12 for various BCD thumbwheel setting values in Table 15-8. 3. Compare U7 pinl signal with OUT and record the phase shifts of U7 pinl signal in Table 15-8. 4. Compare U7 pin12 signal with OUT and record the phase shifts of U7 pin12 signal in Table 15-8. 5. Remove the jumper from position 3 to position 4. 5 Repeat steps 2 thru 4. 6. Remove the jumper from position 4 to position Repeat steps 2 thru 4. y Synthesize.r Frequency Synthesizer Synthesizer with Frequency Conv erter , constructs a 5-4, and sets inpers in positions 2, 5, 6, 7, 10, and 13. qffiesizer with lowering frequency l5S, and sets fp=Q.5KHz, f1=l[1492. This step constructs a converter as shown in pin1, and U7 f: scope or frequency countel measure and record the output il'. lfts of U7 d pinl local oscillator on TP9. fiequency fl = rtd r shifts of U7 record the frequencies on OUT (fo) and U11 pinS for various setting values in Table 15-9. on U11 pinS should equal to the output frequencies minus - mcillator ftequency, fe-f1. leps'2 thru 4. : teps 2 thru 4. l5-23 Unit 15 Frequency Synthcsizcr Table 15-1 Reference frequency measurement Waveforin ynthesizcl i:i lltrO inptrt voltage vs output frequency characteristic l tr", hr*R*nn F" lit*-' OUT Waveform & FrequencY (KHz) Output o o5 N EE-' ti 15 F.* i2 2!-5 F= 3 35 ---i, , F' 1 i r r-s F'- T'g 55 5 F- h. 65 iF- T t*- ils I f* >+ -' - rF I ot w r Iro ts-25 Unit l5 Frequen_cy _Synfheg [e r Table 15-3 VCO input voltage (VR2 connected) vs output frequency characteristic TP6 lnput dc Voltaqe ru) 0 OUT Output Waveform & Frequency (KHz) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 I 9.5 10 ry sy1_t!e5qe1 23156789101112 lF'nG Arput lnput Voltage (v) frequency vs input voltage characteristic 2.3456789101112 lnput Voltage (v) ls'17 Ortput frequency vs input voltage characteristic Unit t5 frequmcy Syntheiaer. Table 15-4 Phase comparator frequencies Frequency Synthesi2er ,lfrllmeasurement Froquoncy Sy:tlhooirar Table 15-6 Transient response of frequency synthesizer lnput Frequency (KHz) Transient Response Settling Time 100 to 200 200 to 300 300 to 400 400 to 500 500 to 600 600 to 700 1 5-30 Syntltooizor Frequency $Yntheqizqr ffilrrccurement Unit 15 Frequency Table 15€ Transient response of frequency synthesizer lnput Frequency ffil-iz) Transient Response Settling Time 100 to 200 200 to 300 300 to 400 1 I I 'tl 400 to 500 l ii 'l I lL 500 to 600 1 ii i i l ii i.i''l' ir, iii il 600 to 700 I il t' il t 5.30 Unit l5 Frequency Synthesizer' Table 15-8 Frequency synthesizer with prescaler U7 pin12 with frequency converter qJT heryency U11 pinS 0Frequency Unit l5 15.5 QUESTIONS 1. Describe the function of JK flip-flops (U5a, USb) in reference freq and programmable divider sections. Describe the requirement of tne input signals to phase comparators cD4046. 3. What is the frequency range of VCO in PLL section? I 5-34