[IEEE Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan (June 3-5, 1997)] Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - Optimization Of Tilt-implanted Punchthrough Stopper On Short-channel Behavior In Quarter-micron Mosfet With Low-concentration Wells

Optimization of Tilt-Implanted Punchthrough Stopper on Short-Channel Behavior in Quarter-Micron MOSFET with Low-Concentration Wells Chih-Hsien Lin*, Jiunn-Jer Yang", Konrad Young*, and Kuang-Yi Chiu* Winbond Electronics Corp., Science-Based Industrial Park, Hsinchu, Taiwan Abstract In this work, the tilt-implanted punchthrough stopper (TIPS) in 0.25 um dual-gate device is optimized with respect to threshold voltage roll-off, drain induced barrier lowering (DIBL), minimal gate length (Lmin) @ Ioff=l OpA/um and drive current Idsat, with or without conventional anti-punchthrough (APT) stopper implant. The optimization methodology is based on the performance of nominal devices with strong devices meeting Ioff specs. We found that threshold voltage roll-off was greatly reduced by large-angle TIPS implant in both N- and P- MOSFET's. The optimal device design is low dose APT- plus-TIPS for NMOS and high dose TIPS only without APT for PMOS. Both conditions reduce gate length sensitivity of threshold and yield lower nominal threshold, resulting in higher nominal drive current. Introduction As the CMOS devices keep scaling down, source to drain punchthrough and Vt roll-off are the main limitations. Vt roll-off causes a significant off-state leakage current owing to the reduced leakage barrier between source and drain. In order to accommodate the Vt roll-off phenomenon and suppress Ioff at strong devices, Vt at nominal devices must be raised to a certain high value which in turn degrades the drive current. Tilt-implanted punchthrough stopper, featureing a local pocket implantation adjacent to source and drain ( S D ) regions, was proposed to increase punchthrough immunity and suppress short channel effect (SCE) in deep submicron MOSFET's, allowing a smaller Vt at nominal device while still keeping Ioff to a certain acceptable level.[l-31 In this work, we investigate the optimized TIPS implant conditions for 0.25um dual-gate MOSFET's with or without conventional APT stopper implant. Considerations for optimization include the suppression of Vt roll-off at Vds=O.lV and 2SV, drain induced barrier lowering (DIBL), minimum channel length (Lmin) meeting Ioff specs (10pAhm) and Idsat at nominal device. Experiment Conventional twin-well dual-gate CMOS transistors were fabricated with gate oxide thickness Tox=60A (from C-V measurement with gate accumulated at IVgbl=3V). APT implant dose is varied to adjust long channel threshold. After gate patterning at Lgate=0.25um, gate reoxidation was performed at SOOC to grow approximately 60A oxide on Si wafer. TIPS implant was then performed using the same mask process with LDD implant. The doses of BF2 TIPS implant for NMOS are 1.5, 2, and 2 . 5 ~ 1 0 ' ~ cm-' at either 100KeV-30D (30 degree tilt implant) or SOKeV-15D (15 degree tilt implant) for devices with low- dose APT implant, or 3, 4, and 5 ~ 1 0 ' ~ cm-' at 100KeV-30D for devices without APT implant. In PMOS, the conditions of phosphorus TIPS implant are the same with NMOS. For comparison, APT implant without TIPS implant is performed for control device. A IOOOA nitride was then deposited and etched as sidewall spacer followed by S/D implant. Gate doping was done simultaneously with S/D implantation to simplify process sequence and reduce fabrication cost. Poly depletion effect was minimized by optimizing S/D RTA annealing condition ( IOOOC or higher). TiSi2 was formed by two-step self-aligned RTA salicidation utilizing Ti of 300A afterwards. The temperature for backend process was limited to 8OOC. Results and Discussion Fig. 1 shows the schematic cross-section view of TIPS and APT implantation. Uniform high doping concentration along channel is achieved by blanket APT implantation, while TIPS produce a local peak concentration. Fig. 2 and 3 show the NMOS linear threshold (Vt-lin) and saturation threshold (Vt-sat) versus gate length for different types of device structure, (1) APT only, (2) TIPS only and (3) APT plus 30 degree TIPS implant. Vt-lin was measured at Vds=O.lV, and Vt-sat at Vds=2.5V. All devices have the same Vt adjust implant, while APT and TIPS implantation increase long-channel Vt slightly. The APT-only MOSFET has higher APT implant dose than the APT-plus-TIPS * Currently with Worldwide Semiconductor Manufacturing Corp. 303 device in order to achieve similar Vt-lin values at nominal device. The TlPS implant dose is 4x10'2cm'2 for TIPS-only and 2 . 5 ~ 1 0 ' ~ cm-2 for APT-plus-TIPS NMOSFET's. The data shows that reduced Vt roll-off is achieved by 30 degree TIPS implant regardless APT stopper. In TIPS-only device, strong reverse short channel effect (RSCE) and rapid roll-off are observed. Vt-lin for APT-plus-TIPS-30D MOSFET remains nearly constant down to Lgate=0.2 um. To further investigate the effect of TIPS dose and tilt angle on TIPS-plus-APT NMOS, Vt-lin characteristics with doses of 1.5, 2, and 2 .5~10" cm-' at 30 degree tilt, or 2 ~ 1 0 ' ~ cm-* at 15 degree are plotted in Fig. 4. With 30 degree tilt, doses between 1.5 to 2 . 5 ~ 1 0 ' ~ cm-* does not have significant influence on Vt-lin behavior. However, the result shows that, for 15 degree tilted implant, the localized anti-punchthrough pocket does not have enough lateral extension to alleviate Vt lowering. Fig. 5 shows DIBL effects versus the gate length. DIBL is defined as the threshold voltage difference between linear and saturation regions. APT-plus-TIPS-30D NMOS has the lowest DIBL value because of higher channel surface doping concentration than TIPS-only NMOS , and longer effective channel length than APT-only NMOS for a given gate length. Since the saturation voltage roll-off is directly related to off-state leakage current, Ioff specs determines the required saturation voltage to suppress off-state leakage, which consequently limits the minimum device gate length. The NMOS saturation voltage versus Ioff relationship is plotted in Fig. 6. For Ioff specs of 10pA/um, the required Vt-sat is around 0.4V for all structures. The similar Vt-sat-Ioff relationship indicates the subthreshold swing (gate controllability), mainly determined by the ratio of gate oxide thickness to channel depletion layer thickness, is not increased by additional TIPS implant. With Ioff specs of 10pA/um, the minimum gate length (Lmin) is then extracted from Vt-sat vs. gate length relationship (Fig. 3) and plotted in Fig. 7. The Lmin's are 0.23 um for both TIPS-only and APT-plus-TIPS-30D NMOSFET's, and 0.26um for APT-only NMOS, while with APT-plus-TIPS-1 5D, Lmin is only 0.27um, slightly shorter than the APT-only (labeled as Low APT in Fig. 7), but worse than the high APT-dose device. With Lmin (strong device) meeting Ioff specs, the performance of nominal device (typically 10% longer than the strong device) is illustrated in Fig. 8, which plots the Idsat versus Lg-Lmin. The highest Idsat is achieved with the option of low APT plus TIPS implant. TIPS-only NMOS has smaller nominal Idsat because of higher nominal Vt owing to strong RSCE. very similar roll-off behavior is seen as in APT-plus-TIPS PMOS. Small RSCE is observed and good SCE is achieved in TIPS-only PMOS with small long channel threshold. Therefore, TIPS-only nominal device has a smaller Vt, which will cause a larger nominal Idsat. Fig. 11 shows the PMOS DIBL effect versus gate length. Similar to NMOS, APT-plus-TIPS PMOS has lowest DIBL, but only slightly smaller than TIPS-only PMOS. Therefore TIPS implant is the dominant factor to reduce saturation roll-off for PMOS. Again, to obtain the PMOS minimum gate length meeting Ioff specs, saturation threshold and Ioff relationship is plotted in Fig. 12. For Ioff specs of lOpAhm, IVt-satl is about 0.43V for all structures, slightly larger than that in NMOS. The minimum gate length Lmin for PMOS can be extracted from Fig. 10 and plotted against various device design as shown in Fig. 13. Both APT-plus-TIPS and TIPS-only PMOSFET's achieve similar Lmin of 0.25um. Fig. 14 which show the characterization of Idsat versus Lg- Lmin for PMOS. In contrast to NMOS, TIPS-only PMOS, without significant RCSE, has larger nominal Idsat than APT-plus-TIPS PMOS, mainly attributed to the lower nominal Vt. Summary In summary, we investigate the optimization of TIPS implant with or without conventional APT stopper implant for 0.25um dual-gate CMOS. We found that TIPS implant is a very effective way to reduce threshold voltage roll-off, improve gate length sensitivity of Vt and reduce minimum gate length for a given Ioff specs. The optimization is based on Vt sensitivity and nominal Idsat. In NMOS, the optimal condition is low dose APT stopper plus TIPS implant, while in PMOS, the optimal condition is high TIPS dose without APT implant. Both optimal conditions for N- and PMOS yield smaller Vt in nominal device, thus higher Idsat. Reference: [l]. C. Codella et al., IEDM Tech. dig. 1985, p.230. [2]. T. Hori et al., IEDM Tech. Dig. 1988, p. 394. [3] . C. Duvury et al., IEDM Tech. Dig. 1990, p. 215 PMOS Vt-lin and Vt-sat versus gate length are shown in Fig. 9 and 10 for the same device design as NMOS. The TIPS implantation condition is lOOKeV-4e12-30D for TIPS-only PMOS, and 100KeV2.5e12-30D for APT- plus-TIPS PMOS. As in NMOS, additional TIPS implant alleviate Vt roll-off from APT-only PMOS. In TIPS-only PMOS, unlike NMOS which has rapid roll-off behavior, 3 04 Gat e Fig. 1. Schematic cross-section view of APT stopper and TIPS in a MOSFET. 0.8 -1 I 5' 0.2 t , 1 OTIPS only , ~ 1 0.15 0.25 0.35 0.45 Lgate (um) A APT plusTlPS 0.0 Fig. 2. NMOS Vt-lin behavior vs. gate length for APT- only, TIPS-only, and APT-plus-TIPS(30 degree) design. 0.8 I Vds=2.5V 0 0.0 1 ' ' I 0.15 0.25 0.35 0.45 Lgate (um) Fig. 3. NMOS Vt-sat behavior vs. gate length for APT- only, TIPS-only, and APT-plus-TIPS(30 degree) design. 0.6 ~~ h 2. .- c0.4 - - 0.2 - - - 0 - 0.15 0.25 0.35 0.45 Lgate (um) Fig. 4. NMOS Vt-lin characteristics for APT-plus-TIPS(30 and 15 degree) 0.21 0.23 0.25 0.27 0.29 Fig. 5. NMOS DIBL values vs. gate length for APT-only, TIPS-only, and APT-plus-TIPS(3 0 degree) design. Lgate (um) oTIPS only 0 AAPT plus TIPS 1 0.0 ! " ' '7 1E-1 IE+O 1E+1 1E+2 1E+3 loff (pA/um) Fig. 6. NMOS saturation voltage Vt-sat vs. Ioff. For Ioff specs of 1 OpAium, Vt-sat is 0.4V approximately. 0.3 h v 5 0.25 E K -1 .- 0.2 + LOWAPT ! \High APT \ 0 \\ Fig. 7. NMOS minimum gate. length (Lmin) with Ioff -1 - VdS=-O.IV I I +APT only -0.8 I -0.8 - h 2 - 0 . 6 - - -0.6 h 2. c 2 -0.4 + I Q 5 -0.2 4 6 0 TIPS only I .- -I #APT only -0.2 B S .TIPS only AAPT plusTlPS # # 1 AAPT plus TIPS I o i 0 1 ' I 1E-1 1E+O 1E+1 1E+2 1E+3 loff (pAlum) Fig. 12. PMOS saturation voltage Vt-sat vs. Ioff. For Ioff specs of 10pA/um, IVt-satl is 0.43V, slightly larger than that in NMOS. 0.15 0.25 0.35 0.45 Lgate (um) Fig. 9. PMOS Vt-lin behavior vs. gate length for APT- only, TIPS-only, and APT-plus-TIPS(30 degree) design. -1 I Vds=-2.5V 1 0.3 I LowAPT 2 -0.6 Q -0.4 - - c m u) I 5 - - O ' I I -0.2 High APT 0 C -1 .- E I OTIPS oniy 1 I 1 AAPT plusTlPS 1 1 . I . , 0 1 " 0.15 0.25 0.35 0.45 Lgate (um) I 6 ~ ~ ~ o n i y Fig. 10. PMOS Vt-sat behavior vs. gate length for APT- only, TIPS-only, and APT-plus-TIPS(30 degree) design. Fig. 13. PMOS minimum gate length (Lmin) for Ioff of 1 OpA/um versus different device design. 200 150 c cs 100 > m -1 50 a 0 0.21 0.23 0.25 0.27 0.29 Lgate (um) 0 TIPS only h h 3 m v c. $ 240 - - 200 I I 0 0.01 0.02 0.03 0.04 0.05 Lg-Lmin (urn) Fig. 11. PMOS DIBL effect vs. gate length for APT-only, TIPS-only, and APT-plus-TIPS(3Odegree) design. Fig. 14. PMOS Idsat vs. Lg-Lmin with Lmin-0.25-0.27um. TIPS only PMOS has largest nominal Idsat. 306