Abstract—A novel characterization setup for integrated capacitor array mismatch determination is presented. The biasing of twenty capacitor units and the selection of a specific array are controlled by externally generated digital signals. Information about the spatial matching behavior is provided for an entire MIM capacitor array, where the relevant parameters are the standard deviations �(�Ci / C) and the offsets μ(�Ci / C) of units i. Furthermore, the measurement repeatability is determined and an advanced derivation to consider the correlations introduced by the circuit structure and the extraction method is presented. The corresponding test chips were successfully realized in 0.35 um and 0.18 um standard CMOS technologies. Index Terms—DFM, matching, capacitance matching, capacitance mismatch, unit capacitors, capacitance array, floating gate I. INTRODUCTION Precise characterization of capacitor matching behavior is in many cases a key to successful area optimized analog circuit design. The production yield e.g. of charge redistribution ADCs is strongly related to the matching of binary weighted capacitors, where the integral (dual) capacitance ratios are realized by connecting unit capacitors in parallel. A matching characterization technique for such binary weighted capacitors is presented in [1]. Since systematical influences during processing are assumed to be homogenous for the entire array, highly accurate capacitor ratios can be realized when using matched capacitor units. In order to preserve the margin the interconnect wiring and the geometry of capacitor plates have to be designed very carefully to avoid parasitic systematical offsets. In [2] effects are summarized as mismatched perimeter ratios, parasitic interconnect capacitances, mismatch of interconnect capacitances, mismatch of long range fringing capacitances and proximity effects in lithography. Random influences [3],[4] on unit capacitance values are mainly caused by fluctuations of the insulator thickness, the relative dielectric permittivity and by edge roughness effects. The novel test structure presented here is intended to determine systematical and random mismatch for an entire array. Offsets due to an imprecise layout were carefully avoided and results show the influence of processing depending on the position of a certain unit. The goal is to provide information about the spatial matching behavior of the entire array, where the relevant parameters are the standard deviations �(�Ci/C) and the offsets μ(�Ci/C). Both quantities are related to the capacitance mean value C of an array. Ci is the particular capacitance value of a unit, which fluctuates randomly and/or systematically. Standard deviations and offsets are extracted from array data of the entire wafer. II. TEST STRUCTURE For capacitance-pair mismatch determination the floating gate concept [5]-[8] is commonly used. There is a modified structure which applies a differential approach [7] in order to reduce the sufficient number of data points. Investigations regarding leakage currents and their influence on the circuit performance are described in [8]. The test structure presented here is based on the floating gate concept. It uses a capacitance voltage divider and a PFET source follower. New extensions are: a) The number of capacitances (m=2 in [6]) is increased to m=20 units. b) Terminal multiplexing is used to share probe pads. Each unit of the array can be selected by a digital control sequence. c) Several arrays can be implemented in parallel, where each array can be selected by a digital control sequence. d) A low leakage switch is included to predefine the mid node voltage of the capacitance voltage divider. Subsequent explanations refer to the circuit schematics shown in Fig. 3 and Fig. 4. Fig. 1 Layout of the MIM capacitor array. 10 1 2 3 4 56 7 8 9 12 13 14 15 16 17 18 19 20 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10 11 Fig. 2 Mapping of switch index i to the position inside the array. The white squares are dummy capacitors. a) The concept of [6] is extended by using a total number of m=20 capacitors which are connected to the mid point A Test Structure for Integrated Capacitor Array Matching Characterization Werner Posch , Member, IEEE, Gilbert Promitzer, and Ehrenfried Seebacher, Member, IEEE austriamicrosystems AG A-8141 Unterpremstaetten, Austria
[email protected] 152 2010 IEEE International Conference on Microelectronic Test Structures, March 22-25, Hiroshima, Japan. 7.1 978-1-4244-6915-4/10/$26.00 ©2010 IEEE node, MP, of the voltage divider. A p-channel FET source follower M1 is used to decouple the voltage divider with high impedance. During all measurements a constant current IPM is forced through M1 and the divider mid point voltage VMP is mirrored to the source with an additional constant offset due to the gate-source voltage needed to drive the current. M1 is designed using W/L = wide / medium long, which yields a small output conductance gds and a high transconductance gm to gain linearity of the output voltage and a good compensation of IPM current fluctuations. A constant parasitic capacitance CP from MP to ground is included, which considers the direct capacitance from the mid plate to ground, the parasitic wiring capacitance to ground of the mid node and the gate-drain capacitance of the source follower. To hold this assumption the same physical layer is used for all capacitor plates connected to MP. M2 BSM3CP GND SH VPM IPM C1 C2 C3 C19 C20 MP M1 VC2 VC1 VC3 VC20 VC19 Fig. 3 Source follower unit: Ci…unit capacitors, M1…source follower, CP…parasitic capacitance to ground, MP…mid point node, M3…short switch, M2…switch to select the source follower, VCi…input voltages of unit caps, IPM and VPM…source follower source current and source voltage. b) The controlling of the capacitance input voltages VCi is realized via transmission gates which connect each capacitance either to ground or to VC. The input voltage VC is provided externally by the parameter analyzer. c) In order to implement an arbitrary number of arrays in parallel, pad sharing is used for the output voltage VPM at the source of M1. The relevant source follower can be selected by enabling the FET switch M2 in the circuit, whereas no current can pass through unselected source followers due to switches M2 being in the highly resistive OFF state. Both, transmission gates and switches for unit selection and array selection are digitally controlled by the outputs of two serial shift registers (VDD=5V). The input signals of a shift register are reset R, clock CLK, and data D. A serial addressing concept is applied to be independent in pad function assignment if the number of arrays or the number of accessible unit capacitors will be changed in future realizations of the circuit. d) Since significant y-axis intercept variations of VPM versus VC curves were observed for the floating gate structure in [6], a predefined voltage for node MP can be guaranteed if using a switch M3 to ground. The transistor size of M3 was chosen W/L= narrow / long which provides a low leakage current because of increased threshold voltage due to the narrow channel. Furthermore, there is no threshold voltage reduction because of the short channel effect. Additionally, a small width yields a small drain-gate overlap capacitance. VPS MP2 MP3 SF1 SF2 SF3 OE D0 SH D1 ARRAY CAP1 CAP2 CAP3 ARRAY ARRAY MP1 VPF CLK0 RES VCF VCS CLK1 RES SR 1 SR2 BS3 BS2 BS1 S1 S2 S3 D 1− D 20 Fig. 4 Simplified circuit schematic of the chip. SRi...shift registers, Si…switches to control unit cap biasing, MPi…mid point nodes, BSi…digital signals to enable/disable the source follower units SFi. Output voltages VP and input voltages VC use sense/force technique. Fig. 5 Microphotograph of the first chip realized in 0.35 um CMOS technology, center: MIM capacitor array; left, right: poly1-poly2 capacitor arrays. SMU1 − SMU5 GPIB IF PR PC array select unit select TC Fig. 6 Measurement setup: GPIB…instrument interface, 4156C…parameter analyzer; array select, unit select…device selection, IF…interface board, PR…probe card, TC…test chip. III. MEASUREMENTS AND PARAMETER EXTRACTIONS Measurements are executed in an analogous manner as for pair mismatch determination in [6]. If m is the total number of accessible units, then m-1 capacitors are connected to ground and unit i is connected to input voltage VC. The current IPM is forced through the source follower and switch M3 is opened. 153 Then two output voltages VPM1,2 are measured according to input voltages VC1=0V and VC2=5V. The slope ki is calculated by ki = (VPM2–VPM1) / (VC2-VC1). It can be related to capacitances by the voltage divider expression as: P m k k i i CC Ck � � � �1 (1) Differences of relative capacitances �Ci/ are determined by 1�� � � � � � k k k kk C CC C C iiii (2) for each capacitance unit, as shown in Fig. 7. The quantities and are the mean values of m capacitances and m slopes. In this case the differences are referred to the mean value of slopes and capacitances. This approach is advantageous because m (m-1) / 2 correlated differences are found if each unit is compared to each other. Then standard deviations �(�Ci/) and mean values �(�Ci/) are determined for numerous �Ci/ data samples, as demonstrated in Fig. 8 for data of 420 sites. 0 5 10 15 20 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 x 10 −3 ca pa ci ta nc e m is m at ch Δ C i / < C > unit capacitor index i Fig. 7 relative capacitance differences �Ci/ of one array versus unit index i. Measurements (o) were repeated 10 times, (-) mean value. A. Measurement Considerations In terms of data point number it is more efficient to repeat measurements for VC1=0V and VC2=5V and perform averaging if the influence of measurement or system noise is significant. No data is measured for voltage VC being between VC1 and VC2. Since a predefinition of the mid point voltage VMP is applied, the measurement of data belonging to VC1 seems to be redundant. It would be sufficient to determine the value once. It has to be verified that the charge injection during the opening of the short switch M3 has no significant influence. A correlation plot of VC1 data versus VC2 data proves that both voltages fluctuate independently. Measurements for both input voltages are nevertheless advantageous in order to prevent any potential drifts of the mid point MP. A large parasitic capacitance CP decreases the slope value, which leads to increased repetition effort and/or increased integration time to reach a sufficient small resolution of slopes ki. The same holds if the number m of accessible units is increased. Data is measured using a standard parameter analyzer, though the concept can also be adapted for wafer sort test equipment. If additional probe pads for output pins are implemented, parallel testing in addition to multiplexing can also be performed. B. Measurement Repeatability Measurement repeatability is determined by calculating differences of consecutive measurements of the same unit. A histogram of difference values rjkkk jj ,...,4,2,1 ���� � (3) where r=10 is the number of measurement repetitions is shown in Fig. 9. The data contain differences �k for ten measurement repetitions, 20 unit capacitors and 420 sites. Finally, the standard deviation �(�k) can be used to determine the standard deviation of �Ci/ measurement repeatability which is �(��C/). It can be utilized to remove the influence of system noise from �(�Ci/) data as demonstrated in [6]. 0 5 10 15 20 −5 −4 −3 −2 −1 0 1 2 3 4 x 10 −3 unit capacitor index i ΔC i / < C > Fig. 8 (+) Measurement data �Ci/ versus switch index. 420 sites, CMIM array, (-) mean value μ(�Ci/). −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 x 10−5 0 200 400 600 800 1000 1200 1400 1600 slope differences Δ k fre qu en cy Fig. 9 Histogram of slope measurement repeatability �k, 420 sites, one array, 20 units 10 repetitions. 154 C. Consideration of Correlations For the determination of each individual capacitance unit standard deviation �(�Ci/C) an extended derivation is provided: �Ci/ values are correlated a) due to the capacitance voltage divider measurement technique and b) due to 1��� k k C C ii (4) a) Each slope is determined by (1) and therefore fluctuations not only of Ci, but also of the residual capacitances in the denominator influence the value of ki. A Taylor approximation � � � �� � � ���� C C mCCCfk qPmi ,,,..,1 (5) (q=1,..,m) is applied, which can be written in matrix format: � �� � � ����� C C k qqii , (6) (q, i=1...m). It expresses that all fluctuations of slopes depend on all fluctuations of capacitances. The difference � is related to the mean value of each individual unit: � �� � � � � � � �� � � � C C C C C C qqq � (7) b) Since the expression (2) considers data of all slopes, fluctuations not only of ki, but also of the residual slopes influence the result. Again, a Taylor approximation can be applied � � qmi kmkkfC C ��� � � � � � � ,,..,1 (8) (q, i=1..m) which can be expressed in matrix format as qqi i k C C ���� � � � � � � , (9) Effects a) and b) can be combined to � �� � � ��� � � � � � � C C BA C C q qi i ,)( (10) (q, i=1..m), which are linear functions where m output values depend on m input parameters. Since standard deviations should be determined the expression is squared in order to propagate variances, giving � �� � � �� � � � � � C C BA C C q qi i 22 , 2 )( �� (11) The left side of the equation is defined by measurements and the right side can be found by solving the system of linear equations. Since m=20 is relatively large, crosswise correlations and therefore off-diagonal elements of (B A) are small, whereas diagonal elements are close to unity. A large CP additionally reduces the correlation. Anyhow, for m becoming small significant corrections are found between �(�Cq/) and �(�Cq/C). D. Derivation of Matrix Components It must be distinguished between diagonal elements Aii and off-diagonal elements Aij of matrix A. In diagonal elements the relevant selected capacitance Ci is found in the numerator and in the denominator, whereas in off-diagonal elements Cj is found in the denominator only. In order to derive diagonal elements we differentiate � �2 2 1 1 P i P m j Pj i m j Pj i i CCm C CCm CC C CCC k �� � �� � � �� � � � � � � � �� (12) which leads to � � � �� � ��� � ��� � � � 2)1()1( 1 Cvm C CvmC k i i i (13) when using the definition for the ratio v, CmvCP ��� . (14) Furthermore, assuming CCi � gives � � CvmvmC k i i 1 )1( 1 )1( 1 2 � �� � �� � �� � � � (15) which can be rewritten as � � C kk C k i i 2� � � � (16) In an analogous manner we find for off-diagonal elements C k C k j i 2� � � � (17) which yields for components of matrix A: 2 , 2 , , kAkkA jiii ���� . (18) The capacitance C in (16) and (17) is used in (6) in order to get a relative capacitance mismatch �Cq/C, because the differentiation (12) is referred to Ci. In the next steps components of matrix B are derived. Again, it must be distinguished between diagonal elements Bii and off-diagonal elements Bij. For diagonal elements we get kmkkm k kk C C i i i � �� � �� � �� ��� 111 2 (19) where it was assumed that kki � Off-diagonal elements are given by kmkm k k C C i j i � �� � �� � �� ��� 1 2 (20) which yields for components of matrix B: kmkmk jiii � ��� � ��� 1.11 ,, (21) 155 2 4 6 8 10 12 14 16 18 1 2 3 4 5 6 7 8 9 10 x y −20E−04 −15E−04 −10E−04 −5E−04 0E−04 5E−04 Fig. 10 contour plot of mean value μ(�C/), top view, depending on position. The axis correspond to coordinates in Fig. 2; *…measured data. 5 10 15 2 4 6 8 10 −3 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 x 10−3 y x −20E−04 −15E−04 −10E−04 −5E−04 0E−04 5E−04 Fig. 11 contour plot of mean value μ(�C/), perspective view 30o, depending on position. The axis correspond to coordinates in Fig. 2; *…measured data . IV. RESULTS Results for mean values (offsets) and standard deviations of relative capacitance fluctuations are presented for a MIM capacitor array. For both quantities contour plots are provided in Fig. 10 to Fig. 13 in order to show the behavior depending on position. Compared to the border, the array shows an increased capacitance offset in the center. Standard deviation values fluctuate within 10% inside the array, but e.g. the border unit i=10 shows a 50% increased value. V. CONCLUSION This novel test structure allows a joint determination of capacitance mismatch for many (in this case m=20) unit capacitors. Extracted mean values (offsets) and standard deviations provide mismatch data depending on position. Results are presented for a MIM capacitor array in 0.18 um CMOS technology. For standard deviations an advanced 2 4 6 8 10 12 14 16 18 1 2 3 4 5 6 7 8 9 10 x y 6E−04 6.5E−04 7E−04 7.5E−04 8E−04 8.5E−04 9E−04 9.5E−04 10E−04 Fig. 12 contour plot of standard deviation �(�C/C), top view, depending on position. The axis correspond to coordinates in Fig. 2; *…measured data. 5 10 15 2 4 6 8 10 5 6 7 8 9 10 11 12 x 10−4 x y 6E−04 6.5E−04 7E−04 7.5E−04 8E−04 8.5E−04 9E−04 9.5E−04 10E−04 Fig. 13 contour plot of standard deviation �(�C/C), perspective view 120o, depending on position. The axis correspond to coordinates in Fig. 2; *…measured data. derivation was provided taking correlations due to the circuit structure and the extraction method into account. Results led to the conclusion that additional dummy capacitor units have to be implemented at the array border in order to get rid of capacitance value gradients and increased random fluctuations, which will then be found in dummy capacitors. REFERENCES [1] J. L. McCreary, D. A. Sealer, “Precision Capacitor Ratio Measurement Technique for Integrated Circuit Capacitor Arrays,” IEEE Trans. on Instrumentation and Measurement, vol. IM-28, no. 1, March 1979. [2] M. J. McNutt, S. LeMarquis, J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal of Solid-State Circuits, vol. 29, no. 5, pp. 611-616, 1994. [3] J. Shyu, G. Temes, K. Yao, “Random Errors in MOS Capacitors,” IEEE Journal of Solid-State Circuits, vol. SC-17, no. 6, pp. 1070-1076, 1982. [4] J. Shyu, G. Temes, F. Krummenacher, “Random Error Effects in Matched MOS Capacitors and Current Sources,” IEEE Journal of Solid-State Circuits, vol. SC-19, no. 6, pp. 948-955, 1984. 156 [5] C. Kortekaas, “On-chip Quasi-Static Floating-gate Capacitance Measurement Method,” in Proc. 1990 IEEE ICMTS, vol. 3, pp. 109-113 March 1990. [6] H. P. Tuinhout, H. Elzinga; J. T. Brugman, F. Postma, “The Floating Gate measurement Technique for Characterization of Capacitor Matching,” IEEE Transactions on Semiconductor Manufacturing, vol. 9, no. 1, Feb. 1996. [7] J. Hunter, P. Gudem, S. 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Hutter, “Gate Oxide Leakage and Floating Gate Capacitor Matching Test,” in Proc. 2007 IEEE ICMTS, pp. 120-123, 19-22nd March 2007. 157 /ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 200 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages false /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 400 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 600 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile (None) /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False /CreateJDFFile false /Description > >> setdistillerparams > setpagedevice