[IEEE 2006 IEEE International Test Conference - Santa Clara, CA, USA (2006.10.22-2006.10.27)] 2006 IEEE International Test Conference - Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks

Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks Zahi Abuhamdeh TranSwitch Corp 34 Crosby Drive Bedford MA, 01730 781-276-4109 Philip Pears TranSwitch Corp 34 Crosby Drive Bedford MA 01730 781-276-4174 Jeff Remmers Plexus Design Solutions, Inc. 325-1 Boston Post Road Sudbury, MA 01776 Alfred L. Crouch Inovys Corporation 1715 Warwick Way Cedar Park, TX 78613 512-632-1898 Bob Hannagan TranSwitch Corp 3 Enterprise Drive Shelton, CT 06484 203-929-8810 x2331 978-443-1862 x202 Abstract Many modern designs have transient and localized failures which can be attributed to excessive instantaneous power consumption known as dildt or IR drop. IR drop is problematic because power rails may not be sized correctly for the load they must handle in both function and test, and so there might be localized "hot spots. " The current technique for mitigating this issue is at design time, when the power rails are analyzed using tools attempting to predict the actual current spikes and limiting their effect on device performance. This paper will describe a methodology using on-chip process monitoring circuits to help identify and localize IR drop "hot spots. " This methodology will utilize a circuit that is easy to integrate on chip and use in a production environment. Furthermore, a comparison between the predicted IR drop and the actual will be presented. 1. INTRODUCTION Motivation: Current design methodology uses power prediction tools to anticipate and assure power grid integrity before the chip is built. A great deal of design effort is expended in estimating and designing power grids to prevent problems with power distribution - most specifically, IR drop due to dynamic switching. The EDA tools used for the estimation, though accurate in what they model, are typically based on an abstraction of several elements in the chip that affect power consumption. The lack of feedback in this area has prompted an excessive dependence on "tweaking" the key parameters of these tools and almost always required the layout engineers to over design the power rails. In doing so, the layout engineer ends up consuming more precious routing channels than needed. Over designing the power grid has driven the chip designs to more complex timing structures and introduces larger delays on the wiring. This larger delay is due to longer signal routes because routing resources were consumed in power grid design. Paper 21.1 INTERNATIONAL 1-4244-0292-1/06/$20.00 C 2006 IEEE In other instances, the chip would be taped out to fabrication and hope that the trade offs assumed at front end design time were accurate. With the current leading edge silicon technology, the delay and cost associated with a re-spin can drive a company out of business. Causing a re-spin because of an insufficient power grid design is avoided at all costs - resulting in over-design of those grids. With embedded process monitors throughout a chip, it may be possible to actually measure IR Drop within the device. By keeping the external supply voltage stable, the devices junction temperatures stable, and varying the activity level of the chip, process monitor data can create a base line for when the chips diverge from healthy supply voltage levels. If proven valid, this can accomplish two goals: 1) It will create a mechanism to provide feedback to design tools to make the estimation and design process more robust. This closes the loop in an otherwise open-looped power grid design activity. 2) It can act as a production screen looking for excessive IR Drop anomalies in each die. It is also the goal of this work is to accomplish this IR drop measurements by use of simple circuits that are easy to integrate into the full chip, by use of standard digital layout techniques, and with support of a standards-based interface that can be used during production testing of the chip. Background Process Monitors are not new and are not rocket science; they have been used in designs in the past, but for more mundane purposes (the evaluation and feedback of process information for life-testing, yield-monitoring, and TEST CONFERENCE 1 yield-enhancement purposes). Today, however, they are proving to be useful in a great many ways: * They can validate performance information on each die. * They provide an ability to monitor and measure process changes (transistor). * They provide information on the manufactured process corner (best case, worst case, typical). * They provide a method for conducting speed binning [ 1 ]. * They can be used in diagnostics to determine where in the process a device is failing (physical x,y,z; or process step t). For example, for FA labs, one item to log is where in the process variation the failing device falls. * They can be used at wafer, package, board and system test to determine which step is causing a LEand the overall operation of the chip. * And it is proposed that IR drop can possibly be detected [2] [3] in produced silicon devices. Process Monitor Introduction The Process Monitor can be considered to be made up of four functional blocks, defined as 5-bit TCK counter (identifies the measurement window), a ring oscillator (characterized across operating range), a 10-bit ring oscillator counter (counts the ring oscillator output pulses) and a synchronization circuit (synchronizes enabling and disabling the oscillator). These are illustrated in Figure 1 below. Figure 1 The TCK Counter This is a 5-bit counter that counts up to a terminal value of 5'bl 1111. The counter can be reset to zero or loaded with a start value. The ENABLE signal can be defined at the same time as the start (SETUP) value. If enabled, the count will start one cycle later. The SETUP value determines the measurement window for the ring oscillator. The maximum time is 32 TCK periods. At the terminal value, STOP is asserted on the next TCK and remains high until reset or a new SETUP value is loaded. The Synchronization Circuit Two Flops are used, as shown in Figure 1, to asynchronously enable (in phase with TCK) the ring oscillator and synchronously disable it once the TCK Counter has reached its terminal value - that is, two ring oscillator clock periods later. The Ring Oscillator This simple oscillator is shown in Figure 2. An odd number of 2-input NAND gates form the ring oscillator. As shown in the figure, one input is driven from the output of the previous NAND gate and the other input is tied to VDD. An active high Enable signal is added on the first gate. An output buffer isolates the oscillator from an output load. Ninety-nine elements were found to provide an oscillator frequency that was high enough for sufficient count resolution across the operating range, yet low enough to allow the ripple-carry counter to still operate. VDD VDD VDD VDD VDD Ring Oscillator stages Figure 2 Post layout SPICE simulations of this circuit in 0.13um technology resulted in the following range specification: Best Case (fast process, 1.32V, -40C): 190MHz Typical Case (typical process, 1.2V, 25C): 130MHz Worst Case (slow process, 1.08V, 125C): 79MHz Power Consumption Total power consumption of the process monitor was also extracted from spice at < 500uA during its measurement window. The measurement window is expected to be for 3.1 uS. Out side the measurement window, the process monitor's Ring Oscillator is disabled and as such draws very little power. The Ring Oscillator Counter This is a 10-bit counter that is reset to a zero count and counts up as long as it receives clock pulses. The maximum count is 1024, well within the expected ring counter range. It will need to be reset for subsequent counts. INTERNATIONAL TEST CONFERENCEPaper 21.1 2 Placements of Four Process Monitors on a Test Chip The process monitor block was then made into a hard macro. The macro was hardened to ensure that differences due to the layout would be eliminated. Four identical instantiations were placed on a test die. The test chip was a 0.13um process chip that had a significant amount of logic added to it. It was wire bonded and measured over 120mm square in area. The Process Monitor block is small enough in size and did not cause any significant growth or congestion issues. There were four instances of this block placed in such a way as to cover most of the area of the chip. Figure 3 shows the respective placements of the process monitors on the die. PM 1 measurement on the ring oscillator. It is the intention of this paper to describe the process which includes creation of a stable voltage and junction temperature environment around the process monitors; and creation of enough activity on the chip, to try to induce a measurable voltage drop. Ifwe are successful, then we will be able to use this technique to calibrate our IR Drop estimation tools as well as measure IR Drop in a production environment. The remainder of the paper will be organized as follows: section 2 will discuss the test goals and the test setup; section 3 will discuss the data collection; section 4 will present the data and analysis; the paper will be concluded in section 5; future work will be discussed in section 6. PM_2 2. THE TEST GOALS AND SETUP PM 3 PM 4 Test Chip Process Monitors Placement Figure 3 Each process monitor measures 77um X 77um, for a total of 0.03 sq. mm of area for all four process monitors. In the 0.13um technology node, that is less than 3,000 NAND Gate equivalents of usable area. The power grid for the two chips is built using all of the available metal layers in a vertical and horizontal routing pattern. The power routing has a minimum density, and can be expanded to use routing channels not already consumed by functional signaling. Furthermore, all filler cells occupying un-used areas are built out of de-coupling capacitors, connected between VDD and Ground. Using a Performance Monitor for IR Drop Analysis The performance monitor is generally a ring-oscillator that has a natural resonant frequency of operation. The oscillator will change its natural frequency if the process varies significantly (as in best case, worst case and typical process corners). Once the die is built, the operational environment dictates the final operating frequency, based on temperature and voltage. If the chip activity induces a change to the voltage rails, then this too will affect the The monitoring of process is an "after the fact" analysis in most cases and is done by evaluating the chip's response to all applied test vectors. By including a ring- Dscillator, a more direct measurement can be done. Hlowever, the initial operation establishes the baseline Dperation of the oscillator since it is more accurately measured on silicon than estimated on paper. Once the baseline is understood, it can be used to characterize whether chips fall into a "best case", "typical", or "worst vase" bin - and these bins generally represent "fast", 'normal", and "slow" parts (and a corollary is that best- case-fast represents higher background leakage and worst-case-slow is more power conscious). To use the process monitor to understand and characterize the power structure of the chip also requires establishing a baseline value and then noting which activities, and in which localized areas, affect the performance of the process monitor. Since functional vectors are very difficult to assess for power consumption activities, a more efficient method of changing the "variables" and then measuring the result, would be to use structural test - most specifically clocks in scan mode. This mode is the only mode that can guarantee a uniform distribution of power across the chip by driving all the clock trees and all Flip-Flops to the same frequency. Furthermore, this test is very easy to create on a tester, is highly repeatable, and can provide a uniform predictable load on the chip. This test also provides the ability to increase the loading on the chip by scanning-in different scan patterns. For example, a pattern of "00001 11100" will produce a 20% activity level on the Flip-Flops (e.g. the number of toggles or transitions per 100 flip-flops). The chip was fully scanned, and a cyclical input pattern can be easily applied to all the scan chains with fairly good certainty that it will create a uniform activity level in all the FFs. In addition INTERNATIONAL TEST CONFERENCEPaper 21.1 3 the shifting in of targeted logic values will create some level of activity on the combinational data paths which is not easily predicted without a full-toggle simulation. There are techniques that can minimize or eliminate this effect, such as gating the Q-outputs during the shift process, but those techniques were not applied to this chip. Further more, for this paper we did not use any data toggles to increase the power consumption of the part. We relied on the clock trees and drove them to higher clock rates than what they were designed to achieve. This method proved to be adequate at creating a power drain on the supply rails that is with in the expected total core power consumption. It was assumed that the clock trees where uniformly distributed in the die. While in scan mode, asserting Reset and varying the clock frequencies we can achieve one level of power consumption (which basically characterizes the power consumption of the clock-trees). De-asserting Reset and creating various scan shift pattern densities can increase the power consumption of the chip in a predictable manner. Changing these values can quickly establish a pseudo-deterministic or predictable load on the power rails and allow us to vary it in a known or expected manner. Test Setup description The test chip's expected power consumption is 1.7Watts or 1.4Amps at the 1.2Volt Core supply for the 0.13um process technology. This current draw can be exceeded up to 2.8Amps giving us a wide range to push the part past its operational range (the package can handle the excess power dissipation, and these parts are not targeted to go into production). The following are the experiments performed to extract the possible IR Drop in the supply rails: * Baseline measurement of the four process monitors under nominal voltage * Shmoo temperature conditions * Under Reset, vary input clock frequencies while keeping voltage and temperature settings fixed. A thermal bath is used to separate any Temperature effects from the targeted IR drop measurement. For this set of experiments, temperature stability may take as much as 15 minutes to achieve a 95%0 junction temperature stability - it is postulated that the production analysis can be extrapolated by adding back in the effects of temperature once a curve or family of curves has been characterized. After some initial power measurements, it was established that under Reset, over driving the clock trees with higher clock rates created a power drain that was equivalent to twice the power requirement of the chip during normal operation. Since the clock tree is distributed evenly through out the chip, it was a good way to stress the power rails and create a steady state power consumption situation for our experiments. 3. THE DATA COLLECTION PROCESS The result of the data collection process is a series of sets of ring oscillator counts per test configuration. The series consist of the full 4 process monitor count readings every lOms or so for the duration of the test (Sample speed is software dependent, and was not running in real time). A configuration is the operation of the chip at some fixed frequency, voltage, and temperature and then inserting a predetermined change whose affect on the process monitors was to be measured. This section of the paper will explain the test configuration and the data collection process. It is common knowledge that the level of activity in a die can change its junction temperature. The more activity and power consumption the die has, the higher its temperature will be. This temperature difference directly affects any PM readings since it will be reflected in the speed of the part, and as such will cloud any measurements of IR drops. So the effect of temperature on performance has to be separated and excluded from any voltage drop reading. To separate the effects of temperature, we will assume that a thermal source is present in the die when the chip is operational and consuming a significant amount of power. We will also assume that as soon as you stop this activity, this thermal source will be removed. This rate of die temperature change is key - if it is slower than the IR drop effect then we can separate the two with a reasonable certainty that we are measuring IR drop only. If the temperature change is faster than the IR drop change, then our PM circuit might not be suitable to do the IR measurements, and a more sophisticated circuit will need to be constructed. The first experimental measurement is the rate of change in thermal response of the die due to removal of a thermal source. This experiment will take a die from an elevated temperature and drop it to a lower temperature. The rate of change will be measured. A thermal bath does not have the same characteristics of the on-die thermal source, but by removing both sources we can use it to measure the cooling speed of the die. The second experiment is the measurement of the die going from high activity and high power consumption, to no activity and low power and then back to high activity INTERNATIONAL TEST CONFERENCEPaper 21.1 4 and high power consumption. This is the central experiment to this work since here is where we expected to observe the effects of IR Drop. By driving the clocks to 200MHz, we can create enough power drain on the power rails that is equivalent to two times the normal power consumption of the part. It is important to note that this power consumption is distributed evenly through out the die. The total power and distribution are important to stress the part beyond normal operating conditions. Once the clocks are turned off, the reaction of the PMs is investigated. Since the die heat sources have been turned off, the die should start drifting back to ambient temperature. The direct values of the PMs, and their subsequent values will show us where on the curve the thermal components are added, and where the Voltage drop from IR affects is added. 4. EXPERIMENT DATA 4.1. Base line Temperature Response of the Chip: Figure 4 shows the thermal response of the die when it is cycled from 25C to -40C. The graph shows all three monitors extracted at approximately lOims. Also shown is the state of the test using 'Switch -40C' and 'Reach - 40C'. When 'Switch -40C' is turned on, it is when the temperature setting was switched from 25C to -40C on the thermal stream. When 'Reach -40C' is on, that is when the thermal stream reached -40C. total diffirence is 400. That is consistent with the expected variation due to this type of temperature change. The thermal stream deployed[7] here was able to inject air with a temperature of -40C on the die with in 40 seconds from when the new temperature was set. The rate of change the die and the ambient air experienced is very limited due to the low thermal conductivity nature of Silicon[8], and the need for high level of thermal mass to move the temperature around. Figure 5 shows the expanded view of the highest slope of temperature change the die experienced. This slope is extracted to show a single count change in 1 second. That is the fastest rate of change for the count value based on temperature change. T~It CM I Figure 5 From this data, it seems the thermal component of cooling a chip is slow. It is approximatly 1/380 per second. 4.2. IR Drop Measurement: To measure IR Drop, we pushed the chip into a significant distributed power consumption mode and then turned off the power draining activity and idled the chip. Figure 6 shows the PM measurements for the chip in full throttle consuming 2.4Amps, and when it goth throttled back to idle consuming The signal 'Stop Clocks', is exactly the location at which the tester actually stopped applying the clocks. From the plot it is clear that there is a sharp increase in PM count values. Figure 7 shows a detailed plot of the area of interest, just when we turn off the clocks. ZeOOdi Cc TM O 420 ,D ,D D D_D40 iM t0;WIo%f F4.f- Figure 7 The source data is presented in Tables 2 & 3. Table 2 represents the actual PM readings. Table 3 represents the percent diffirence from a base line ofPM readings during a thermally stable clock toggeling state at time 0.301ms, and when the clocks where turned off. It is important to consider the percent diffirence here since absolute diffirences can be attributable to process variation on the die since the PMs are hard macros replicated on diffirent locations on the die. Time PM1 PM2 PM3 PM4 Clocks 0.301 402 401 414 422 On 0.311 402 401 414 422 On 0.321 419 419 436 438 Off 0.331 421 421 438 441 Off 0.341 421 421 438 440 Off Actual PM Values Table 2 Time PM1 PM2 PM3 PM4 Clocks 0.301 000 000 000 000 On 0.311 00o 00o 00o 0o% On 0.321 4.2% 4.50o 5.30o 3.8% Off 0.331 4.70o 5.00o 5.8% 4.50o Off 0.341 4.70o 5.00o 5.8 o 4.30o Off Percent Increase ofPM Values Based on the 0.30 ims Sample as a base line Table 3 As can be seen from Figure 7, the count values jumped by a count of 20 in less than lOms. Since when we turn off the clocks we are also removing the clock source, we expect the counts to drift higher by 1 count every second. It actually changed every 1/3 of a second. This change indicates that the temperature was hotter than what we started with in the initial thermal cycling measurement. Still the fact that a count of 20 change was observed in 1Oms, is purely attributable to IR drop. Error margin is probably in the +/- 1 count. 4.3. Expected vs. Actual IR Drop Table 1 shows count values of the 4 PMs when the chip was at idle and when operated at 100MHz scan clocks. The measurments were done under a thermal stream set to a temperature of 25C. The table also includes the percent difference of counts between those two states. The chip at the 100MHz clock rate was drawing the approximate equal amount of current as what is expected during normal operating mode. As the table shows, there was a diffirence in the over all trend of when the IR drop was experienced. Since this is a wire bonded design, the center area (PM3) experienced the most amount of relative drop in value when operated. Idel 100MHz 00 Diff Current 0.03A 1.48A PM1 406 398 2.0% PM2 409 400 2.2% PM3 396 386 2.5% PM4 403 395 2.0% Table 1 Figure 8 shows the predicted IR drop distribution during normal use. PM_2 V... mm AL W3" PM 3 PM 1 I... F... .D... Figure 8 INTERNATIONAL TEST CONFERENCE p-, o""", 0 46 74 r4b *I r4h dj & r* MI, * r4i & r-O r& 16 r* rM Paper 21.1 6 The tool was run on the actual physical power distribution structure, and assumed an evenly-distributed current load on the grid. This is exactly what we were able to mimic using the scan clocks since they went to every Flip-Flop and RAM in the design. Both the clock distribution network and the FFs acted as a distributed current load matching the tool. The tool predicted IR drop was in the 2-3% range, and we measured 500 (expected double the predicted since we loaded the chip with twice its normal load). The center hot spot is confirmed by PM3 which is located close to the center. 5. DISCUSSION OF RESULTS As can be seen from the data collected the value of the counter changed rather quickly when the level of activity was modified. This change in activity resulted in an observable count change within a lOms measuring window. Further more, the percent difference in count values matched the expected IR drop predicted by the front end tools. The count difference was achieved fast enough that temperature could not have contributed more than 1/380 to the error of the measurement. As such, it is believed by us that it was an accurate measure of IR drop. Furthermore, a production version of this test is also possible. By using this same circuit and selecting a suitable clock(s) frequency that reflects the upper spectrum of the power consumption of the part. Taking two measurements back to back, when the clocks are on and off can present the difference percentage of IR drop the die can experience. This percent difference in the counts can be checked that it is with in the expected range of the frond end tools. A production quality test can be built based on these assumptions, and an effective screen can be put together that can validate the power grid integrity. 6. FUTUREWORK The IR Drop measured was an average value, not an instantaneous voltage spike. The monitor as it is today is not dynamic enough to observe a short-period spike. It would be great to build a circuit that monitors the max/min range of the voltage during the measurement period. Future devices may also have a scan structure specifically made to allow the measurement of the clock-component (no toggles); the sequential component (toggles in flops- only); and the combinational component. These can be done in an additive manner by applying the same patterns and subtracting the previously measured values (combinational logic power consumption is what is left when the clock-tree and the sequential components are subtracted from an "all-logic" measurement). In this design, we were restricted from placing a Process Monitor on all four corners of the die and in the center. In a future device, this will be the goal. In addition, there was an epiphany of sorts with an extreme measurement (100% toggle at 200MHz) that the counter used to do the measurement could be affected and corrupted by the IR drop of the logic being measured. By putting the PM on a separate supply rail, we can eliminate this possibility and it may minimize the need to subtract temperature effects in the counter. The analysis was focused in calibrating the front end design IR Drop analysis tool with the actual silicon results. However, what is more relevant is the actual IR Drop during normal operational clocking and data transactions. This type of analysis is too sophisticated for the front end tool and can only be done in silicon. One of the future works from this project could be to perform these IR Drop measurements using real clock frequencies and stress full data loads to find out what the operational IR Drop will truly be. 7. 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