Cell-Based IC Physical Design and Verification with Astro 陳麒旭
[email protected] Cell-Based IC Physical Design and Verification with Astro Design Setup General Astro Flow Design Setup Design Setup Gate-level Gate-level Netlist Netlist Floorplanning Floorplanning Timing Setup Timing Setup Placement Placement GDSII GDSII Layout Layout CTS CTS Routing Routing Design for Manufacturing Design for Manufacturing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Unit1 Unit1 Unit2 Unit2 Unit3 Unit3 Unit4 Unit4 Unit5 Unit5 Unit6 Unit6 Unit7 Unit7 1-2 What does Design Setup entail? Library Data Technology File Reference Libraries Design Data Gate-level Netlist Timing Constraints Starting Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-3 Design Setup Create Design Library Library > Create Attach Reference Libraries Read Netlist Expand Netlist Open Design Library & Create Starting Cell Bind Netlist to Cell Preserve the Hierarchy Save Starting Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-4 Create Design Library A design library is a container that holds or points to all of the logical and physical data A technology file must be specified when creating a design library; it contains: Layer definitions Via definitions Process design rules (example: min width/spacing) TLU parasitic capacitance models Preferred routing directions GUI display info (example: color and fill of layers) Units, example: time, capacitance, distance Astro’s design library utilizes Milkyway database Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-5 Unix Structure of Design Library Library Name LM LM views NETL EXP CEL FRAM TIM lib lib_1 lib_bck Design Cell CHIP.NETL CHIP.EXP CHIP.CEL CHIP.FRAM CHIP.TIM CHIP CODEC inv CHIP CHIP CHIP_cts CHIP CHIP CHIP_route Net views Expanded Cell netlist views views Frame views Timing views Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-6 Design Setup Create Design Library Attach Reference Libraries Library > Add Ref Read Netlist Expand Netlist Open Design Library & Create Starting Cell Bind Netlist to Cell Preserve the Hierarchy Save Starting Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-7 Design Library & Reference Library StdLib inv nand2 nor2 ADC CODEC IO1 MEM Physical Hierarchy Recorder DAC DAC DAC IOLib IO1 IO2 inv xor3 Reference Memory MEM CHIP IO99 IO99 Top Cell Name Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-8 Design Setup Create Design Library Attach Reference Libraries Read Netlist Netlist In > Verilog In Expand Netlist Open Design Library & Create Starting Cell Bind Netlist to Cell Preserve the Hierarchy Save Starting Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-9 Power Connection Original netlist representation 1’b1 Implicit Power/Ground connections VDD VDD GND 1’b0 GND NETL/ representation VDD Explicit input connections to global Power/Ground GND Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-10 Naming Convention module CHIP(x, y); module CHIP(x, y); ..... ..... m inst_m( .i(a), .j(b), .k(c) ); m inst_m( .i(a), .j(b), .k(c) ); ..... ..... endmodule endmodule module m(i, j, k); module m(i, j, k); ..... ..... ..... ..... ..... ..... ..... ..... wire t; wire t; n inst_n( .p(d), .q(e) ); n inst_n( .p(d), .q(e) ); endmodule endmodule module n(p, q); module n(p, q); wire tmp; wire tmp; buf buffer( .in(in), .out(out) ); buf buffer( .in(in), .out(out) ); endmodule endmodule inst_m.inst_n.tmp inst_m.inst_n.buf Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-11 Library After Reading Netlist Recorder NETL EXP CEL FRAM LM lib lib_1 lib_bck CHIP.NETL CHIP.EXP CHIP.CEL CHIP.FRAM CHIP.TIM CHIP CODEC inv Top Cell and Sub Blocks of All Top Cell and Sub Blocks of All Hierarchy Hierarchy Net views Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-12 Design Setup Create Design Library Attach Reference Libraries Read Netlist Expand Netlist Netlist In > Expand Open Design Library & Create Starting Cell Bind Netlist to Cell Preserve the Hierarchy Save Starting Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-13 Flat Layout vs. Hierarchical Netlist The physical layout is a flat representation of all leaf cells from all logical hierarchy levels. Logical sub-blocks “disappear” and are ignored. Hierarchical Netlist Top Top A2 A B RAM A3 A1 C1 C3 A4 RAM C3 C2 Flat Layout A1 A2 A3 A4 C1 C C2 = leaf cell (std or macro cell) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-14 Global Power/Ground “Association” to Cells During expansion, P/G ports in std and macro cells must be “associated” with corresponding Global Power/Ground signals Use the “Global Nets Option” dialog to specify, which ports are associated with which global nets NETL/ representation EXP/ representation P/G ports “associated” with global Power/Ground VDD VDD VDD GND VDD GND GND GND Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-15 Library After Expanding Netlist Library Name NETL EXP CEL FRAM TIM lib lib_1 lib_bck CHIP.NETL CHIP.EXP CHIP.CEL CHIP.FRAM CHIP.TIM CHIP CODEC inv CHIP Top Cell Only Top Cell Only Expanded netlist views 1-16 Net views Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Design Setup Create Design Library Attach Reference Libraries Read Netlist Expand Netlist Open Design Library & Create Starting Cell Library > Open & Cell > Create Bind Netlist to Cell Preserve the Hierarchy Save Starting Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-17 Library After Creating Starting Cell Library Name NETL EXP CEL FRAM TIM lib lib_1 lib_bck CHIP.NETL CHIP.EXP CHIP.CEL CHIP.FRAM CHIP.TIM CHIP CODEC inv CHIP CHIP CHIP CHIP (Empty Layout) (Empty Layout) Expanded Cell netlist views views 1-18 Net views Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Design Setup Create Design Library Attach Reference Libraries Read Netlist Expanded Netlist Expand Netlist Open Design Library & Create Starting Cell Bind Netlist to Cell Design Setup > Bind Netlist Preserve the Hierarchy Save Starting Cell CHIP CHIP (Empty Layout) (Empty Layout) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-19 Design Setup Create Design Library Attach Reference Libraries Read Netlist Expand Netlist Open Design Library & Create Starting Cell Bind Netlist to Cell Preserve the Hierarchy Cell > Initialize Hierarchy Information Cell > Mark Module Instances Preserved Save Starting Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-20 Post-layout Gate-level Simulation Astro operates on a flat design By default, output netlist is flat: Test “probe” points on sub-block boundaries may have moved or disappeared – cannot reuse test bench Problem: How do you reuse existing test benches and stimulus files? Solution: “Preserve the Hierarchy” during P&R Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-21 Hierarchy Preservation Hierarchy preservation is done in two steps: Initialize Hierarchy Maintains the sub-block hierarchy of selected blocks A necessary first step if you want to “mark as preserved” or do an HVO (Hierarchical Verilog Out) at project end Allows decode of hierarchical names in the SDC file Mark as Preserved Tells Astro that pin name, number and functionality must remain the same Usually the entire hierarchy is marked Depending on the verification technology, it may be unnecessary to mark as preserved to the lowest level Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-22 Design Setup Create Design Library Attach Reference Libraries Read Netlist Expand Netlist Open Design Library & Create Starting Cell Bind Netlist to Cell CHIP CHIP Preserve the Hierarchy CHIP_designsetup CHIP_designsetup Save Starting Cell CHIP_floorplan Cell > Save! & Cell > Save As CHIP_floorplan CHIP_place CHIP_place … … Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-23 Lab 1-1 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 1-24 Cell-Based IC Physical Design and Verification with Astro Floorplanning General Astro Flow Design Setup Design Setup Gate-level Gate-level Netlist Netlist Floorplanning Floorplanning Timing Setup Timing Setup Placement Placement GDSII GDSII Layout Layout CTS CTS Routing Routing Design for Manufacturing Design for Manufacturing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Unit1 Unit1 Unit2 Unit2 Unit3 Unit3 Unit4 Unit4 Unit5 Unit5 Unit6 Unit6 Unit7 Unit7 2-2 Floorplan Areas Pad Area Core Area Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-3 Floorplanning Create power and corner pads Specify IO Constraint Define the core and pad area Place the macros Implement P/G grid Defining placement and routing blockages Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-4 Creating Power and Corner Pads ; Create P/G pads for core power ; Create P/G pads for core power dbCreateCellInst (geGetEditCell) dbCreateCellInst (geGetEditCell) dbCreateCellInst (geGetEditCell) dbCreateCellInst (geGetEditCell) supply supply "" “PVSSC.FRAM" "" “PVSSC.FRAM" "" “PVDDC.FRAM" "" “PVDDC.FRAM" “vss_core_1" “vss_core_1" “vdd_core_1" “vdd_core_1" "0" "NO" '(0.0 0.0) "0" "NO" '(0.0 0.0) "NO" '(0.0 0.0) "NO" '(0.0 0.0) ; Create corner cells ; Create corner cells dbCreateCellInst (geGetEditCell) "" “PCORNER.FRAM" "CornerLL" "270" "NO" '(10 10) dbCreateCellInst (geGetEditCell) "" “PCORNER.FRAM" "CornerLL" "270" "NO" '(10 10) dbCreateCellInst (geGetEditCell) "" “PVSSC.FRAM" “vss_core_1" "0" "NO" '(0.0 0.0) 0o Cell ID Reference Library Reference Instance Rotation Mirror Origin (X,Y) Cell name 90o 270o Return current cell 180o Rotation Return current library 2-5 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Floorplanning Create power and corner pads Specify IO Constraint Define the core and pad area Place the macros Implement P/G grid Defining placement and routing blockages Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-6 IO Constraints By default pads are evenly distributed on each side pad padName padSide [padOrder] [padOffset] [“reflect”] pad pad pad pad pad pad pad pad pad “Cul＂ “left＂ “Cur＂ “top＂ “Clr＂ “right＂ “Cll＂ “bottom＂ “L1＂ “left＂ “L2＂ “left＂ “L3＂ “left＂ “T1＂ “top＂ “T2＂ “top＂ 4 3 1 1 1 2 400 3 200 1 2 Cul L3 L2 L1 Cll T1 T2 Cur padOrder constraint overrides padOffset constraint 400 200 Clr Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-7 Floorplanning Create power and corner pads Specify IO Constraint Create the core and pad area Design Setup > Set Up Floorplan Place the macros Implement P/G grid Defining placement and routing blockages Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-8 Create Core Area (1/2) Core To Left Distance Width Core Area Height Bottom of row key Control Parameters Control Parameters Aspect Ratio Aspect Ratio -- Utilization Utilization -- Aspect ratio (H/W) Aspect ratio (H/W) -- Row/core ratio Row/core ratio Width & Height Width & Height -- Width Width -- Height Height -- Row/core ratio Row/core ratio ………. ………. Core To Bottom Distance horizontal no double back no-flip first row Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-9 Create Core Area (2/2) Row (Area：1600 µm2) Channel (Area：400 µm2) Standard Cell (Area：800 µm2) Aspect ratio: 40/50 = 0.8 Core Utilization: 800/2000 = 0.4 Row/Core Ratio: 1600/2000 = 0.8 Core to Left: 10 Core To Right: 11 Core To Bottom: 12 Core To Top: 13 10µm 40µm 13µm 50µm 11µm 12µm Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-10 Create Pad Area Signal pads Instantiated in netlist CornerUR Power and corner pads Created with dbCreateCellInst command in the tdf file Filler pads Inserted later with PostPlace > Add Pad Fillers command Reset Filler VDD VSS P/G rings: Added later with PreRoute > Pad Rings command Pad area is created by loading the tdf file Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-11 Chip Package Requirements Bond wire requirements No crossing Min spacing Max angle Max length More … Wire crossing over bond finger violation Core Area Pads moved to clear violation Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-12 Specify IO Pad Location ; Variable definition for a shorter name used below ; Variable definition for a shorter name used below define _cell (geGetEditCell) define _cell (geGetEditCell) ; Place IO using Cartesian Coordinate ; Place IO using Cartesian Coordinate dbCreateCellInstPlacement _cell “D0" "270" "no" "origin" '(0 400.00) dbCreateCellInstPlacement _cell “D0" "270" "no" "origin" '(0 400.00) dbCreateCellInstPlacement _cell “D1" "270" "no" "origin" '(0 480.00) dbCreateCellInstPlacement _cell “D1" "270" "no" "origin" '(0 480.00) dbCreateCellInstPlacement _cell "VDD1" "270" "no" "origin" '(0 560.00) dbCreateCellInstPlacement _cell "VDD1" "270" "no" "origin" '(0 560.00) dbCreateCellInstPlacement _cell “D0" "270" "no" "origin" '(0 400.00) VSS1 Filler VDD1 D1 D0 Cell ID Pad name Rotation Mirror Reference Location Point of Cell (X,Y) CornerLL CK Unspecified pads are placed automatically Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-13 Cell After Creating Core and Pad Areas Unplaced Macro Unplaced Macro Flip First Row Flip First Row Double Back Double Back Unplaced Unplaced Standard Standard Cell Cell Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-14 Floorplanning Create power and corner pads Specify IO Constraint Create the core and pad area Place the macros Modify > Move & Modify > Transform Implement P/G grid Defining placement and routing blockages Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-15 Floorplanning Create power and corner pads Specify IO Constraint Create the core and pad area Place the macros Implement P/G grid Connect Ports to P/G (PreRoute > Connect Ports to P/G) Create Ring (PreRoute > Rectangular Rings) Create Strap (PreRoute > Straps) Connect Macro & IO P/G ports to Ring (PreRoute > Macros/Pads) Defining placement and routing blockages Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-16 P/G Grid and Blockages core ring core ring strap strap macro ring macro ring soft soft blockage blockage hard hard blockage blockage Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-17 Connect Ports to P/G module CHIP(…); module CHIP(…); INV i1(...); INV i1(...); AND a1(...); AND a1(...); Macro m1(...); Macro m1(...); PPAD(...); PPAD(...); GPAD(...); GPAD(...); ….. ….. endmodule endmodule VDD VDD VDD VDD1 X Macro Y GND INV I O B A AND VSS O VSS VSS 1. 2. 3. 4. 5. 6. Connect Connect Connect Connect Connect Connect power to standard cells power to macros VDDP Core Power power to IO cells PPAD Pad ground to standard cells ground to macros ground to IO cells VSSP Core Ground GPAD Pad Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-18 Create Ring LH TL BL LL Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro RH TH BH RL 2-19 Create Strap At First Targets Extend to High Boundaries and Generate Pins At Core Bdry VSS VDD 750 1250 Step Group2 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Group1 Pitch (0,0) 2-20 2 Ring + 1 Strap ring macro macro macro ring strap Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-21 3 Straps macro macro macro strap strap strap Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-22 Connect Macro & IO P/G ports to Ring Connections are made to the closest P/G grid on each side of the instance Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-23 Floorplanning Create power and corner pads Specify IO Constraint Create the core and pad area Place the macros Implement P/G grid Defining placement blockages Create hard blockage (PrePlace > Create Hard Blockage) Create soft blockage (PrePlace > Create Soft Blockage) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-24 Hard Blockage vs. Soft Blockage Hard blockage prevents standard cells from being placed in this region Macro 1 Macro 2 Hard placement blockage Soft placement blockage Soft blockage allows new buffers/inverters to be inserted during optimization 2-25 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Lab 1-2 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 2-26 Cell-Based IC Physical Design and Verification with Astro Timing Setup General Astro Flow Design Setup Design Setup Gate-level Gate-level Netlist Netlist Floorplanning Floorplanning Timing Setup Timing Setup Placement Placement GDSII GDSII Layout Layout CTS CTS Routing Routing Design for Manufacturing Design for Manufacturing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Unit1 Unit1 Unit2 Unit2 Unit3 Unit3 Unit4 Unit4 Unit5 Unit5 Unit6 Unit6 Unit7 Unit7 3-2 Timing Driven P&R Astro optimizes the logic gates, places and routes them to fit in the smallest possible area while meeting all timing constraints In addition to P&R, Astro has the capability of static timing analysis (STA) for the given timing constraints interconnect parasitic extraction estimation and calculation logic gates optimization based on the physical design information Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-3 Static Timing Analysis (STA) Main steps of STA Break the design into sets of timing paths Calculate the delay of each path Check all path delays to see if the given timing constraints are met Four types of paths PI Start Point Combinational Logic End Point PO Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-4 Block-based vs. Path-based STA AT=2 3 1 Path-based: 2 1 3 1 3 2 RAT=10 2+2+3 = 7 2+3+1+3 = 2+3+3+2 = 5+1+1+3 = 5+1+3+2 = 5+1+2 = 8 9 10 10 11 (OK) (OK) (OK) (OK) (Fail) (OK) AT=5 AT=2 AT=2 RAT=5 AT=5 3 1 AT=5 RAT=4 AT=6 RAT=5 2 1 3 1 AT=7 RAT=7 Block-based: 3 2 RAT=10 AT=11 RAT=10 AT=9 RAT=8 Critical path is determined as collection of gates with the same, negative slack: In our case, we see one critical path with slack = -1 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-5 Data Preparation for STA Gate-level Netlist Design Data Block Models Back-annotated Parasitic Interconnect Data Estimated Wire Load Models STA Descriptions of Clocks Cell Library Library Data Operating Conditions Timing Exceptions Timing Constraints Boundary Conditions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-6 Library Data Cell Delay model Linear model Non-linear model Operating conditions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-7 Linear Cell Delay Model delay time (ns) T0 Cell Delay = T0 + Ac * Cload output capacitance load (pf) T0 : cell pin to pin intrinsic delay (delay without any loading) Ac : drive impedance Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-8 Non-linear Cell Delay Model Delay values are stored in the delay tables Delay tables Cell delay Transition delay Vin 50% 50% Vout 20% 80% I1 I2 Dtransition(I1) Dc Req Dtransition(I2) I3 Ceq 3-9 Dcell(I2) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Delay Tables Cell Delay Transition Delay Output Capacitance 0.1 0.2 Dcell(I2) = f(Dtransition(I1), Ceq) Dtransistion(I2) = g(Dtransition(I1), Ceq) Input Transition 0 0.123 0.222 0.5 0.234 0.432 1 0.456 0.801 index1: input transition Index2: output capacitance Vin I1 I2 Dtransition(I1) Dc Vout Dtransition(I2) Req Ceq 3-10 I3 Dcell(I2) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Select the Correct Delay Table According to output transition direction rise table fall table R F Output transition direction depends on unateness invert (positive_unate) noninvert (negative_unate) nonunate The worst case delay is selected edge_rising edge_falling R or F R Consider the clock edge for sequential cells Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-11 Operating Conditions The process, voltage, and temperature (PVT) ranges a design encounters Specified in the technology library Cell and interconnect delays are scaled Dscale = D (1 + ∆ P K P )(1 + ∆V KV )(1 + ∆ T K T ) ∆ P = Pr ocess − nom _ process / ∆V = Voltage − nom _ voltage ∆ T = Temperature − nom _ temperature delay Worst Typical Best Process Voltage Best Temperature 3-12 delay Worst Typical Best delay Worst Typical Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Data Preparation for STA Gate-level Netlist Design Data Block Models Back-annotated Parasitic Interconnect Data Estimated Wire Load Models STA Descriptions of Clocks Cell Library Library Data Operating Conditions Timing Exceptions Timing Constraints Boundary Conditions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-13 Define Timing Constraints Design rule constraints Set fan-out constraints Set capacitance constraints Set transition time constraints Design optimization constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-14 Define Clock Specification We need to accurately specify the clock including the clock routing details in the early design stage in order to achieve timing convergence What should be defined? Period Waveform Latency Source latency Network latency Uncertainty Jitter Skew All register-to-register path are constrained now Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-15 Clock Period & Waveform Period: Clock cycle time Waveform: Clock rise and fall time Example: Period: 10ns Rise time: 0ns Fall time: 5ns clock 0 5 10 3-16 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Clock Latency A very important part of the clock is the routing effects: Off Chip cause: Source latency (delay): the timing a clock signal takes to propagate from its ideal waveform original point to the clock definition point On Chip cause: Budgeted network latency (delay) : the time the clock signal takes to propagate from the clock definition point to the clock pin of the sequential cells Actual insertion delay D Q QN network latency source latency (min_rise : max_rise : min_fall : max_fall) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-17 Clock Uncertainty Definition The maximum difference between the arrival of clock signals at sequential cells in one clock domain or between domains P1 FF P4 FF P2 P3 FF Arrival(P1) Arrival(P2) Arrival(P3) Arrival(P4) = = = = 0.5ns 1ns 1.2ns 1.3ns uncertainty = 1.3 – 0.5 = 0.8ns FF Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-18 Clock Uncertainty A very important part of the clock is the routing Off Chip impact: Jitter: typically a small value On Chip impact: Budgeted skew Actual skew Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-19 Ideal and Computed Clocks Off chip clock effects are fixed throughout flow: Source Latency Jitter On chip routing is estimated till clock tree routing Budgeted network latency Budgeted skew On chip routing is calculated after clock tree routing Actual insertion delay (network latency) Actual skew Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-20 Define Timing Constraints Design rule constraints Set fan-out constraints Set capacitance constraints Set transition time constraints Design optimization constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-21 I/O Constraints After constraining clock, we still need to constrain the I/O Only comboin needs a "budgeted" arrival time Only combout needs a "budgeted" required time Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-22 Boundary Conditions Input driving cell Input transition time Output capacitance load Input delay Output delay D Q QN b 5pf Driving Cell INV01 Output Capacitance Load Input Transition Time Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-23 Input & Output Delay An input delay is the specification of an arrival time at an input port relative to a clock edge An output delay represents an external timing path from am output or inout port to a register Input delay = Delayclk-Q + a Q a Q b c Input Block My Design Output Block Output delay = c Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-24 Define Timing Constraints Design rule constraints Set fan-out constraints Set capacitance constraints Set transition time constraints Design optimization constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-25 Constraint Combinational Path Delay Set a target maximum delay for output ports Override the default single-cycle timing for paths Set a target minimum delay for output ports Override the default hold relation in a sequential path IN Logic Out Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-26 Define Timing Constraints Design rule constraints Set fan-out constraints Set capacitance constraints Set transition time constraints Design optimization constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions False Path Multi-cycle path Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-27 False Path Why are there false path constraints in a design? A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-28 Unexercised Path A path may exist in the circuit but never be used in its normal functional operation A test register PROBE is inserted in the circuit to enable chip debugging in the field. Data can be read through the probe register. Data can be written from the probe register. Probing would not occur at speed. (An alternative to scan) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-29 False Path Why are there false path constraints in a design? A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-30 Irrelevant Path A functional path may exist but the timing is so slow or irrelevant The chip uses a synchronized synchronous reset. The reset cycle has a huge number of cycles before it needs to settle. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-31 Asynchronous Path A functional path may exist but the timing is so slow or irrelevant I have metastabilization registers between those two asynchronous clock zones Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-32 False Path Why are there false path constraints in a design? A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-33 IP Reuse A block may be reused and certain signal functions are no longer required This piece of logic is a custom adder. With design re-use, often the blocks contain all of the potentially useful functions. When the design is implemented in a chip, often particular signals are not implemented Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-34 False Path Why are there false path constraints in a design? A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-35 Logically Impossible Path A path may exist in the circuit but no combination of input vectors may ever exercise it A signal cannot travel from the Q output of a_reg through the two muxes to b_reg PrimeTime attempts to automatically detect "logically impossible false paths“ (requires many CPU cycles) These situations are quite rare Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-36 False Path Why are there false path constraints in a design? A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-37 Combinational Loops A combinational loop exists in the design that needs to be broken Most STA’s can’t leave combinational loops in the design, as a race condition will occur PrimeTime dynamically breaks combinational loops. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-38 Break Combinational Loops Break Break Break Break any reset arc (unusually specified) a three-state enable arc at the first loop re-entry point arcs in the library Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-39 Define Timing Constraints Design rule constraints Set fan-out constraints Set capacitance constraints Set transition time constraints Design optimization constraints Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions False Path Multi-cycle path Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-40 Multicycle Paths Multicycle paths occur because the designer knows that the particular logic function will not be used till a later cycle Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-41 Data Preparation for STA Gate-level Netlist Design Data Block Models Back-annotated Parasitic Interconnect Data Estimated Wire Load Models STA Descriptions of Clocks Cell Library Library Data Operating Conditions Timing Exceptions Timing Constraints Boundary Conditions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-42 Interconnect Data Estimated delay information for nets based on a wire load model is used before P&R Back-annotated (Actual) delay information based on the P&R result is often described in the form of SDF (timing information) – Standard Delay Format SDF triplet: (min:typ:max) RSPF – Reduced Standard Parasitic Format DSPF – Detailed Standard Parasitic Format SPEF – Standard Parasitic Exchange Format SPEF also has syntax that allows the modeling of capacitance between different nets, so it is used by the crosstalk analysis tool Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-43 Wireload Model Very inaccurate! wire_load (“500”) ( resistance : 3.0 capacitance: 1.3 area: 0.04 slop: 0.15 fanout_length ( 1 , 2.1 ) fanout_length ( 2 , 2.5) fanout_length ( 3 , 2.8) fanout_length ( 4 , 3.3) /* R per unit length*/ /* C per unit length */ /* area per unit length */ /* extrapolation slope*/ /* fanout-length pairs */ 500um x 500um 1000um x 1000um Cwire = (fanout=3, length =2.8) x capacitance coefficient (1.3) = 3.64 load units Rwire = (fanout=3, length =2.8) x resistance coefficient (3.0) = 8.4 resistance units AreaNet = (fanout=3, length =2.8) x area coefficient (0.04) = 0.112 net area units 3-44 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Wireload Modes Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-45 Parasitic Model During P&R Compute wire length Ideal Manhattan Model Computed Manhattan Model Global Routing Model Compute parasitic value Linear parasitic model Table lookup parasitic model Calculate wire delay Elmore Model Final Layout Model Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-46 Ideal Manhattan Model Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-47 Computed Manhattan Model Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-48 Global Routing Model Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-49 Table Lookup Parasitic Model Table-Look-Up (TLU) Capacitance model CapTable cap_value = f(configuration, width, spacing) CapModel Assign CapTable to the reference layer according to the configuration Capacitances are categorized into bottom, top and lateral group M2 M1 Poly configuration1 configuration2 air top lateral substrate configuration3 3-50 bottom Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Elmore Model Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-51 Final Layout Model AWE (Extraction Based) Model p1 , p2 – Poles r1 , r2 - Residues Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-52 Perform Static Timing Analysis Gate-level Netlist Block Models Cell Library Operating Conditions Back-annotated Parasitic Specify design data & libraries Estimated Wire Load Models Specify interconnect Specify timing constraints Check Timing Constraint Violation Reports Path Timing Reports Descriptions of Clocks Boundary Conditions Timing Exceptions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-53 STA Example 1 (Assumptions) Check setup time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-54 STA Example 1 (Timing Constraints) Clock definition Clock Clock Clock Clock period: 14ns (Dclkp) source latency: 2ns (Dclks) network latency: 3ns (Dclkn) uncertainty: 1ns (Dclku) IO constraints Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-55 STA Example 1 (Timing Paths) Timing Path 1 Timing Path 2 Timing Path 3 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-56 STA Example 1 (AT of Path1 - Rise) Timing path 1: PI to clock data input Arrival time at end point: Da+2+3+2+3+2 = 13ns launch edge 0 13 14 capture edge AT source clock (ideal) target clock (ideal) R 2 3 R 2 AT = 13 2 Why are the delay values chosen? R 3 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-57 STA Example 1 (AT of Path1 - Fall) Timing path 1: PI to clock data input Arrival time at end point: Da+2+2+2+3+2 = 12ns launch edge 0 12 14 capture edge source clock (ideal) target clock (ideal) AT F 2 2 F 2 AT = 12 2 Why are the delay values chosen? R 3 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-58 STA Example 1 (RT of Path1 - R/F) Timing path 1: PI to clock data input Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns launch edge 0 14 target clock (ideal) 16 target clock (source) source clock (ideal) capture edge 19 target clock (source+network) 18 RT 17 target clock (source+network +uncertainty) setup time Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-59 STA Example 1 (Slack of Path1 - Rise) Timing path 1: PI to clock data input Slack at end point: RT - AT = 17-13 = 4ns Timing is met since slack is greater than 0 R 2 3 R 2 AT = 13 RT = 17 R 3 2 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-60 STA Example 1 (Slack of Path1 - Fall) Timing path 1: PI to clock data input Slack at end point: RT - AT = 17-12 = 5ns Timing is met since slack is greater than 0 F 2 2 F 2 AT = 12 RT = 17 2 R 3 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-61 STA Example 1 (AT of Path2 - Rise) Timing path 2: clock to clock data input Arrival time at end point: Dclks + Dclkn +3+2+3+2+3+2 = 20ns source clock (ideal) 0 5 launch edge 14 19 20 AT source clock (source +network) AT = 20 3 R2 3 R 2 3 2 R Why are the delay values chosen? Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-62 STA Example 1 (AT of Path2 - Fall) Timing path 2: clock to clock data input Arrival time at end point: Dclks + Dclkn +3+2+2+2+3+2 = 19ns source clock (ideal) 0 5 launch edge 14 19 AT source clock (source +network) AT = 19 3 F2 2 F 2 3 2 R Why are the delay values chosen? Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-63 STA Example 1 (RT of Path2 - R/F) Timing path 2: clock to clock data input Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns launch edge 0 5 14 16 source clock (source+ network) target clock (ideal) target clock (source) capture edge 19 target clock (source+network) 18 RT 17 target clock (source+network +uncertainty) setup time Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-64 STA Example 1 (Slack of Path2 - Rise) Timing path 2: clock to clock data input Slack at end point: RT - AT = 17-20 = -3ns Timing is not met since slack value is negative AT = 20 3 3 RT = 17 R 2 3 2 R R2 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-65 STA Example 1 (Slack of Path2 - Fall) Timing path 2: clock to clock data input Slack at end point: RT - AT = 17-19 = -2ns Timing is not met since slack value is negative AT = 19 RT = 17 3 F2 2 F 2 3 2 R Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-66 STA Example 1 (AT of Path3 - Rise) Timing path 3: clock to PO Arrival time at end point: Dclks + Dclkn +3+2+3+2= 15ns source clock (ideal) 0 5 launch edge 14 15 source clock (source +network) AT 3 R 2 3 AT = 15 R 2 3-67 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro STA Example 1 (AT of Path3 - Fall) Timing path 3: clock to PO Arrival time at end point: Dclks + Dclkn +3+2+2+2= 14ns source clock (ideal) 0 5 launch edge AT 14 source clock (source +network) 3 F 2 2 AT = 14 F 2 3-68 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro STA Example 1 (RT of Path3 - R/F) Timing path 3: clock to PO Required time at end point: Dclkp - DY = 14-3 = 11ns launch edge 0 5 RT 11 14 source clock (source+ network) target clock (ideal) output delay 3 F 2 2 RT = 11 F 2 3 D Q QN Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-69 STA Example 1 (Slack of Path3 - Rise) Timing path 3: clock to PO Slack at end point: RT - AT = 11-15 = -4ns Timing is not met since slack value is negative This is the critical path 3 R 2 3 AT = 15 RT = 11 3 R 2 QN D Q Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-70 STA Example 1 (Slack of Path3 - Fall) Timing path 3: clock to PO Slack at end point: RT - AT = 11-14 = -3ns Timing is not met since slack value is negative 3 F 2 2 AT = 14 RT = 11 F 2 3 D Q QN Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-71 STA Example 2 (Assumptions) Check hold time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-72 STA Example 2 (Timing Constraints) Clock definition Clock Clock Clock Clock period: 14ns (Dclkp) source latency: 2ns (Dclks) network latency: 3ns (Dclkn) uncertainty: 1ns (Dclku) IO constraints Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-73 STA Example 2 (Timing Paths) Timing Path 1 Timing Path 2 Timing Path 3 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-74 STA Example 2 (AT of Path1 – R/F) Timing path 1: PI to clock data input Arrival time at end point: Da+1 = 2ns launch edge 0 2 capture edge AT Next Data AT = 2 D Q QN source clock (ideal) 14 target clock (ideal) Why are the delay values chosen? R/F 1 1 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-75 STA Example 2 (RT of Path1 - R/F) Timing path 1: PI to clock data input Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns launch edge 0 7 target clock (ideal) target clock (source) target clock (source+network) capture edge RT hold time target clock (source+network +uncertainty) source clock (ideal) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-76 STA Example 2 (Slack of Path1 – R/F) Timing path 1: PI to clock data input Slack at end point: AT - RT = 2-7 = -5ns Timing is not met since slack value is negative This is the critical path D Q QN R/F 1 1 AT = 2 RT = 7 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-77 STA Example 2 (AT of Path2 - Rise) Timing path 2: clock to clock data input Arrival time at end point: Dclks + Dclkn +3+1+2+1+2+1 = 15ns source clock (ideal) 0 5 launch edge 14 AT 19 20 source clock (source +network) Next Data AT = 15 3 R1 2 R 1 2 1 R Why are the delay values chosen? Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-78 STA Example 2 (AT of Path2 - Fall) Timing path 2: clock to clock data input Arrival time at end point: Dclks + Dclkn +3+1+1+1+2+1 = 14ns source clock (ideal) 0 5 launch edge 14 source clock (source +network) Next Data AT = 14 3 F1 1 F 1 2 1 R Why are the delay values chosen? AT Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-79 STA Example 2 (RT of Path2 - R/F) Timing path 2: clock to clock data input Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns launch edge 0 7 target clock (ideal) target clock (source) target clock (source+network) capture edge RT hold time target clock (source+network +uncertainty) source clock (ideal) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-80 STA Example 2 (Slack of Path2 - Rise) Timing path 2: clock to clock data input Slack at end point: AT - RT = 15-7 = 8ns Timing is met since slack is greater than 0 AT = 15 RT = 7 3 2 R 1 2 1 R R1 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-81 STA Example 2 (Slack of Path2 - Fall) Timing path 2: clock to clock data input Slack at end point: AT - RT = 14-7 = 7ns Timing is met since slack is greater than 0 AT = 14 RT = 7 3 F1 1 F 1 2 1 R Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-82 STA Example 2 (AT of Path3 - Rise) Timing path 3: clock to PO Arrival time at end point: Dclks + Dclkn +3+1+2+1= 12ns source clock (ideal) 0 5 launch edge 12 AT Next Data source clock (source +network) 3 R 1 2 AT = 12 R 1 3-83 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro STA Example 2 (AT of Path3 - Fall) Timing path 3: clock to PO Arrival time at end point: Dclks + Dclkn +1+1+1= 11ns source clock (ideal) 0 5 launch edge 11 AT Next Data source clock (source +network) 3 F 1 1 AT = 11 F 1 3-84 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro STA Example 2 (RT of Path3 - R/F) Timing path 3: clock to PO Required time at end point: - DY = -3ns launch edge -3 0 source clock (source+ network) target clock (ideal) RT output delay F 1 1 RT = -3 F 1 D Q QN 3 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-85 STA Example 2 (Slack of Path3 - Rise) Timing path 3: clock to PO Slack at end point: AT - RT = 12-(-3) = 15ns Timing is met since slack is greater than 0 AT = 12 R 1 2 RT = -3 R 1 D Q QN 3 1 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-86 STA Example 2 (Slack of Path3 - Fall) Timing path 3: clock to PO Slack at end point: AT - RT = 11-(-3) = 14ns Timing is met since slack is greater than 0 AT = 11 F 1 1 RT = -3 F 1 3 D Q QN 1 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-87 Astro Timing Setup Define and Load Timing Constraints Timing > Load SDC Check Timing Data Attach Parasitic Model Set Appropriate Parameters in Timing Setup Panel Timing Sanity Check Net Delay Model Selection Before CTS After CTS Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-88 SDC Timing Constraints (1/2) Define clock waveform create_clock -name “SYS_CLK" -period 10 -waveform {0 5} [get_ports {clk}] create_generated_clock -name MY_CLK -source [get_ports {clk}] -multiply_by 1 [get_pins {ipad_clk/Y}] Define clock latency set_clock_latency 2 [get_clocks {MY_CLK}] Define clock uncertainty set_clock_uncertainty 0.5 [get_clocks {MY_CLK}] Set Propagated Clock set_propagated_clock [get_clocks {MY_CLK}] Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-89 SDC Timing Constraints (2/2) Set input delay set_input_delay 1 -clock "MY_CLK" [get_ports {datain[0]}] Set output delay set_output_delay 2 -clock "MY_CLK" [get_ports {dataout[0]}] Set output load set_load -pin_load 10 [get_ports {dataout[0]}] Set false path set_false_path -setup -from [get_ports {TEST_SI}] Set Operating Condition (Necessary when LM view is used instead of timing view) set_operating_conditions -min fast -max slow Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-90 Astro Timing Setup Define and Load Timing Constraints Check Timing Data Timing > Timing Data Check Attach Parasitic Model Set Appropriate Parameters in Timing Setup Panel Timing Sanity Check Net Delay Model Selection Before CTS After CTS Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-91 Check Timing Data After reading SDC constraints, you must ensure that they completely constrain the design. Completeness does not imply correctness! Number of unconstrained endpoints in the design: 30 Unconstrained Endpoints: -----------------------h264_d1 h264_d2 ... Number of input ports with no delay: 4 Ports With No Input Delay: -------------------------din[0] reset ... Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-92 Astro Timing Setup Define and Load Timing Constraints Check Timing Data Attach Parasitic Model Tech File > ITF to TLU+ Set Appropriate Parameters in Timing Setup Panel Timing Sanity Check Net Delay Model Selection Before CTS After CTS Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-93 Attach Parasitic Model The Mapping File translates .tf (Astro technology file) layer/via names into StarRCXT .itf layer/via names. 018.itf DIELECTRIC IMD1B DIELECTRIC IMD1A CONDUCTOR ME1 { THICKNESS=1.28 ...} { THICKNESS=0.6 ...} { THICKNESS=0.48 WMIN= ...} Verify that star_rcxt data is consistent with the main library’s technology data! 018.tf Layer “met1" { layerNumber = 46 maskName = "metal1" ... 018.map conducting_layers poly POLY metal1 ME1 metal2 ME2 … Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-94 Select TLU+ Capacitance Model Choice is made in “Timing Setup Panel” Timing > Timing Setup Make sure you click Apply Make sure you click Apply after making changes after making changes Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-95 Astro Timing Setup Define and Load Timing Constraints Check Timing Data Attach Parasitic Model Set Appropriate Parameters in Timing Setup Panel Timing Sanity Check Net Delay Model Selection Before CTS After CTS Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-96 Timing Sanity Check Verify that the constrained netlist has a good chance of meeting timing after P&R Timing Analysis is performed while ignoring net C Set “Ignore Interconnect” Set “Ignore Interconnect” option for zero C option for zero C Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-97 Net Delay Model Selection (1/2) After placement, but prior to routing, net geometry is estimated based on a Virtual Route Since Virtual Routing is only an estimate use Elmore for all steps up to and including routing After routing, detailed net is available and extraction will be more accurate Use AWE or Arnoldi for post-route optimizations Arnoldi preferred when comparing to PrimeTime™ Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-98 Net Delay Model Selection (2/2) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-99 Before CTS Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-100 After CTS Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-101 Lab 1-3 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 3-102 Cell-Based IC Physical Design and Verification with Astro Placement General Astro Flow Design Setup Design Setup Gate-level Gate-level Netlist Netlist Floorplanning Floorplanning Timing Setup Timing Setup Placement Placement GDSII GDSII Layout Layout CTS CTS Routing Routing Design for Manufacturing Design for Manufacturing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Unit1 Unit1 Unit2 Unit2 Unit3 Unit3 Unit4 Unit4 Unit5 Unit5 Unit6 Unit6 Unit7 Unit7 4-2 Astro Placement and CTS Flow Detach Scan Chains Set Placement Common Options Pre-Placement Optimization Standard Cell Placement Post-Placement Optimization Phase 1 (PPO1) Clock Tree Synthesis Connect Scan Chains Post-Placement Optimization Phase 2 (PPO2) Clock Tree Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-3 Placement Detach Scan Chains PrePlace > Trace Scan Chain PrePlace > Optimize/Delete Scan Chain Set Placement Common Options Pre-Placement Optimization Standard Cell Placement Post-Placement Optimization Phase 1 (PPO1) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-4 Scan Chains Scan chains are designed to load/unload test data: FFs are serially connected (alphanumeric ordering) Requires a lot of routing resources if serially connected FFs are not placed in their ordering Routing can be reduced by placing serially connected FFs based on their ordering: Requires long runtime to optimize FFs placement May hurt critical paths d[0] s_in1 d[1] s_in2 d[2] s_in3 scan_en FF FF FF FF FF FF FF FF FF dout_1 s_out1 dout_2 s_out2 dout_3 s_out3 A better solution... Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-5 Solution for Scan Chains Disconnecting the scan chains prior to placement allows the tool to focus on better for the functional critical paths Scan chains are re-connected after CTS using placement-based scan chain reordering FF FF FF FF FF FF FF FF FF d[0] s_in1 d[1] s_in2 d[2] s_in3 scan_en Reorder Scan Chains FF FF FF FF FF FF FF FF FF dout_1 s_out1 dout_2 s_out2 dout_3 s_out3 Detach Scan Chains Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-6 Placement Detach Scan Chains Set Placement Common Options InPlace > Placement Common Options Pre-Placement Optimization Standard Cell Placement Post-Placement Optimization Phase 1 (PPO1) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-7 Set Placement Common Options Options must be set prior to any placement and optimization steps. Use at least Congestion and Timing optimization mode. Better run time and congestion Better chip area 4-8 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Placement Detach Scan Chains Set Placement Common Options Pre-Placement Optimization PrePlace > Pre-Placement Optimization Standard Cell Placement Post-Placement Optimization Phase 1 (PPO1) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-9 Pre-Placement Optimization PrePlace optimization removes all WLM effects to create a minimal "seed" netlist (clean slate) prior to actual cell placement: Performs zero WLM (RC=0) optimization (Ideal Optimization) & logic re-mapping Reduces total cell area by gate down sizing (area recovery) and buffer removal Buffers high fanout nets based on a "reasonable" throw-away placement (quick placement) If timing violations are more than 5%, go back to the synthesis stage. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-10 Estimating Timing During Placement Placement uses RC parameters from Virtual Route (VR) to calculate timing VR = shortest Manhattan-distance between two pins VR RCs are much more accurate than WLM RCs The Virtual Route in Astro will look out for blockages/obstructions. If there are blockages, the virtual route will route around them Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-11 Buffer High Fanout Nets High fanout buffers are first collapsed then synthesized based on VR RCs from a "quick" placement This creates a better “seed” netlist for actual placement Collapse HFNs from Synthesis Netlist HFNs from Synthesis Netlist HFNs in “seed” Netlist HFNs in “seed” Netlist (based on quick placement) (based on quick placement) 4-12 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Placement Detach Scan Chains Set Placement Common Options Pre-Placement Optimization Standard Cell Placement Connect Standard Cell Power/Ground PreRoute > Standard Cells Cell Placement Congestion Analysis and Fixing Post-Placement Optimization Phase 1 (PPO1) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-13 Connect Standard Cell Power/Ground P/G rails for Std Cells uses routing resources. This affects congestion! Create P/G rails early so they are accounted for during placement Connect ports to P/G before this step for multiple PG design VSS VDD VSS VDD P/G Rail Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-14 Placement Detach Scan Chains Set Placement Common Options Pre-Placement Optimization Standard Cell Placement Connect Standard Cell Power/Ground Cell Placement InPlace > Design Placement Placement HFN Re-Synthesis In-Placement Opt. The above 3 steps occur concurrently Congestion Analysis and Fixing Post-Placement Optimization Phase 1 (PPO1) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-15 Cell Placement Timing driven placement Tries to place critical path cells close together to reduce net RCs and meet timing Is based on Virtual Route (VR) In-Placement Optimization (IPO) performs: Cell-sizing, cell-moving, cell-bypassing, net splitting, gate duplication, buffer/inverter insertion, area recovery Select In-Placement Optimization for logic optimization and HFN Collapse/Re-synthesis Previous HFNS was based on "throw away“ placement. This HFNS build buffer trees for the real placement. So HFN is re-synthesized. 4-16 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Placement Detach Scan Chains Set Placement Common Options Pre-Placement Optimization Standard Cell Placement Connect Standard Cell Power/Ground Cell Placement Congestion Analysis and Fixing InPlace > Display Congestion Map InPlace > Search and Refine Post-Placement Optimization Phase 1 (PPO1) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-17 Congestion There is a limit to the number of nets that can be routed through the small area (enclosed by the red circle) When you approach or exceed this limit, the area is said to be congested If placement remains unchanged, only solution is for the actual route to detour Worse, if nets cannot be detoured then the design cannot be routed! Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-18 2D Congestion Map 6/5 7/5 Horizontal demand = 14 Horizontal supply = 12 Overflow = 2 8/5 GRcell 6/5 14/12 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-19 1D Congestion Map 4/3 5/4 6/5 9/8 ∑demand ∑ supply 0.81 0.43 24/20 0.99 1.20 0.76 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-20 Be Proactive with Congestion Actual detoured net will have worse RC / timing compared to the VR estimate In highly congested areas, VR is therefore optimistic congestion area detoured net Fix congestion problems Fix congestion problems prior to routing prior to routing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-21 Fix Congestion During Placement During placement, the congestion is fixed by spreading cells apart Timing will get worse If the cells that are spread apart are in a timing critical path, this path may violate timing These timing violations can be resolved by performing logic optimization S&R works on localized areas and spreads cells apart in congested areas, even at the expense of timing. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-22 Placement Detach Scan Chains Set Placement Common Options Pre-Placement Optimization Standard Cell Placement Post-Placement Optimization Phase 1 (PPO1) PostPlace > Post-Place Optimization Phase 1 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-23 PPO1 Performs setup fixing and max tran/cap fixing First time max tran/cap fixing is performed. Slack may get worse with Tran/Cap fixing. Violations will be addressed during PPO2. Enable Global Routing (GR) Enable Global Routing (GR) for improved accuracy for improved accuracy Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-24 Global Routing (GR) Assigns nets to specific metal layers and global routing cells (GRCs) to more accurately predict the final routing paths and delays Also accounts for: P/G (rings/straps/rails) Routing blockages Placement blockages Congestion area GRC (next slide) GRC (next slide) global route Y virtual route X congestion area Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-25 Global Routing Cells (GRCs) GR determines if each assigned GRC along a path has enough wire tracks for the assigned nets through the edges of that GRC If not enough wire tracks, GR re-assigns metal layers or GRCs accordingly Z Y X M3 M2 M1 GRC wire tracks global route GR delay calculations and placement decisions are based on GR delay calculations and placement decisions are based on more accurate estimated wire routes and parasitics compared to VR more accurate estimated wire routes and parasitics compared to VR Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-26 Additional GR Benefits in PPO1 PPO1 uses global route to foresee routing detours based on congestion and routing blockages Buffers are added to account for long detoured nets while observing placement blockages More effort spent here will speed up post-place flow Routing blockage Detoured route Placement blockage Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-27 Lab 1-4 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 4-28 Cell-Based IC Physical Design and Verification with Astro CTS General Astro Flow Design Setup Design Setup Gate-level Gate-level Netlist Netlist Floorplanning Floorplanning Timing Setup Timing Setup Placement Placement GDSII GDSII Layout Layout CTS CTS Routing Routing Design for Manufacturing Design for Manufacturing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Unit1 Unit1 Unit2 Unit2 Unit3 Unit3 Unit4 Unit4 Unit5 Unit5 Unit6 Unit6 Unit7 Unit7 5-2 CTS Clock Tree Synthesis Clock > Clock Common Options Clock > Clock Tree Synthesis Connect Scan Chains Post-Placement Optimization Phase 2 (PPO2) Clock Tree Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-3 Effect of Clock Skew on Timing The budget for combinational delay is 9ns only -1ns -1ns capature time = 10 – 1 = 9 Decrease the timing performance if there are critical paths in the combinational logic cloud. The budget for combinational delay is 11ns. 1ns 1ns capature time = 10 + 1 = 11 Useful Useful Skew Skew 5-4 Increase the timing performance if there are critical paths in the combinational logic cloud. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Why Clock Tree Synthesis? Normally, we do CTS for zero skew. Logical synthesis tool doesn't have good knowledge on building good clock tree to buffer loads on the clock. Do not add clock tree during synthesis. HFN synthesis is used to balance the load but it's not DQ good at balance the skew. DQ DQ DQ DQ CTS CTS HFN synthesis HFN synthesis & & Skew optimization Skew optimization Clock DQ Clock DQ DQ DQ DQ LPM D Q G DQ LPM D Q G DQ Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-5 How Clock Tree Synthesis? Add multi-level buffer trees according to your clock specification (model/estimation) for the previous stages skew & insertion delay A good clock tree should have the same features as described in the clock estimation CTS result will be always bad if the clock estimation is not realistic. In this case, make realist clock estimation according to the CTS result and then go back to the Timing Setup stage. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-6 Effects of Clock Tree Synthesis More buffers added Other cells may move Congestion may increase Can introduce new timing and max cap/trans violations Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-7 Clock Tree Synthesis Setup Settings for CTS and CTO Include all clocks from the SDC file if this field is empty This skew value overrides set_clock_uncertainty from the SDC set_clock_latency from SDC overrides this insertion delay value Options will be used during CTO Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-8 Clock Tree Synthesis and Optimization Input to CTS should be placed design w/o clock tree tran/Cap fixed HFN synthesized minimized timing violations acceptable congestion SDC clock constraints Create clock tree to meet SDC targets CTO can run automatically right after CTS Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-9 When does CTS and CTO Stop? CTS CTS Skew < Target? No CTO CTO Reduces Skew Reduces Skew Yes Insertion Delay > Target? Yes No CTO CTO Adds Delay Cells Adds Delay Cells Stop Default values are zeros which means to minimize the targets as much as possible 5-10 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro After CTS Adjust the following in the timing setup panel to tell optimizations to use the actual clock tree delays Set “Ignore Clock Uncertainty”, unless this is used to gain additional margin Unset “Ignore Propagated Clock” Unset “Enable Ideal Network Delay “ Reconnect scan chains so the next optimization steps take them into account for hold time fixing After CTS, the design may have: Timing (setup/hold) violations Max transition and max capacitance violations Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-11 CTS Clock Tree Synthesis Connect Scan Chains Post-Placement Optimization Phase 2 (PPO2) Clock Tree Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-12 CTS Clock Tree Synthesis Connect Scan Chains Post-Placement Optimization Phase 2 (PPO2) PostPlace > Post Placement Optimization Clock Tree Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-13 PPO2 Fixes violations due to CTS perturbations and addresses hold for the 1st time CTS CTS Enable to reduce routing congestion Setup and Hold Fixing Setup and Hold Fixing Max Tran/Cap Fixing Max Tran/Cap Fixing Area Recovery Area Recovery Setup/hold, Setup/hold, max tran/cap max tran/cap ok? ok? no Vary PPO 2 Vary PPO 2 Parameters Parameters yes CTO CTO For large design, target only one optimization at a time, e.g. only max transition fixing 5-14 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro CTS Clock Tree Synthesis Connect Scan Chains Post-Placement Optimization Phase 2 (PPO2) Clock Tree Optimization Clock > Clock Tree Optimization Clock > Skew Analysis Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-15 Clock Tree Optimization Improve the clock tree after PPO 2 PPO2 PPO2 Clock Skew Analysis Clock Skew Analysis (next slide) (next slide) Skew OK? Skew OK? no Optimize Optimize Clock Clock yes Routing Routing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-16 Clock Skew Analysis Global Clock Skew: Reports skew for all clocks Local Clock Skew: Arrival time difference between two flops that are adjacent through combinational logic Inter Clock Skew: The difference between clock with smallest skew and clock with largest skew Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-17 Lab 1-5 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 5-18 Cell-Based IC Physical Design and Verification with Astro Routing General Astro Flow Design Setup Design Setup Gate-level Gate-level Netlist Netlist Floorplanning Floorplanning Timing Setup Timing Setup Placement Placement GDSII GDSII Layout Layout CTS CTS Routing Routing Design for Manufacturing Design for Manufacturing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Unit1 Unit1 Unit2 Unit2 Unit3 Unit3 Unit4 Unit4 Unit5 Unit5 Unit6 Unit6 Unit7 Unit7 6-2 Design Status, Start of Routing Phase Standard cells are placed Clock tree and HFN buffers placed Virtual route (or optionally a Global route) was completed: Estimated Estimated Estimated Estimated congestion - acceptable timing - acceptable (~0ns slack) net caps – no violations signal transition times – no violations Any “routes” done to gather information for a timingdriven placement will be discarded Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-3 Grid-based Routing (1/2) What is Routing? Draw DRC-correct metal shapes for all interconnect wire while maintaining circuit timing, clock skew, signal net transition and capacitance limits Astro is a grid-based router Each metal layer has its own, possibly unique, grid and preferred routing direction Metal shapes implementing wires will be centered on the grid points A series of grid points in a line is called a metal “track” while unoccupied, a trace when occupied Track spacing values are set in the technology file Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-4 Grid-based Routing (2/2) track trace prBoundary row unitTile pitch channel Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-5 Design Rule Check or DRC Physical domain – mask design rules Wire spacing & width area check Via considerations Many other rules related to device (transistor) formation Built-in DRC is used for simple verification only, you should use other tools for sign-off. width check outside spacing check enclosure spacing check inside spacing check 6-6 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Wire Parasitic RC Extraction Astro contains an LPE (Layout Parasitic Extraction) engine LPE automatically calculates wire parasitic RCs from wire shape data Parasitic RC values are used to calculate the wire delays for timing analysis After detailed routing, all wire RCs are re-calculated using the actual metal shapes for the nets TLU or TLU+ models are used by LPE for wire delay calculations Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-7 Route Operations in Astro There are 4 routing operations that Astro performs: Global Route Track Assignment Detailed Route Search and Repair Route Operations, relative run time 20 18 16 14 12 10 8 6 4 2 0 Clk Route global route Track Assign Detail Route Route Opt S&R Each clock and signal net is global routed, track assigned and detailed routed Each clock and signal net may be rerouted during search & repair Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-8 Global Route (1/2) During global route (Groute), Astro assigns nets to the global routing cells (Gcell or GRcell) through which they will pass. Groute avoids obstacles and makes routes that do not create congested areas. The metal layer used for net routing in each Gcell is also assigned during Groute. For each Gcell, routing capacity is calculated according to the blockages, pins, and routing tracks inside the cell. Astro calculates the demand for wire tracks in each global routing cell. This is the basis for congestion analysis. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-9 Global Route (2/2) Astro may reduce overloaded Gcells by detouring nets around congested areas Detours increase wire length, hence increase wire delay Pre-routed wires are considered, block-ages to new signal routes A new congestion map is available after Groute Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-10 Track Assignment Track assignment selects tracks within Gcells to be used for routing each net Track assignment operates on the entire design at once attempting to: Make long, straight routes Reduce the number of vias Net connection is complete, but many DRC violations are expected (shorts) Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-11 Detail Route (1/2) Detailed route works to clear all the DRC violations left by the track assignment stage Track Assignment Global Route Detail Route Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-12 Detail Route (2/2) The detail router divides the chip area into switch boxes A switch box aligns SBox Boundary GCell Grid to Gcell boundaries Each switch box is overlapped with its neighbor by 1 Gcell Detail router generates the detailed routing one switch box at a time Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-13 Search & Repair During S&R, Astro searches for design rule violations and reroutes wires in an effort to fix them Multiple passes with different sized SBoxes are conducted If DRC violations cannot be cleared in ~50 S&R loops: Check the GR congestion map If only a handful of errors remain, try cleaning them up interactively with the axgQuickSignalRoute command Check layouts for unreachable pins Create or free up routing resources Floorplan changes Removing routing obstructions Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-14 General Flow for Routing Placement & CTS P/G Route Set Routing Options Route Clock Nets Global Route Global Route Opt. Track Assign Detail Route Design for manufacturability Search & Repair Optimize Routing Post-route CTO ECO Route Post-route Opt. In-route Opt. = 6-15 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Routing P/G Route Set Routing Options Route Clock Nets Route Signal Nets Optimize Routing Post-route CTO Post-route Optimization Post-route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-16 Routing P/G Route Set Routing Options Route Setup > Route Common Options Route Clock Nets Route Signal Nets Optimize Routing Post-route CTO ECO Route Post-route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-17 Set Routing Options Select options to match the design requirements before each routing command To minimize clock skew, Set Clock Routing option to “balanced”. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-18 Routing P/G Route Set Routing Options Route Clock Nets Route > Route Net Group Route Signal Nets Optimize Routing Post-route CTO ECO Route Post-route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-19 Route Clock Nets Skew control and insertion delay targets easier to meet if these nets are routed first Command can also be used to route critical signals or busses separately Route all clock nets at once! Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-20 Routing P/G Route Set Routing Options Route Clock Nets Route Signal Nets Route > Global Route & Route > Auto Route & Route > Search and Repair Optimize Routing Post-route CTO ECO Route Post-route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-21 Route Signal Nets Determine if GRoute optimization should be performed Auto-Route does not offer an option to run GRoute optimization Global Route Auto-Route complete GRoute, Track Assignment, no Detail Route in a slack < GRoute PPO 2 optimization single step yes AutoRoute Track Assignment Detail Route Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-22 Global Route Optimization Perform setup time, hold time, max transition, max capacitance fixing by cell sizing and buffer insertion. Must either select “ECO Route” option or re-run global route after this optimization is completed Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-23 Routing P/G Route Set Routing Options Route Clock Nets Route Signal Nets Optimize Routing Route > Post Route Optimization Post-route CTO ECO Route Post-route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-24 Optimize Routing Optimize the routing by reducing wire length, the number of vias, and removing unnecessary jogs If the process is new or unproven, the reduction in via counts and increase in long straight routes may improve yield Skip this step if timing is already met and the process is mature Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-25 Routing P/G Route Set Routing Options Route Clock Nets Route Signal Nets Optimize Routing Post-route CTO Clocks > Post Route CTO ECO Route Post-route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-26 Post-route CTO Clock skew may have been disturbed by previous routing and route optimization activity Do CTO only if preceding route or optimization activity has perturbed the clock skew. You may consider it also if timing is marginally negative and tightening the clock skew might close timing. Can specify specific Clock Nets for optimization with astClockOptions command Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-27 Routing P/G Route Set Routing Options Route Clock Nets Route Signal Nets Optimize Routing Post-route CTO ECO Route ECO > ECO Route – Design ECO Post-route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-28 Post-CTO ECO Route First, select CTS nets “minor change only” in the Route Common Option form No Track Assignment or GRoute is necessary, so deselect them on the form To minimize disruption to existing routes: Select “utilize” for dangling wires Reroute “modified nets first” Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-29 Routing P/G Route Set Routing Options Route Clock Nets Route Signal Nets Optimize Routing Post-route CTO ECO Route Post-route Optimization Route > Post Route Optimization In-route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-30 Post-route Optimization Do it if timing is not met or any trans/cap violations Performs cell sizing, buffer and inverter insertion Strong hold time fixing Topology based optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-31 Routing P/G Route Set Routing Options Route Clock Nets Route Signal Nets Optimize Routing Post-route CTO ECO Route Post-route Optimization In-route Optimization Route > In Route Optimization Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-32 In-route Optimization Does “in-route” extraction: Fast incremental mode Runs/updates as routes change ~5% more pessimistic than normal post-route extraction Most useful for cross-talk fixes Used when a very small increase in timing performance is required and other optimizations have stalled Can have a long runtime Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-33 Lab 1-6 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 6-34 Cell-Based IC Physical Design and Verification with Astro DFM General Astro Flow Design Setup Design Setup Gate-level Gate-level Netlist Netlist Floorplanning Floorplanning Timing Setup Timing Setup Placement Placement GDSII GDSII Layout Layout CTS CTS Routing Routing Design for Manufacturing Design for Manufacturing Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Unit1 Unit1 Unit2 Unit2 Unit3 Unit3 Unit4 Unit4 Unit5 Unit5 Unit6 Unit6 Unit7 Unit7 7-2 Design state at the start of DFM Standard cells are placed Clock tree and HFN buffers placed All clock, signal and P/G nets have been completely routed All route related optimizations are completed: Setup and Hold time: met Maximum capacitance limits - met Maximum signal transition times – met Design is DRC clean Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-3 Manufacturability Issues Astro can address several issues to increase manufacturing yield: Gate Oxide integrity antenna fixing Via resistance and reliability extra contacts Metal erosion metal slotting Metal liftoff metal slotting Metal Over-Etching metal fill Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-4 Problem: Gate Oxide Integrity Metal wires (antennae) placed in an EM field can generate voltage gradients During the metal etch stage, strong EM fields are used to stimulate the plasma etchant Resultant voltage gradients at MOSFET gates can damage the thin oxide • Oscillating charges in Plasma Etch Damaged Gate Oxide Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-5 Antenna Rules As length of wire increases during processing, the voltage stressing the gate oxide increases Antenna rules define acceptable length of wires Antenna Ratios: Area of Metal Connected to Gate Combined Area of Gate Or Area of Metal Connected to Gate Combined Perimeter of Gate gate poly diffusion 7-6 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Solution 1: Splitting Metal or Layer Jumping Before metal splitting unacceptable antenna length gate driver After metal splitting to meet Antenna rules gate driver acceptable antenna length Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-7 Solution 2: Inserting Diodes Before inserting diodes • Diode Inhibits charge oscillation in metal tracks During etch phase, the diode clamps the voltage swings Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-8 Antenna Fixing Flow Routing & related Routing & related Routing & related optimizations Routing & related optimizations Routing & related optimizations optimizations optimizations Route DRC violations? No Set antenna rules Search & Repair Insert Antenna Diodes for all remaining violations Yes Search & Repair Remaining Design for Manufacturability Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-9 Via Resistance and Reliability Replacing one contact with multiple contacts can improve yield & timing (series R reduction) Inserts multiple contacts without rerouting extra vias added Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-10 Problem: Metal Erosion The wafer is made flat (planarized) by a process called Chemical Mechanical Polishing (CMP) Metals are mechanically softer than dielectrics: CMP leaves metal tops with a concave shape - dishing The wider the metal the more pronounced the dishing Wide traces with little intervening dielectric and can become quite thin – dishing this severe is called erosion Process rules specify maximum metal density per layer to minimize erosion Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-11 Problem: Metal Liftoff Conductors and Dielectrics have different coefficients of thermal expansion: Stress builds up with temperature cycling Metals can delaminate (lift off) with time Wide metal traces are more vulnerable than narrow ones Maximum metal density rules also address this issue Metal thermal expansion Metal Dielectric Dielectric thermal expansion Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-12 Solution: Metal Slotting Slotting wide wires reduces the metal density Slots minimize stress buildup, reducing liftoff tendency Primarily used on Power and Ground traces: Can apply to any other net if wide enough Slotting parameters can be set layer by layer SideClearance OpenSlot SideSpace Width EndSpace Length Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-13 Problem: Metal Over-Etching A narrow metal wire separated from other metal receives a higher density of etchant than closely spaced wires The narrow metal can over-etch Minimum metal density rules are used to control this Plasma Etchant Less etchant per wire More etchant per wire 7-14 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro Solution: Metal Fill Fills empty tracks with metal shapes to meet the minimum metal density rules Uses up most of the remaining routing resource: No further routing or antenna fixes can be done Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-15 Final Validation From antenna and DFM steps Generate a PARA view Output GDS2 Generate output netlist Write .spef file Astro Calibre LEC PrimeTime timing engine Detailed DRC & LVS. Prove logical equivalence after Astro optimizations Validate Astro’s timing results Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-16 Final Validation: wire parasitics (PARA) Generate a PARA view using: Astro LPE or Star-RCXT called from Astro PARA contains extracted, parasitic RC values for nets PARA view is used inside Astro for: Timing, skew or crosstalk analysis Speeds up processing since no net RC re-extration is required Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-17 Final Validation: wire parasitics (spef) Wire parasitics for external STA are provided via a .spef file The .spef file can be generated from the PARA view or from the internal LPE of Astro: In the Timing Setup: Parasitic Tab select “LPE” or “DB” Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-18 Final Validation: Netlist Output Netlists for STA (Static Timing Analysis) do not require output of “Physical only cells” like: Corner Pad Cells Pad/ Core Filler Cells Unconnected Cell instances Exception: Physical only cells are needed for LVS when there are unconnected cell instances (spare cells) The top-level netlist generated from the EXP view is flat Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-19 Final Validation: Hierarchical Netlist Output Write out a hierarchical Verilog netlist Hierarchy must have been preserved before any: Netlist change HFN re-synthesis step CTS Logic or buffering optimization Hierarchical netlists allow re-use of existing test benches for logic verification Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-20 Lab 1-7 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 7-21 Cell-Based IC Physical Design and Verification with Astro CIC Specific Items Outline Cell-based Design Kit provided by CIC Taped-out via CIC What should be prepared? Post-layout Physical Verification Design Rule Check (DRC), Electrical Rule Check (ERC) Layout Versus Schematic (LVS) Post-layout Function and Timing Verification Gate level Transistor level Post-layout Power Analysis Transistor level Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-2 CIC Provides 0.35um Cell-Based Design Kit (TSMC/TSMC) TSMC core and IO library for TSMC 0.35um process Apply memory blocks on CIC’s web site 0.18um Cell-Based Design Kit (UMC/Artisan) Artisan core and IO library for UMC 0.18um process Memory generator included 0.18um Cell-Based Design Kit (TSMC/Artisan) Artisan core and IO library for TSMC 0.18um process Memory generator included Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-3 0.35um CBDK (TSMC/TSMC) Location of Astro Library Data your_path/CBDK035_TSMC_TSMC/CIC/Apollo/ File Descriptions PDS-030612-00-001.pdf stout.map tsmc35_4lm.tf tcb773p tpz773pn tpz773pn_analog itfplus/t035p2p4mm.itf itfplus/t035p2p4mm.tluplus itfplus/t035p2p4mm.map Application Notes Layer Mapping File Technology File Core Library Digital IO Library Analog IO Library Tech File TLU+ RC Model Mapping File Location of Cell’s Documents your_path/CBDK035_TSMC_TSMC/CIC/doc/ Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-4 0.35 TSMC/TSMC CBDK (P/G IO) Power Pads Core VDD IO VDD PVDD1Z PVDD2Z PVDD3Z Ground Pads Core VSS IO VSS PVSS1Z PVSS2Z PVSS3Z Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-5 0.35 TSMC/TSMC CBDK (Special Cells) Core Fillers FEED1, FEED2 IO Fillers PFEED20Z, PFEED10Z, PFEED8Z, PFEED5Z, PFEED4Z, PFEED2Z, PFEED1Z Overlapped IO Fillers PFEED1Z Buffers for CTS BUF6, BUF5, BUF4, BUF3, BUF2, BUF1 Delay elements for CTS DEL5, DEL3, DEL2 Corner Pad PCORNERZ Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-6 0.18um CBDK (UMC/Artisan) Location of Astro Library Data your_path/CBDK018_UMC_Artisan/CIC/Astro/ File Descriptions PDS-030328-00-002.pdf stout.map umc18_CIC.tf umc18_fram umc18io3v5v_5lm itfplus/mixed18.itf itfplus/mixed18.tluplus itfplus/mixed18.map Application Notes Layer Mapping File Technology File Core Library IO Library Tech File TLU+ RC Model Mapping File Location of Cell Documents your_path/CBDK018_UMC_artisan/CIC/doc/ Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-7 0.18 UMC/Artisan CBDK (P/G IO) Power Pads Core VDD IO VDD PVDDC PVDDR Ground Pads Core VSS IO VSS PVSSC PVSSR Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-8 0.18 UMC/Artisan CBDK (Special Cells) Core Fillers FILL64, FILL32, FILL16, FILL8, FILL4, FILL2, FILL1 IO Fillers PFILL, PFILL_9, PFILL_1, PFILL_01 Overlapped IO Fillers PFILL_01 Buffers for CTS CLKBUFXL, CLKBUFX1, CLKBUFX2, CLKBUFX3, CLKBUFX4, CLKBUFX8, CLKBUFX12, CLKBUFX16, CLKBUFX20 Delay elements for CTS DLY1X1, DLY2X1, DLY3X1, DLY4X1 Corner Pad PCORNER Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-9 Taped-out via CIC Before taped-out, make sure that your design is DRC clean. your design passes the black-box LVS check. your design meet the timing/power specification. When taped-out via CIC, prepare the following: GDSII layout of your design Calibre DRC report file Calibre LVS report file Post-layout timing/power verification result Specification files of used memories For 0.18 UMC/Artisan CBDK, 0.18 TSMC/Artisan CBDK Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-10 Post-layout Physical Verification (0.35 TSMC) DRC/ERC Calibre –drc –hier Calibre-drc-cur LAYOUT LAYOUT SOURCE SOURCE PATH "./CHIP.gds" PRIMARY "CHIP“ PRIMARY "CHIP" PATH "./CHIP.spi" modify the header LVS Add Texts for LVS in Astro dbAllowToAddPGIOText #t dbAddIOText (geGetEditCell) "pad" "netName" 40 20 Select “Pin/Net Options Output Net As Text” when streaming out. v2lvs –v CHIP_pr_lvs.vg –l tsmc35_lvs.v –o CHIP.spi – s tsmc35_lvs.spi –c cic_ –n calibre –lvs –spice layout.spi –hier –auto Calibrelvs-cur Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-11 Post-layout Physical Verification (0.18 UMC) DRC/ERC Calibre –drc –hier Calibre-drc-cur LAYOUT LAYOUT SOURCE SOURCE PATH "./CHIP.gds" PRIMARY "CHIP“ PRIMARY "CHIP" PATH "./CHIP.spi" modify the header LVS Add Texts for LVS in Astro dbAllowToAddPGIOText #t dbAddIOText (geGetEditCell) "pad" "netName" 103 20 Select “Pin/Net Options Output Net As Text” when streaming out. v2lvs –v CHIP_pr_lvs.vg –l umc18_lvs.v –o CHIP.spi –s umc18_lvs.spi –c cic_ –n calibre –lvs –spice layout.spi –hier –auto Calibre-lvs-cur Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-12 Post-layout Timing Verification Gate Level Output hierarchical Verilog netlist in Astro. Output SDF timing information in Astro. Proceed gate-level simulation as you did after synthesis. Transistor Level Must be done in CIC’s post-layout verification system (PVS) Apply for the PVS account in http://www2.cic.org.tw/WSAccount/index.html Portal telnet://queue.cic.org.tw Refer to the application note (PDS-031218-00-002.pdf) for the detail Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-13 Replace Layout / LPE Qentry –M {LPE} –tech {UMC18|TSMC25|TSMC35} –f GDSII –T Top_cell_name –s Ram_spce_filename –t {ra1sd|ra1sh|ra2sd|ra2sh|rf2sh|18ra1sh_1|18ra1sh_2|18ra2sh} –c {UMC18|TSMC25|TSMC35} –i {UMC18|TSMC25|TSMC35} –o Netlist_file_name Example: Qentry –M LPE –tech UMC18 –f CHIP.gds –T CHIP –s RAM1.spec –t 18ra2sh –s RAM2.spec –t 18ra1sh_1 –s RAM3.spec –t 18ra1sh_2 –c UMC18 –i UMC18 –o CHIP.netlist Use Qstat to check the status of your job. The result is stored in “result_#” directory. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-14 Edit Files for Running Nanosim (1/2) Stimulus File (is=vec)(en=input.dat)(ot=CLOCK,START,IN[7:0]); Input Pattern File ; time radix io high 3.3 low 0.0 25 50 75 100 . . . . . CLOCK 1 i START 1 i IN[7:0] 44 ii 0 1 0 1 0 0 0 1 xx xx xx ff Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-15 Edit Files for Running Nanosim (2/2) Spice Header File Modify PVT .lib 'l18u18v.012' L18U_BJD .lib 'l18u18v.012' L18U18V_TT .lib 'l18u33v_g2.011' l18u33v_tt *epic tech="voltage 3.3“ *epic tech="temperature 100" Configuration File bus_notation [ : ] set_node_v DVDD 3.3 set_node_gnd DGND set_node_v VDD 1.8 set_node_gnd GND print_node_logic CLOCK Refer to Nanosim Training course for the detail Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-16 Tricks to Get the Input Pattern File Add the following descriptions in your Verilog test bench: integer outf; initial begin outf = $fopen("input.dat"); . . . . . $fclose(outf); $finish; end always @(clock or start or in) $fdisplay(outf,"%t %b %b %h",$time,clock,start,in); Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-17 Running Nanosim Qentry –M {NANOSIM} –n {CHIP.io} –nspice CHIP.netlist spice.header –m Top_cell_name –c {CHIP.cfg} –z {CHIP.tech.z} –o Output_file_name –t Total_simulation_time Example: Qentry –M NANOSIM –n CHIP.io –nspice CHIP.netlist spice.header –m CHIP –c CHIP.cfg –z CHIP.tech.z –o UMC18 -t 100 Use Qstat to check the status of your job. The result is stored in “result_#” directory. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-18 View Simulation Result NOVAS nWave A waveform viewer which supports Nanosim output waveform format. Environment setup unix% set path=($path /usr/debussy/bin) unix% setenv LM_LICENSE_FILE 5219@license_server_name Starting nWave unix% nWave & Refer to Debussy training course for the detail. Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-19 Power Analysis using Nanosim Add the following statement in the configuration file : report_node_powr example : report_node_powr VDD Check nanosim.log Current information calculated over the intervals: 0.00000e+00 1.00010e+03 ns Node: VDD Average current : -3.53355e+05 uA RMS current : 3.53388e+05 uA Current Current Current Current Current peak peak peak peak peak #1 #2 #3 #4 #5 : : : : : -4.54061e+05 -4.34973e+05 -3.88048e+05 -3.87280e+05 -3.84302e+05 . . . . . . uA uA uA uA uA at at at at at 6.78400e+02 4.00000e-01 2.59000e+01 1.27500e+02 5.77800e+02 ns ns ns ns ns Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-20 Lab 1-8 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-21 Lab 2 Chip Implementation Center / Design Service Department / Physical Design Section / C.S.Chen Cell-Based IC Physical Design and Verification with Astro 8-22 Astro Laboratory Exercise Design Preparation unix% cp /**********/astro_lab_2004_07.tar.gz ~/ unix% gzip –dc astro_lab_2004_07.tar.gz | tar xvf Table I DESIGN DATA Gate Level Netlist IO Constraint File Timing Constraint File Technology File (Add it by yourself) Layer Mapping File Antenna Rules ~/astro/Lab1/tech/stout.map ~/astro/Lab1/tech/antenna_rules.cmd ask the instructor Lab1 FILE OR DIRECTORY ~/astro/Lab1/design_data/CHIP.vg ~/astro/Lab1/design_data/io.tdf ~/astro/Lab1/design_data/CHIP.sdc ~/astro/Lab1/tech/umc18_CIC.tf Reference Library (Memory) ~/astro/Lab1/ref_lib/hdsramsp512x32 Reference Library (Core) Reference Library (IO) TLU+ Data Script Files ~/astro/Lab1/ref_lib/umc18_fram ~/astro/Lab1/ref_lib/umc18io3v5v_5lm ~/astro/Lab1/star_rcxt/ ~/astro/Lab1/scripts/ Table II Lab2 DESIGN DATA Gate Level Netlist IO Constraint File Timing Constraint File Running Directory Running Scripts FILE OR DIRECTORY ~/astro/Lab2/design_data/pmult32_syn.vg ~/astro/Lab2/design_data/iopin.tdf ~/astro/Lab2/design_data/pmult32_pr.sdc ~/astro/Lab2/run/ ~/astro/Lab2/scripts/ Directory for Physical Verification ~/astro/Lab2/verify/ Environment Setup unix% source ****************************** ask the instructor Chip Implementation Center – Design Service Department – Digital Technology Section 1 Lab1-1 Design Setup 1. Change directory to lab1_1 unix% cd ~/astro/Lab1/lab1_1 unix% Astro –cmdd logs/CHIP –logd logs/CHIP& 建立新的 Library。 “ Library > Create ” Library Name Technology File Name Hierarchy Separator Set Case Sensitive sparc ../tech/umc18_CIC.tf . Enable 2. 按 OK。 3. 加入 Reference Library，包括 umc18 的 standard cell、io pad、sram 的 library。 “ Library > Add Ref ” Library Name sparc Ref Library Name ../ref_lib/umc18_fram 按 Apply。 Library Name sparc Ref Library Name ../ref_lib/umc18io3v5v_5lm 按 Apply。 Library Name sparc Ref Library Name ../ref_lib/hdsramsp512x32 按 OK。 檢查 library 是否加入正確。 “ Library > Show Refs ” Library Name sparc 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 2 4. “ Tools > Data Prep ” “ Netlist In > Verilog In ” Verilog File Name Verilog List File Name Library Name Tech File Name HDL To GDSII Map File Bus Naming Style Verilog Model Directory Model File Extension Net Name for 1’b0 Net Name for 1’b1 Hierarchy Seperator Bus Name Append Multiple PG Nets Set Case Sensitive No Backslash Insertion to avoid Hier Name Collisions Remove First Backslash Of All Escaped Identifiers Create Bus for Undefined Cells Disable Enable Disable Disable From Connect .v, .V GND VDD . [%d] sparc ../design_data/CHIP.vg 按 OK。 檢查 sparc library 裡是否多了 NETL 的資料夾。 5. Expand the Netlist “ Netlist In > Expand ” Library Name Unexpanded Cell Name Expanded Cell Name Precede hierarchical names with “/” Expand netlist cell with no instance Stop at FRAM view cells only Print out net has a pin but no connections sparc CHIP.NETL CHIP.EXP Disable Enable Disable Disable 按 Global Net Options。 Mode Net Name Add VDD Port Pattern VDD 按 Apply，分別加入 VDD、GND，每加入一個，Number Defined 會加 1。加完最後一個之後， 按 Hide，再按 OK 。 Expand 結束後 sparc 裡會多出一個 EXP 的資料夾。 Chip Implementation Center – Design Service Department – Digital Technology Section 3 6. 開啟 Library 並建立新的 Cell “ Tools > Astro ” “ Library > Open ” Library Name Library Path sparc 按 OK。 “ Cell > Create ” Cell Name CHIP 按 OK。 此時會開啟一個新的 CELL window。 7. 將 CHIP.EXP bind 到 CHIP.CEL 中 “ Design Setup > Bind Netlist ” Net Cell CHIP.EXP 按 OK。 在 CELL window 上按 “ 8. f ”，看看 design 是否有 bind 進來。 保留 Hierarchy 名稱，以便 post-layout simulation 時不需再改 test bench。 “ Cell > Initialize Hierarchy Information ” Flattened Cell Name (.EXP .CEL) Hierarchical Top Cell Name (.NETL) CHIP.CEL CHIP.NETL 按 OK。 “ Cell > Mark Module Instances Preserved ” Flattened Cell Name (.EXP .CEL) Preserve Hierarchical Boundary for: CHIP.CEL All Module Instances 按 OK。 “ Cell > Save! ” “ Cell > Save As ” Cell Name overwrite CHIP_design_setup Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 4 Lab1-2 Floorplanning 1. Change directory to lab1_2 unix% cd ~/astro/Lab1/lab1_2 unix% Astro –cmdd logs/CHIP –logd logs/CHIP& “ Library > Open ” Library Name Library Path sparc 2. 按 OK。 “ Cell > Open ” Cell Name CHIP 按 OK。 3. 規劃 IO Pad 腳位擺放方向及位置，並編輯 io.tdf 檔供 floorplan 用(已編輯完畢)。 1 5 10 15 20 25 30 32 ipad_WATCH_RAM ipad_WATCH_PC ipad_DATAIN24 ipad_DATAIN25 ipad_DATAIN26 ipad_DATAIN27 ipad_DATAIN28 ipad_DATAIN29 ipad_DATAIN30 ipad_DATAIN31 ipad_DATAIN23 ipad_ADDRIN0 ipad_ADDRIN1 ipad_ADDRIN2 ipad_ADDRIN3 ipad_ADDRIN4 ipad_ADDRIN5 ipad_ADDRIN6 ipad_ADDRIN7 ipad_ADDRIN8 ipad_ADDRIN9 ipad_RESET core_vdd1 core_vss1 ipad_TM io_vdd1 io_vdd2 io_vdd3 io_vss1 io_vss2 io_vss3 33 cornerUL cornerUR io_vss12 ipad_DATAIN22 30 io_vdd4 opad_BYPASS_OUT opad_TEST_SO opad_Finish opad_DATAOUT31 io_vss4 opad_DATAOUT30 opad_DATAOUT29 opad_DATAOUT28 opad_DATAOUT27 io_vdd5 opad_DATAOUT26 opad_DATAOUT25 opad_DATAOUT24 32 ipad_DATAIN21 ipad_DATAIN20 ipad_DATAIN19 io_vdd12 ipad_DATAIN18 30 25 ipad_DATAIN17 ipad_DATAIN16 ipad_DATAIN15 io_vss11 ipad_DATAIN14 25 20 ipad_DATAIN13 ipad_DATAIN12 ipad_DATAIN11 core_vss4 core_vdd4 20 Core opad_DATAOUT23 core_vdd2 core_vss2 opad_DATAOUT22 opad_DATAOUT21 opad_DATAOUT20 io_vss5 opad_DATAOUT19 opad_DATAOUT18 opad_DATAOUT17 opad_DATAOUT16 io_vdd6 opad_DATAOUT15 opad_DATAOUT14 opad_DATAOUT13 opad_DATAOUT12 io_vss6 5 10 15 15 ipad_CLOCK ipad_DATAIN10 ipad_DATAIN9 ipad_DATAIN8 io_vdd11 10 ipad_DATAIN7 ipad_DATAIN6 ipad_DATAIN5 ipad_DATAIN4 io_vss10 5 ipad_DATAIN3 ipad_DATAIN2 ipad_DATAIN1 ipad_DATAIN0 1 io_vdd10 ipad_WATCH_REG ipad_LOAD_INSTR opad_DATAOUT10 opad_DATAOUT11 ipad_LOAD_RAM opad_DATAOUT0 opad_DATAOUT1 opad_DATAOUT2 opad_DATAOUT3 opad_DATAOUT4 opad_DATAOUT5 opad_DATAOUT6 opad_DATAOUT7 opad_DATAOUT8 opad_DATAOUT9 ipad_BYPASS_IN ipad_TEST_SE ipad_BistMode opad_BistFail0 opad_BistFail1 opad_ErrMap0 opad_ErrMap1 ipad_TEST_SI core_vdd3 core_vss3 io_vdd9 io_vdd8 io_vdd7 io_vss9 io_vss8 io_vss7 cornerLL cornerLR 1 1 5 10 15 20 25 30 32 Chip Implementation Center – Design Service Department – Digital Technology Section 5 umc018 使用的 P/G Pad、I/O Pad 和 Corner 名稱 core pad io pad corner input output PVDDC, PVSSC PVDDR, PVSSR PCORNER P2A P8A 由於 gate level netlist 並未加入 P/G Pad 和 Corner 的 Cell，所以必須在 tdf 中建立這些 cell，其 範例如下，其中 core_vdd1、core_vdd2、ipad_DATAIN0 等為 Instance Name，"left" 1 為其擺放 位置及順序。 io.tdf 檔(已編輯完畢) define _cell (geGetEditCell) dbCreateCellInst _cell "" "PVDDC.FRAM" "core_vdd1" "0" "NO" dbCreateCellInst _cell "" "PVDDC.FRAM" "core_vdd2" "0" "NO" ……. dbCreateCellInst _cell "" "PVSSC.FRAM" "core_vss1" "0" "NO" ……. dbCreateCellInst _cell "" "PVDDR.FRAM" "io_vdd1" ……. dbCreateCellInst _cell "" "PVSSR.FRAM" "io_vss1" ……. ;;left pad "io_vdd10" "left" 1 pad "ipad_DATAIN0" "left" 2 pad "ipad_DATAIN1" "left" 3 pad "ipad_DATAIN2" "left" 4 pad "io_vss10" "left" 5 ……. pad "cornerUL" "left" 33 ;;right pad "cornerLR" "right" 1 ……. ;;top pad "io_vdd1" "top" 1 ……. pad "cornerUR" "top" 32 ;;bottom pad "cornerLL" "bottom" 1 ……. pad "io_vdd7" "bottom" 32 "0" "NO" "0" "NO" '(0.0 0.0) '(0.0 0.0) '(0.0 0.0) '(0.0 0.0) '(0.0 0.0) Chip Implementation Center – Design Service Department – Digital Technology Section 6 4. 讀取 IO Constraints “ Design Setup > Load TDF ” Cell Name TDF File Name Overwrite ../design_data/io.tdf Enable 按 OK。 5. Floorplan 設定 “ Design Setup > Set Up Floorplan ” Control Param Core Utilization Row/Core Ratio Core Aspect Ratio(H/W) Horizontal Row Double Back Start First Row Flip First Row Core To Left Core To Right Core To Bottom Core To Top aspect ratio 0.8 1 1 Enable Enable Disable Enable 200 200 200 200 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 7 6. 設定 macro 內部的 pin 為 visible 點選 CHIP.CEL 視窗左邊的 Window option。 Visible Pin Instances macro cell 按 Apply 後再按 Redraw 然後關閉 Window Options 視窗 此時就可看見 macro 內的 power ring ， ， 和 pin 的 layout。 7. 將 macro 擺放到 core region “ Select > Select by Point ” (bind keys : p )，點選其中一個 hard macro，利用“ Modify > Move ” (bind keys : m ) 或 “ Modify > Transform ” (bind keys : t ) 將 macro 移動或翻轉 至適當位置(macro 的 pin 朝向 core 內部)。 8. 建 Power Ring 及 Straps “ PreRoute > Connect Ports to P/G ” 將 VDD, GND 分別填入，注意 Net Type 的區別。 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports VDD VDD .* .* Power Core Pad Macro, Std/Module Cell, Pad Disable Connect Enable 按 Apply。此時會跳出一個 Dialog Box 視窗，按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 8 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports GND GND .* .* Ground Core Pad Macro, Std/Module Cell, Pad Enable Connect Enable 按 OK。此時會跳出一個 Dialog Box 視窗，按 OK。 “ PreRoute > Rectangular Rings ” Around Net Name(s) Skip Side(s) L-Width / L-Layer R-Width / R-Layer B-Width / B-Layer T-Width / T-Layer Offsets Are Offsets Left Offsets Right Offsets Bottom Offsets Top All other options 60 / 52 60 / 52 60 / 50 60 / 50 Absolute 30 30 30 30 Default value Core VDD, GND 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 9 “ PreRoute > Straps ” Direction Start X Net Name(s) Width Layer Configure By Groups Step Pitch within Group Low Ends High Ends Place Straps X Increment All other options Vertical 900 VDD, GND 30 52 Groups & Step 1 0.0 30.32 At First Targets At First Targets 3 330 Default value 按 DRC。 Spacing Rule Are Treat Fat Blockages as Thin Wires Use Fat Via If Width Meets Requirement All other options Radial Enable Enable Default value 按 Hide，再按 OK。 9. I/O Pad 到 Power Ring 及 Macro Ring 到 Power Ring 的連接。 “ PreRoute > Macros/Pads ” Instance Type(s) Select Pins Automatically and Route Primary Routing Layer Horizontal Layer Vertical Layer All other options Pad All but Specified Specified 50 48 Default value 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 10 選取右上角的 macro ( bind keys : p )。 “ PreRoute > Macros/Pads ” 先按 Default Instance Type(s) Instances Skip Side(s) Select Pins Automatically and Route Primary Routing Layer All other options Macro Selected Bottom All Preferred Default value 按 OK。 按 CHIP.CEL 視窗左邊的 Deselect-all。 選取右下角的 macro。 “ PreRoute > Macros/Pads ” Instance Type(s) Instances Skip Side(s) Select Pins Automatically and Route Primary Routing Layer All other options Macro Selected Top All Preferred Default value 按 OK。 按 CHIP.CEL 視窗左邊的 Deselect-all。 10. 建立 Placement Blockage 在 macro 周圍 “ PrePlace > Create Hard Blockage ” 直接在 CELL Window 上面建立 Placement Blockage 範圍。 Chip Implementation Center – Design Service Department – Digital Technology Section 11 11. “ Cell > Save! ” “ Cell > Save As ” Cell Name CHIP_floorplan overwrite Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 12 Lab1-3 Timing Setup 1. Change directory to lab1_3 unix% cd ~/astro/Lab1/lab1_3 unix% Astro –cmdd logs/CHIP –logd logs/CHIP& “ Library > Open ” Library Name Library Path sparc 2. 按 OK。 “ Cell > Open ” Cell Name CHIP 按 OK。 3. Attach TLU+ to MilkyWay Database “ Tools > DataPrep ” “ Tech File > ITF to TLU+ ” Library Name LPE Mode Nom Cap Table File Nom ITF File Star-RCXT Mapping File sparc delete all capacitance tables Enable NOM ../star_rcxt/mixed18.tluplus ../star_rcxt/mixed18.itf ../star_rcxt/mixed18.map 按 OK。 4. Configuring Timing Setup Panel “ Tools > Astro ” “ Timing > Timing Setup ” 選取 Environment tab Ignore Interconnect Ignore Clock Uncertainty Enable Time Borrowing Ignore Propagated Clock Disable Disable Enable Enable Enable Ideal Network Delay Enable 設定完記得先按 Apply ，再選取 Parasitics tab。 Operating Cond Max, Min Capacitance Model TLU+ 按 Apply，再選取 Model tab。 Chip Implementation Center – Design Service Department – Digital Technology Section 13 Operating Cond Max, Min Delay Model Elmore 按 Apply，再按 Hide 關閉 Timing Setup Pannel。 5. Load Synopsys Design Constraints (已編輯完畢) CHIP.sdc 檔 set sdc_version 1.2 create_clock -period 20 -name CLOCK -waveform {0 10} [get_pins {ipad_CLK/Y}] set_clock_uncertainty 1 -setup [get_clocks {CLOCK}] set_clock_latency 1 [get_clocks {CLOCK}] set_input_delay 1.5 -clock "CLOCK" [get_ports [all_inputs]] set_output_delay 2.5 -clock "CLOCK" [get_ports [all_outputs]] set_drive 1 [get_ports [all_inputs]] set_load -pin_load 1 [get_ports [all_outputs]] set_load -min -pin_load 1 [get_ports [all_outputs]] 在 Message/Input Area 輸入 ataRemoveTC “ Timing > Load SDC ” SDC File Name SDC File Bus Naming Style SDC File Hierarchy Separator ../design_data/CHIP.sdc [%d] / 按 OK。 確認是否全部的 constraints 都有下到。 “ Timing > Timing Data Check ” 6. “ Cell > Save! ” “ Cell > Save As ” Cell Name CHIP_timing overwrite Enable Default 值，按 OK。 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 14 Lab1-4 Placement 1. Change directory to lab1_4 unix% cd ~/astro/Lab1/lab1_4 unix% Astro –cmdd logs/CHIP –logd logs/CHIP& “ Library > Open ” Library Name Library Path sparc 2. 按 OK。 “ Cell > Open ” Cell Name CHIP 按 OK。 3. Detach Scan Chain，因為 Scan Chain 會造成高的 congestion。 “ PrePlace > Trace Scan Chain ” Start Port Name Of Instance Name Allow Buffers Allow Muxes Mux Master Name(s) Specify Chain End End Port Name End Instance Name Enable A opad_TEST_SO Y cell instance ipad_TEST_SI Enable Buffer Master Name(s) .*INV.*, .*BUF.* Disable 按 OK。 “ PrePlace > Optimize/Delete Scan Chain ” Chain Name Pattern match Option Mode .* Enable Allow New Module Ports Delete only 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 15 4. Pre-Placement “ InPlace > Placement Common Options ” Optimization Mode All other options Congestion, Timing No Cells under Preroute of M1, M2, M3, M4, M5 Default value 按 OK。 “ PrePlace > Pre-Placement Optimization ” Default 值，按 OK。 “ Timing > Timing Report ” Setup Slack Slack Num Default 值，按 OK。 Hold Slack Slack Num Num Trans Num MaxCap 5. “ PreRoute > Connect Ports to P/G ” 將 VDD, GND 分別填入，注意 Net Type 的區別。 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports VDD VDD .* .* Power Core Pad Macro, Std/Module Cell, Pad Disable Connect Enable 按 Apply。 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports GND GND .* .* Ground Core Pad Macro, Std/Module Cell, Pad Enable Connect Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 16 “ PreRoute > Standard Cells” Default 值，按 OK。 6. InPlace “ InPlace > Design Placement ” Speed Mode In-Placement Optimization Routability v.s. Timing bar medium congestion + timing Enable 5 按 OK。 7. 觀察 Congestion 及 Critical Path “ InPlace > Display Timing Map ” 按 Clear，再按 Cancel。 “ InPlace > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。 “ Timing > Timing Report ” Setup Slack Slack Num Default 值，按 OK。 Hold Slack Slack Num Num Trans Num MaxCap Chip Implementation Center – Design Service Department – Digital Technology Section 17 8. “ PostPlace > Post-Place Optimization Phase 1 ” Optimization Effort Re-do HFN Synthesis Setup Fixing Hold Fixing Design Rule Fixing Fix Max Length Fix Tran/Cap Prevent Xtalk LOW Enable Using Global Routing Enable Enable Disable Enable Disable Enable Disable 按 OK。 “ Timing > Timing Report ” Setup Slack Slack Num Default 值，按 OK。 Hold Slack Slack Num Num Trans Num MaxCap 9. “ Cell > Save! ” “ Cell > Save As ” Cell Name CHIP_placed overwrite Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 18 Lab1-5 CTS (Clock Tree Synthesis) 1. Change directory to lab1_5 unix% cd ~/astro/Lab1/lab1_5 unix% Astro –cmdd logs/CHIP –logd logs/CHIP& “ Library > Open ” Library Name Library Path sparc 2. 按 OK。 “ Cell > Open ” Cell Name CHIP 按 OK。 3. 4. 5. 6. “ Clock > Clock Common Options ” Default 值，按 OK。 “ Clock > Clock Tree Synthesis ” Default 值，按 OK。 在 Message/Input Area 輸入 “ atCmdFreeTimer ” 來更新 timing view。 “ Clock > Skew Analysis ” Default 值，按 OK。 Global Skew CLOCK Longest Delay Shortest Delay 7. “ Timing > Timing Setup ” 選取 Environment tab Ignore Interconnect Ignore Clock Uncertainty Enable Time Borrowing Ignore Propagated Clock Enable Ideal Network Delay Disable Enable Enable Disable Disable 按 Apply，再按 Hide 關閉 Timing Setup Pannel。 Chip Implementation Center – Design Service Department – Digital Technology Section 19 8. 重新連接 Scan Chain “ PrePlace > Optimize/Delete Scan Chain ” Chain Name Pattern match Option Mode .* Enable Allow New Module Ports Optimize 按 OK。 9. “ Timing > Timing Report ” Setup Slack Slack Num Default 值，按 OK。 Hold Slack Slack Num Num Trans Num MaxCap 10. “ PostPlace > Post Placement Optimization ” Default 值 11. “ Timing > Timing Report ” Setup Slack Slack Num Default 值 Hold Slack Slack Num Num Trans Num MaxCap 12. “ Cell > Save! ” “ Cell > Save As ” Cell Name CHIP_cts overwrite Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 20 Lab1-6 Routing 1. Change directory to lab1_6 unix% cd ~/astro/Lab1/lab1_6 unix% Astro –cmdd logs/CHIP –logd logs/CHIP& “ Library > Open ” Library Name Library Path sparc 2. 按 OK。 “ Cell > Open ” Cell Name CHIP 按 OK。 3. 在 Placement Optimization 時有些 gate 或 buffer 可能被加入或拿掉，所以必須重新再作一次 Power/Ground Connection。 “ PreRoute > Standard Cells ” Default 值，按 OK。 4. “ Route Setup > Route Common Options ” Global Routing Clock Routing Track Assign Detail Routing Same Net Notch All other options Timing Driven balanced Timing Driven connect tie off, connect open nets check and fix Default value 按 OK。 5. “ Route > Route Net Group ” Net Name(s) From: Phase Search Repair Loop Dangling wires All other options All clock nets global, track assign, detail 5 Discard Optimize routing pattern Enable Default value “ Route > Global Route ” Default 值，按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 21 6. “ Timing > Timing Report ” Setup Slack Slack Num Default 值，按 OK。 Hold Slack Slack Num Num Trans Num MaxCap 7. 觀察 congestion 情況 “ Route > Estimate Global Route Congestion! ” “ Route > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。 congestion 結果 ok，則不需作 Global Route Optimization。 8. 9. “ Route > Auto Route ” Default 值，按 OK。 “ Timing > Timing Setup ” 選取 Model tab Operating Cond Delay Model Max, Min AWE 按 Apply。 10. “ Timing > Timing Report ” Setup Slack Slack Num Default 值，按 OK。 Hold Slack Slack Num Num Trans Num MaxCap 11. 若有 DRC violations，則需使用 Search & Repair 去修正。 “ Route > Search and Repair ” Search Repair Loop 20 All other options Default value 按 OK。 12. 作最後的 Optimize “ Route > Post Route Optimization ” Default 值，按 OK。 13. “ Timing > Timing Report ” Setup Slack Slack Num Default 值，按 OK。 Hold Slack Slack Num Num Trans Num MaxCap Chip Implementation Center – Design Service Department – Digital Technology Section 22 14. “ Cell > Save! ” “ Cell > Save As ” Cell Name CHIP_routing overwrite Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 23 Lab1-7 DFM (Design for Manufacturing) 1. Change directory to lab1_7 unix% cd ~/astro/Lab1/lab1_7 unix% Astro –cmdd logs/CHIP –logd logs/CHIP& “ Library > Open ” Library Name Library Path sparc 2. 按 OK。 “ Cell > Open ” Cell Name CHIP 按 OK。 3. 加入 Antenna Rules (已修改完畢) antenna_rules.cmd define _libId (dbGetCurrentLibId) dbDefineAntennaRule _libId 2 2 0 0 dbAddAntennaLayerRule _libId 2 "met1" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met2" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met3" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met4" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met5" 400 '(0.359 0 0 999999999) 在 Message/Input Area 輸入 load “../tech/antenna_rules.cmd ” 加入 antenna rules。 “ Route Setup > HPO Signal Route Options ” 設定 antenna ratio 的計算模式 Timing-Driven Spacing Off Change-Collecting Antenna advanced 按 OK。 在 Message/Input Area 輸入 axReportAntennaRatio (geGetEditCell) Chip Implementation Center – Design Service Department – Digital Technology Section 24 如果有出現 violation (紅色框框的地方)，必須用 Search & Repair 修正。 “ Route > Search and Repair ” Default 值，按 OK。 輸入 axReportAntennaRatio (geGetEditCell) 確認 violation 是否還存在。 4. 加入 Pad Filler 和 Core Filler “ PostPlace > Add Pad Fillers ” Filler Side PFILL, PFILL_9, PFILL_1, PFILL_01 Overlap Filler PFILL_01 left, right, bottom, top 按 OK。 “ PostPlace > Add Core Fillers ” Master Cell Name(s) Without Metal Master Cell Name(s) With Metal respect hard placement blockage respect soft placement blockage between std cells only Connect to Power Net (optional) Connect to Ground Net (optional) All other options Enable Enable Enable VDD GND Default value FILL64, FILL32, FILL16, FILL8, FILL4, FILL2, FILL1 按 OK。 5. 6. “ PreRoute > Standard Cells ” Default 值，按 OK。 將單一個 via 置換成 2 個 via，作 contacts optimization 在 Message/Input Area 輸入 load “../scripts/optContacts.cmd” Chip Implementation Center – Design Service Department – Digital Technology Section 25 optContacts.cmd (已編輯完畢) axDrouteOptimizeContact (geGetEditCell) '( ("Via1" "Via1" 2) ("Via2" "Via2" 2) ("Via3" "Via3" 2) ("Via4" "Via4" 2) ) 7. 8. “ Route > Search and Repair ” Default 值，按 OK。 由於 Power Net 的寬度過大，違反 metal density rules。 “ PreRoute > Slot Wires ” Select Wires Net Name(s) CutWidth CutLength Width Length Side Space EndSpace Side Clearance End Clearance Stagger Treat Width as Treat Length as Specified VDD, GND 20 30 2 10 10 10 10 10 Enable Minimum Minimum Treat Spaces and Clearances as Maximum 按 OK。 9. “ Route Utility > Fill Notch/Gap ” Default 值，按 OK。 Default 值，按 OK。 Default 值，按 OK。 10. “ Verify > DRC ” 11. “ Verify > LVS ” 12. 作 Calibre LVS 跟 Post Layout Simulation 時要在 layout 上加上 Text 才會正確。 在 Message/Input Area 輸入 load “../scripts/add_text.cmd” add_text.cmd (已編輯完畢) dbAllowToAddPGIOText #t dbAddIOText (geGetEditCell) "*" "*" 103 20 Chip Implementation Center – Design Service Department – Digital Technology Section 26 13. “ Cell > Save! ” “ Cell > Save As ” Cell Name CHIP_dfm overwrite Enable 按 OK。 14. Stream Out GDS II “ Tools > Data Prep ” “ Output > Stream Out ” 注意 Output Net 中一定要選取 As Text，否則 LVS 會有問題。 Stream File Name Library Name Layer File Child Extraction Depth Convert Cell Name Convert Reference Lib Child Cells Flatten Fill Pin/Net Options > Output Pins Pin/Net Options > Output Net CHIP.gds sparc ../tech/stout.map 20 Specified Cell CHIP Enable Devices & Device Arrays FILL As Text As Text 按 OK。 15. SDF OUT “ Tools > Astro ” “ Timing > SDF Out ” Specify Version Operation Mode File Name Version 2.1 Normal SDF CHIP.sdf 按 OK。 16. Verilog Out PS：若無法 dump verilog netlist，必須重新修復 net 和 instance 的連線(CHIP.CEL 要先關閉後才 能執行此動作)。 “ Cell > Repair Hierarchy Information ” Flattened Cell Name(.CEL) CHIP.CEL Repair net connections and instances Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 27 “ Cell > Hierarchical Verilog Out ” ----for post layout simulation Flattened Cell Name (.EXP .CEL) Enter File Name No power/ground ports No power/ground nets Output bus as individual bits No empty Cell Module Definitions No Corner Pad Instances No Pad Filler Cell Instances No Core Filler Cell Instances No Unconnected Cell Instances No Unconnected Ports Strip BackSlash Before Hierarchy Separator No Diode Ports Output Wire Declaration 1’b1 Net Name 1’b0 Net Name Generate macro definitions CHIP.CEL CHIP_sim.vg Enable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable Enable Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for Ground(VSS, gnd, …) Enable VDD GND Disable 按 OK。 “ Cell > Hierarchical Verilog Out ” ----for caliber block box LVS Flattened Cell Name (.EXP .CEL) Enter File Name No power/ground ports No power/ground nets Output bus as individual bits No empty Cell Module Definitions No Corner Pad Instances No Pad Filler Cell Instances No Core Filler Cell Instances No Unconnected Cell Instances No Unconnected Ports Strip BackSlash Before Hierarchy Separator No Diode Ports Output Wire Declaration Generate macro definitions CHIP.CEL CHIP_lvs.vg Enable Disable Disable Enable Disable Disable Disable Disable Disable Enable Disable Enable Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for Ground(VSS, gnd, …) Disable Disable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 28 Lab1-8 Calibre DRC & LVS & Post-Layout Simulation 1. Change directory to lab1_8/drc unix% cd ~/astro/Lab1/lab1_8/drc 複製 DRC 相關檔案至 drc 的資料夾 Calibre-drc-cur 180nm_layers.cal metal_slot_0.18_1P6M-MMC-Calibre-drc-2.2-p1 CHIP.gds unix% cp ~/astro/Lab1/lab1_7/CHIP.gds . 3. 修改 Calibre-drc-cur 檔 LAYOUT PATH "./CHIP.gds" LAYOUT PRIMARY "CHIP" 4. 執行 Calibre DRC unix% calibre –drc –hier Calibre-drc-cur 觀察 drc.sum 檔看看是否有 drc error Design Kit Design Kit Design Kit Astro 2. 若有 error 則用 unix% calibre –rve drc.db Chip Implementation Center – Design Service Department – Digital Technology Section 29 可找到 drc 錯誤的數量、原因、坐標等資訊，再回到 Astro 去作修正。 5. Change directory to lab1_8/lvs unix% cd ~/astro/Lab1/lab1_8/lvs 6. 複製 LVS 相關檔案到 lvs 資料夾 CHIP.gds CHIP_lvs.vg umc18_lvs.spi umc18_lvs.v Calibre-lvs-cur unix% cp ~/astro/Lab1/lab1_7/CHIP.gds . unix% cp ~/astro/Lab1/lab1_7/CHIP_lvs.vg . 7. 產生 RAM Black Box 的 Verilog 和 Spice 檔 修改原來的 hdsramsp512x32.v 檔，只留下 module 和 input、output 的宣告。 hdsramsp512x32_lvs.v (已編輯完畢) module hdsramsp512x32 ( Q, CLK, CEN, WEN, A, D, OEN ); output [31:0] Q; input CLK; input CEN; input WEN; input [8:0] A; input [31:0] D; input OEN; endmodule 利用 v2lvs 產生 hdsramsp512x32_lvs.spi 檔 unix% v2lvs –v hdsramsp512x32_lvs.v –o hdsramsp512x32_lvs.spi Astro Astro Design Kit Design Kit Design Kit Chip Implementation Center – Design Service Department – Digital Technology Section 30 hdsramsp512x32_lvs.spi $ Spice netlist generated by v2lvs $ v9.3_1.4 Wed Mar 12 15:25:10 PST 2003 .SUBCKT hdsramsp512x32 Q[31] Q[30] Q[29] Q[28] Q[27] Q[26] Q[25] Q[24] Q[23] + Q[22] Q[21] Q[20] Q[19] Q[18] Q[17] Q[16] Q[15] Q[14] Q[13] Q[12] Q[11] Q[10] + Q[9] Q[8] Q[7] Q[6] Q[5] Q[4] Q[3] Q[2] Q[1] Q[0] CLK CEN WEN A[8] A[7] A[6] + A[5] A[4] A[3] A[2] A[1] A[0] D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] + D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[14] D[13] D[12] D[11] + D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] OEN .ENDS 8. 將 CHIP_lvs.vg 轉換成 spice 格式 unix% v2lvs –v CHIP_lvs.vg –l umc18_lvs.v –l hdsramsp512x32_lvs.v –o CHIP.spi \ –s umc18_lvs.spi –s hdsramsp512x32_lvs.spi 9. 修改 Calibre-lvs-cur SOURCE PRIMARY "CHIP" SOURCE PATH "./CHIP.spi" LAYOUT PRIMARY "CHIP" LAYOUT PATH "./CHIP.gds" 並在最後新增一行 LVS BOX hdsramsp512x32 10. 執行 Calibre LVS unix% caliber –lvs –spice CHIP.spi –hier –auto Calibre-lvs-cur 觀察 lvs.rep 找到 OVERALL COMPARISON RESULT 部份是否 match 11. Change directory to lab1_8/tbench unix% cd ~/astro/Lab1/lab1_8/tbench Chip Implementation Center – Design Service Department – Digital Technology Section 31 12. 複製相關檔案到 tbench 資料夾 CHIP_sim.v CHIP.sdf Hdsramsp512x32.v umc18.v umc18io3v5v.v IRAM.bin run.f test_postsim.v Checkfile3.golden Astro Astro Memory Compiler Design Kit Design Kit Input Pattern Simulation Script File Testbench File Simulation results (golden) unix% cp ~/astro/Lab1/lab1_7/CHIP.sdf . unix% cp ~/astro/Lab1/lab1_7/CHIP_sim.v . 13. 編輯 run.f ../test_postsim.v ../hdsramsp512x32.v ../CHIP_sim.v -v ../umc18.v -v ../umc18io3v5v.v +access+r 14. Change directory to lab1_8/tbench/run unix% cd ~/astro/Lab1/lab1_8/tbench/run 15. unix% ncverilog –f ../run.f simulation 結束後比對 checkfile3 和 checkfil3.golden 檔。 unix% diff checkfile3 ../checkfile3.golden 若兩個檔案一模一樣，表示 post-layout simulation 沒問題。 Chip Implementation Center – Design Service Department – Digital Technology Section 32 Lab2 Physical Design of a Pipelined 32x32 Multiplier 1. Change directory to Lab2/run unix% cd ~/astro/Lab2/run unix% Astro –cmdd logs/mul –logd logs/mul& 建立新的 Library。 “ Library > Create ” Library Name Technology File Name Hierarchy Separator Set Case Sensitive mul ../tech/umc18_CIC.tf . Enable 2. 按 OK。 3. 加入 Reference Library，包括 umc18 的 standard cell 的 library。 “ Library > Add Ref ” Library Name mul Ref Library Name ../ref_lib/umc18_fram 按 Apply。 檢查 library 是否加入正確。 “ Library > Show Refs ” Library Name mul 按 OK。 4. “ Tools > Data Prep ” “ Netlist In > Verilog In ” Verilog File Name Library Name Bus Naming Style Model File Extension Net Name for 1’b0 Net Name for 1’b1 Hierarchy Seperator Multiple PG Nets Set Case Sensitive No Backslash Insertion to avoid Hier Name Collisions Remove First Backslash Of All Escaped Identifiers Create Bus for Undefined Cells ../design_data/pmult32_syn.vg mul [%d] .v, .V GND VDD . Disable Enable Disable Disable From Connect 按 OK。檢查 sparc library 裡是否多了 NETL 的資料夾。 Chip Implementation Center – Design Service Department – Digital Technology Section 33 5. Expand the Netlist “ Netlist In > Expand ” Library Name Unexpanded Cell Name Expanded Cell Name Precede hierarchical names with “/” Expand netlist cell with no instance Stop at FRAM view cells only Print out net has a pin but no connections mul pmult32.NETL pmult32.EXP Disable Enable Disable Disable 按 Global Net Options。 Mode Net Name Add VDD Port Pattern VDD 按 Apply，分別加入 VDD、GND，每加入一個，Number Defined 會加 1。加完最後一個之後， 按 Hide，再按 OK 。 Expand 結束後 sparc 裡會多出一個 EXP 的資料夾。 6. 開啟 Library 並建立新的 Cell “ Tools > Astro ” “ Library > Open ” Library Name Library Path mul 按 OK。 “ Cell > Create ” Cell Name pmult32 按 OK。 此時會開啟一個新的 CELL window。 7. 將 CHIP.EXP bind 到 CHIP.CEL 中 “ Design Setup > Bind Netlist ” Net Cell pmult32.EXP 按 OK。 在 CELL window 上按 “ 8. f ”，看看 design 是否有 bind 進來。 保留 Hierarchy 名稱，以便 post-layout simulation 時不需再改 test bench。 “ Cell > Initialize Hierarchy Information ” Flattened Cell Name (.EXP .CEL) Hierarchical Top Cell Name (.NETL) pmult32.CEL pmult32.NETL 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 34 “ Cell > Mark Module Instances Preserved ” Flattened Cell Name (.EXP .CEL) Preserve Hierarchical Boundary for: pmult32.CEL All Module Instances 按 OK。 9. “ Cell > Save! ” “ Cell > Save As ” Cell Name overwrite mul_design_setup Enable 按 OK。 10. 讀取 IO Constraints “ Design Setup > Load TDF ” Cell Name TDF File Name Overwrite ../design_data/iopin.tdf Enable 按 OK。 11. Floorplan 設定 “ Design Setup > Set Up Floorplan ” Control Param Core Utilization Row/Core Ratio Core Aspect Ratio(H/W) Horizontal Row Double Back Start First Row Flip First Row Core To Left Core To Right Core To Bottom Core To Top aspect ratio 0.7 1 1 Enable Enable Enable Disable 70 70 70 70 按 OK。 12. 建 Power Ring 及 Straps “ PreRoute > Connect Ports to P/G ” 將 VDD, GND 分別填入，注意 Net Type 的區別。 Chip Implementation Center – Design Service Department – Digital Technology Section 35 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports VDD VDD .* .* Power Core Pad Macro, Std/Module Cell, Pad Disable Connect Enable 按 Apply。此時會跳出一個 Dialog Box 視窗，按 OK。 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports GND GND .* .* Ground Core Pad Macro, Std/Module Cell, Pad Enable Connect Enable 按 OK。此時會跳出一個 Dialog Box 視窗，按 OK。 “ PreRoute > Rectangular Rings ” Around Net Name(s) Skip Side(s) L-Width / L-Layer R-Width / R-Layer B-Width / B-Layer T-Width / T-Layer Offsets Are Offsets Left Offsets Right Offsets Bottom Offsets Top All other options 30 / 52 30 / 52 30 / 50 30 / 50 Absolute 5 5 5 5 Default value Core VDD, GND 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 36 13. “ Cell > Save! ” “ Cell > Save As ” Cell Name mul_floorplan overwrite Enable 按 OK。 14. Attach TLU+ to MilkyWay Database “ Tools > DataPrep ” “ Tech File > ITF to TLU+ ” Library Name LPE Mode Nom Cap Table File Nom ITF File Star-RCXT Mapping File mul delete all capacitance tables Enable NOM ../star_rcxt/mixed18.tluplus ../star_rcxt/mixed18.itf ../star_rcxt/mixed18.map 按 OK。 15. Configuring Timing Setup Panel “ Tools > Astro ” “ Timing > Timing Setup ” 選取 Environment tab Ignore Interconnect Ignore Clock Uncertainty Enable Time Borrowing Ignore Propagated Clock Disable Disable Enable Enable Enable Ideal Network Delay Enable 設定完記得先按 Apply ，再選取 Parasitics tab。 Operating Cond Max, Min Capacitance Model TLU+ 按 Apply，再選取 Model tab。 Operating Cond Delay Model Max, Min Elmore 按 Apply，再按 Hide 關閉 Timing Setup Pannel。 16. Load Synopsys Design Constraints 在 Message/Input Area 輸入 ataRemoveTC Chip Implementation Center – Design Service Department – Digital Technology Section 37 “ Timing > Load SDC ” SDC File Name SDC File Bus Naming Style SDC File Hierarchy Separator ../design_data/pmult32_pr.sdc [%d] / 按 OK。 確認是否全部的 constraints 都有下到。 “ Timing > Timing Data Check ” 17. “ Cell > Save! ” “ Cell > Save As ” Cell Name pmult32_timing overwrite Enable Default 值，按 OK。 按 OK。 18. Pre-Placement “ InPlace > Placement Common Options ” Optimization Mode All other options Congestion, Timing No Cells under Preroute of M1, M2, M3, M4, M5 Default value 按 OK。 19. “ PrePlace > Pre-Placement Optimization ” Default 值，按 OK。 “ Timing > Timing Report ” Default 值，按 OK。 20. “ PreRoute > Connect Ports to P/G ” 將 VDD, GND 分別填入，注意 Net Type 的區別。 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports VDD VDD .* .* Power Core Pad Macro, Std/Module Cell, Pad Disable Connect Enable 按 Apply。 Chip Implementation Center – Design Service Department – Digital Technology Section 38 Net Name Port Pattern Cell Master Pattern Cell Instance Pattern Net Type Net SubType Cell Types Update Tie Up/Down Mode Create Missing Ports GND GND .* .* Ground Core Pad Macro, Std/Module Cell, Pad Enable Connect Enable 按 OK。 “ PreRoute > Standard Cells” Default 值，按 OK。 21. InPlace “ InPlace > Design Placement ” Speed Mode In-Placement Optimization Routability v.s. Timing bar medium congestion + timing Enable 5 按 OK。 22. 觀察 Congestion 及 Critical Path “ InPlace > Display Timing Map ” 按 Clear，再按 Cancel。 “ InPlace > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。 “ Timing > Timing Report ” Default 值，按 OK。 23. “ PostPlace > Post-Place Optimization Phase 1 ” Optimization Effort Re-do HFN Synthesis Setup Fixing Hold Fixing Design Rule Fixing Fix Max Length Fix Tran/Cap Prevent Xtalk LOW Enable Using Global Routing Enable Enable Disable Enable Disable Enable Disable 按 OK。 “ Timing > Timing Report ” Default 值，按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 39 24. “ Cell > Save! ” “ Cell > Save As ” Cell Name mul_placed overwrite Enable 按 OK。 25. “ Clock > Clock Common Options ” Default 值，按 OK。 26. “ Clock > Clock Tree Synthesis ” Default 值，按 OK。 27. 在 Message/Input Area 輸入 “ atCmdFreeTimer ” 來更新 timing view。 28. “ Clock > Skew Analysis ” Default 值，按 OK。 Global Skew CLOCK Longest Delay Shortest Delay 29. “ Timing > Timing Setup ” 選取 Environment tab Ignore Interconnect Ignore Clock Uncertainty Enable Time Borrowing Ignore Propagated Clock Enable Ideal Network Delay Disable Enable Enable Disable Disable 按 Apply，再按 Hide 關閉 Timing Setup Pannel。 “ Timing > Timing Report ” Default 值，按 OK。 30. “ PostPlace > Post Placement Optimization ” Default 值 “ Timing > Timing Report ” 31. “ Cell > Save! ” “ Cell > Save As ” Cell Name mul_cts overwrite Enable Default 值 按 OK。 32. 在 Placement Optimization 時有些 gate 或 buffer 可能被加入或拿掉，所以必須重新再作一次 Power/Ground Connection。 “ PreRoute > Standard Cells ” Default 值，按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 40 33. “ Route Setup > Route Common Options ” Global Routing Clock Routing Track Assign Detail Routing Same Net Notch All other options Timing Driven balanced Timing Driven connect tie off, connect open nets check and fix Default value 按 OK。 34. “ Route > Route Net Group ” Net Name(s) From: Phase Search Repair Loop Dangling wires All other options All clock nets global, track assign, detail 5 Discard Optimize routing pattern Enable Default value “ Route > Global Route ” Default 值，按 OK。 “ Timing > Timing Report ” 35. 觀察 congestion 情況 “ Route > Estimate Global Route Congestion! ” “ Route > Display Congestion Map ” 按 Apply，如果沒問題按 Clear，再按 Cancel。 congestion 結果 ok，則不需作 Global Route Optimization。 36. “ Route > Auto Route ” Default 值，按 OK。 37. “ Timing > Timing Setup ” 選取 Model tab Operating Cond Delay Model Max, Min AWE Default 值，按 OK。 按 Apply。 “ Timing > Timing Report ” Default 值，按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 41 38. 若有 DRC violations，則需使用 Search & Repair 去修正。 “ Route > Search and Repair ” Search Repair Loop 20 All other options Default value 按 OK。 39. 作最後的 Optimize “ Route > Post Route Optimization ” Default 值，按 OK。 “ Timing > Timing Report ” 40. “ Cell > Save! ” “ Cell > Save As ” Cell Name mul_routing overwrite Enable Default 值，按 OK。 按 OK。 41. 加入 Antenna Rules (已修改完畢) antenna_rules.cmd define _libId (dbGetCurrentLibId) dbDefineAntennaRule _libId 2 2 0 0 dbAddAntennaLayerRule _libId 2 "met1" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met2" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met3" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met4" 400 '(0.359 0 0 999999999) dbAddAntennaLayerRule _libId 2 "met5" 400 '(0.359 0 0 999999999) 在 Message/Input Area 輸入 load “../tech/antenna_rules.cmd ” 加入 antenna rules。 “ Route Setup > HPO Signal Route Options ” 設定 antenna ratio 的計算模式 Timing-Driven Spacing Off Change-Collecting Antenna advanced 按 OK。 在 Message/Input Area 輸入 axReportAntennaRatio (geGetEditCell) 如果有出現 violation (紅色框框的地方)，必須用 Search & Repair 修正。 “ Route > Search and Repair ” Default 值，按 OK。 輸入 axReportAntennaRatio (geGetEditCell) 確認 violation 是否還存在。 Chip Implementation Center – Design Service Department – Digital Technology Section 42 42. 加入 Core Filler “ PostPlace > Add Core Fillers ” Master Cell Name(s) Without Metal Master Cell Name(s) With Metal respect hard placement blockage respect soft placement blockage between std cells only Connect to Power Net (optional) Connect to Ground Net (optional) All other options Enable Enable Enable VDD GND Default value FILL64, FILL32, FILL16, FILL8, FILL4, FILL2, FILL1 按 OK。 43. “ PreRoute > Standard Cells ” Default 值，按 OK。 44. 將單一個 via 置換成 2 個 via，作 contacts optimization 在 Message/Input Area 輸入 load “../scripts/optContacts.cmd” 45. “ Route > Search and Repair ” Default 值，按 OK。 46. 由於 Power Net 的寬度過大，違反 metal density rules。 “ PreRoute > Slot Wires ” Select Wires Net Name(s) CutWidth CutLength Width Length Side Space EndSpace Side Clearance End Clearance Stagger Treat Width as Treat Length as Specified VDD, GND 20 30 2 10 10 10 10 10 Enable Minimum Minimum Treat Spaces and Clearances as Maximum 按 OK。 47. “ Route Utility > Fill Notch/Gap ” Default 值，按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 43 48. “ Verify > DRC ” “ Verify > LVS ” Default 值，按 OK。 Default 值，按 OK。 49. 作 Calibre LVS 跟 Post Layout Simulation 時要在 layout 上加上 Text 才會正確。 在 Message/Input Area 輸入 load “../scripts/add_text.cmd” add_text.cmd (已編輯完畢) dbAllowToAddPGIOText #t dbAddIOText (geGetEditCell) "*" "*" 103 20 50. “ Cell > Save! ” “ Cell > Save As ” Cell Name mul_dfm overwrite Enable 按 OK。 51. Stream Out GDS II “ Tools > Data Prep ” “ Output > Stream Out ” 注意 Output Net 中一定要選取 As Text，否則 LVS 會有問題。 Stream File Name Library Name Layer File Child Extraction Depth Convert Cell Name Convert Reference Lib Child Cells Flatten Fill Pin/Net Options > Output Pins Pin/Net Options > Output Net pmult32.gds mul ../tech/stout.map 20 Specified Cell pmult32 Enable Devices & Device Arrays FILL As Text As Text 按 OK。 52. Verilog Out PS：若無法 dump verilog netlist，必須重新修復 net 和 instance 的連線(CHIP.CEL 要先關閉後才 能執行此動作)。 “ Cell > Repair Hierarchy Information ” Flattened Cell Name(.CEL) pmult32.CEL Repair net connections and instances Enable 按 OK。 Chip Implementation Center – Design Service Department – Digital Technology Section 44 “ Cell > Hierarchical Verilog Out ” ----for caliber block box LVS Flattened Cell Name (.EXP .CEL) Enter File Name No power/ground ports No power/ground nets Output bus as individual bits No empty Cell Module Definitions No Corner Pad Instances No Pad Filler Cell Instances No Core Filler Cell Instances No Unconnected Cell Instances No Unconnected Ports Strip BackSlash Before Hierarchy Separator No Diode Ports Output Wire Declaration Generate macro definitions pmult32.CEL pmult32_lvs.vg Enable Disable Disable Enable Disable Disable Disable Disable Disable Enable Disable Enable Output 1’b1 for Power(VDD, vdd, …) and 1’b0 for Ground(VSS, gnd, …) Disable Disable 按 OK。 53. Change directory to Lab2/verify/drc unix% cd ~/astro/Lab2/verify/drc 54. 複製 DRC 相關檔案至 drc 的資料夾 Calibre-drc-cur 180nm_layers.cal metal_slot_0.18_1P6M-MMC-Calibre-drc-2.2-p1 pmult32.gds unix% cp ~/astro/Lab2/run/pmult32.gds . 55. 修改 Calibre-drc-cur 檔 LAYOUT PATH "./pmult32.gds" LAYOUT PRIMARY "pmult32" 56. 執行 Calibre DRC unix% calibre –drc –hier Calibre-drc-cur 觀察 drc.sum 檔看看是否有 drc error 57. Change directory to Lab2/verify/lvs unix% cd ~/astro/Lab2/verify/lvs Design Kit Design Kit Design Kit Astro Chip Implementation Center – Design Service Department – Digital Technology Section 45 58. 複製 LVS 相關檔案到 lvs 資料夾 pmult32.gds pmult32_lvs.vg umc18_lvs.spi umc18_lvs.v Calibre-lvs-cur unix% cp ~/astro/Lab2/run/pmult32.gds . unix% cp ~/astro/Lab2/run/pmult32_lvs.vg . 59. 將 pmult32_lvs.vg 轉換成 spice 格式 unix% v2lvs –v pmult32_lvs.vg –l umc18_lvs.v –o pmult32.spi –s umc18_lvs.spi 60. 修改 Calibre-lvs-cur SOURCE PRIMARY "pmult32" SOURCE PATH "./pmult32.spi" LAYOUT PRIMARY "pmult32" LAYOUT PATH "./pmult32.gds" 61. 執行 Calibre LVS unix% caliber –lvs –spice pmult32.spi –hier –auto Calibre-lvs-cur 觀察 lvs.rep 找到 OVERALL COMPARISON RESULT 部份是否 match Astro Astro Design Kit Design Kit Design Kit Chip Implementation Center – Design Service Department – Digital Technology Section 46