Accumulator Based 3-Weight Pattern Generation

1. NANO SCIENTIFIC RESEARCH CENTRE PVT LTD., WWW.NSRCNANO.COM#404, SIRI ESTATES, ABOVE VASAN EYE CARE BUILDING, OPPOSITE LANE TOR.S.BROTHERS,AMEERPET,HYDERABAD, ANDHRA PRADESH, INDIAVLSI 2012 IEEE1. Design of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic Circuits2. DESIGN OF LOW POWER HIGH SPEED VLSI ADDER SUBSYSTEM3. HICPA: A Hybrid Low Power Adder for High-Performance Processors4. Low-Power and Area-Efficient Carry Select Adder5. Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics6. Design and Implementation of a High Performance Multiplier using HDL7. Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC8. DESIGN Of LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER9. Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application10. FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers11. High Speed and Area Efficient Vedic Multiplier12. High speed Modified Booth Encoder multiplier for signed and unsigned numbers13. High Speed Signed Multiplier for Digital Signal Processing Applications14. Accumulator Based 3-Weight Pattern Generation15. Design of Low Power TPG Using LP-LFSR16. Viterbi-Based Efficient Test Data Compression17. A Feature-Based Robust Digital Image Watermarking Scheme18. Digital Image Watermarking Based on Super Resolution Image Reconstruction19. Hardware Implementation of a Digital Watermarking System for Video Authentication20. Watermarking Mobile Phone Colour Images with Reed Solomon Error Correction Code21. Watermarking Scheme for Copyright Protection of 3d Animated Model22. A Real-time Face Detection And Recognition System23. VHDL Implementation of UART with Status Register24. FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization25. An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform26. VHDL Design for Image Segmentation using Gabor filter for Disease Detection. VLSI 2011 IEEE1. An Efficient Implementation of Floating Point Multiplier2. High Speed and Low Space Complexity FPGA Based ECC Processor3. A blind digital watermarking algorithm based on wavelet transform 2. NANO SCIENTIFIC RESEARCH CENTRE PVT LTD., WWW.NSRCNANO.COM#404, SIRI ESTATES, ABOVE VASAN EYE CARE BUILDING, OPPOSITE LANE TOR.S.BROTHERS,AMEERPET,HYDERABAD, ANDHRA PRADESH, INDIA4. A Distributed Canny Edge Detector And Its Implementation on FPGA5. Design and Simulation of UART Serial Communication Module Based on VHDL6. Design and VLSI implementation of high-performance face-detection engine for mobile applications7. Design and Implementation of Area-optimized AES based on FPGA8. Design of Low Power And High Speed Configurable Booth Multiplier9. Face detection and recognition method based on skin color and depth information10. High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics11. A New Reversible Design of BCD Adder12. Digital Image Authentication from JPEG Headers13. Design and Implementation of Low Power Digital FIR Filter based on low powermultipliers and adders on xilinx FPGA14. Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA15. A Very Fast and Low Power Carry Select Adder Circuit16. A multichannel water making scheme based on DCT-DWT17. An Implementation of a 2D FIR Filter Using the Signed-Digit Number System18. Design and Characterization of Parallel Prefix Adders using FPGAs19. FPGA based FFT Algorithm Implementation in WiMAX Communications System20. FPGA Design of AES Core Architecture for Portable Hard Disk21. FPGA Implementation of RS232 to Universal serial bus converter22. Image Encryption Based On AES Key Expansion23. Feature Extraction of Digital Aerial Images by FPGA based implementation of edgedetection algorithms24. An Efficient Architecture Design for VGA Monitor Controller25. Curve Fitting Algorithm FPGA implementation26. FPGA Implementation of AES Algorithm27. Design of Low Power Column Bypass Multiplier using FPGA28. Design of Serial Communication Interface Based on FPGA29. Design and Implementation of an FPGA-based Real-Time Face Recognition System30. VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders31. Low Cost Binary128 Floating-Point FMA Unit Design with SIMD Support32. Design Enhancement Of combinational Neural Networks using HDL Based FPGAframework for Pattern Recognition33. Efficient VLSI Architecture for Discrete Wavelet Transform