Introduction to Flip Chip

Johnson Ch19 page 1Chapter 19: Flip Chip Assembly and Underfilling R. Wayne Johnson, Auburn University 1.0 INTRODUCTION 1.1 Process Overview 1.1.1 Capillary flow 1.1.2 Fluxing underfills 1.1.3 Wafer-applied underfills 2.0 SUBSTRATE DESIGN 2.1 LAYOUT 2.2 COPPER AND SOLDERMASK REQUIREMENTS 3.0 ASSEMBLY WITH CAPILLARY FLOW UNDERFILL 3.1 Die presentation 3.2 Flux and flux application 3.3 Pick and Place 3.4 Reflow 3.5 Substrate dehydration 3.6 Underfill dispense and cure 3.7 Rework 4.0 ASSEMBLY WITH FLUXING UNDERFILLS 4.1 Substrate dehydration 4.2 Application of fluxing underfill 4.3 Die placement 4.4 Reflow 4.5 Rework 5.0 WAFER APPLIED UNDERFILLS 5.1 Issues in wafer applied underfills 5.1.1 Application to wafer 5.1.2 Dicing and handling 5.1.3 Shelf-life 5.1.4 Placement 5.1.5 Reflow 5.1.6 Rework 6.0 RELIABILITY 6.1 Component Level Testing 6.1.1 JEDEC Moisture Level 6.1.2 Preconditioning 6.2 Environmental and Board Level Testing 6.2.1 Thermal Cycling and Thermal Shock 6.2.2 Power Cycling Johnson Ch19 page 2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 7.0 SUMMARY 8.0 REFERENCES Flex Testing Temperature/Humidity/Bias Aging Autoclave and HAST High Temperature Storage and Electromigration Alpha Particles Johnson Ch19 page 3 1.0 INTRODUCTION IBM first introduced flip chip technology in 1964 in the solid logic technology (SLT) hybrid modules in the System 360 mainframe [1]. The technology was developed by IBM to replace wire bonding as a means of interconnecting semiconductor die to thick film metallization on alumina. The die were three terminal transistors with Au/Ni plated Cu balls embedded in a Pb/Sn solder bump on the three I/O pads of the transistor. A Cr-Cu-Au interface layer was deposited between the Al transistor bond pads and the solder bump. The device was assembled to the hybrid substrate by inverting (flipping) the die and reflow soldering the copper balls to corresponding metal pads on the substrate. The copper balls maintained a constant standoff between the die and the substrate after reflow. As the I/O count of the die increased, the copper spheres were replaced with high lead, tin-lead alloy solder bumps [2]. The solder balls collapse somewhat during the reflow soldering process, balancing the weight of the chip and the surface tension forces of the molten solder. This phenomenon gave rise to the IBM terminology controlled collapse chip connection (C4). The flow of the solder (collapse of the chip-to-substrate spacing) was controlled during reflow by controlling the solder volume and the wettable metal exposed on the die and the substrate. The advantages of the flip chip assembly process for high volume manufacturing were recognized by the automotive industry. Flip chip-on-ceramic was adopted by the automotive industry in the late 1970’s as a high volume, surface mount assembly technology for applications such as ignition modules. The die were typically small (<3mm) with a low I/O count (<20). The solder bumps were primarily high lead alloys, although some eutectic bumps were used. The large pitch of the bumps allowed solder paste to be printed on the thick film metal pads. The flip chip die was then placed and reflowed along with other surface mount components. With the high lead bumps, a high lead solder paste was used. The thick film ceramic substrate allowed reflow at temperatures in excess of 325oC. The flip chip-on-ceramic assembly process paralleled the development of surface mount technology-on-laminate with plastic leaded packages such as SOT’s, PLCC’s and QFP’s. Flip chip technology offers other advantages as semiconductor device speed, size and I/O increases. For high speed applications, the small solder balls add minimal parasitics (resistance, capacitance and inductance) and propagation delays to the electrical signal path. In addition, the elimination of the die package permits the die to be placed close together on the substrate, further reducing interconnection parasitics and propagation delay. Elimination of the die package and close spacing of die is also an advantage in portable electronics, where size and weight is critical. Finally, as the die I/O continues to increase, perimeter electrical interconnection by wire bonding becomes limited. In flip chip technology, I/O can be arrayed over the entire area of the die dramatically increasing the number of I/O. While there is a coefficient of thermal expansion (CTE) mismatch between alumina (6.5ppm/oC) and silicon (3ppm/oC), millions of reliable, under-the-hood modules were built using small die on ceramic without the need for underfill. Millions of flip chip solder joints were also used in mainframe computers without failure. Increasing either the size of the die or increasing the CTE of the substrate (switching from ceramic to laminate @ ~16ppm/oC) increases the strain on the Johnson Ch19 page 4 solder joints during thermal cycling or thermal shock (Figure 1). To improve reliability, underfill was added to the flip chip assembly process [3-5]. Underfill is a polymer material (typically a filled epoxy) that fills the space between the die and the substrate. The underfill bonds the die and the substrate together forming a tri-layer structure. The net effect is to reduce the strain on the individual solder joints by creating a structure that warps as the temperature changes (Figure 2). Figure 1. Illustration of Stress on Solder Joints Due to CTE mismatch when Assembly is Cooled from Solder Solidification Temperature to Room Temperature. The substrate contracts more than the silicon die during cool down. Figure 2. Warpage when Underfilled Structure is Cooled from Underfill Cure Temperature to Room Temperature. The objective of this chapter is to discuss the materials and processes for flip chip assembly with underfill. 1.1 PROCESS OVERVIEW The application and cure of the underfill material are the primary assembly steps that impact the flip chip assembly process flow. The underfill can be applied after the flip chip is placed and reflowed (capillary flow) or prior to die placement. Fluxing underfills are applied to the substrate just prior to die placement, while wafer applied underfills are coated onto the wafer prior to singulating the wafer into individual die. These three options are introduced below and will be detailed in later sections of this chapter. 1.1.1 Capillary Flow Underfills Liquid capillary flow underfill materials are dispensed along the edge of the die after the die has been reflow soldered to the substrate. Capillary action pulls the liquid under the die as illustrated Johnson Ch19 page 5 in Figure 3. After the liquid underfills the die, a second dispense may be required to form a fillet around the edge of the die. Self-filleting is observed with some materials, eliminating this step. Following the dispense step the underfill must be cured. Cure times and temperatures vary from 5 to 90 minutes at 150 to 165oC depending on the underfill chemistry. Capillary flow underfills are commercially available from a number of suppliers and are most commonly used today. Die Substrate Solder Ball Underfill Fillet Residue Figure 3. Illustration of Capillary Underfill Process. 1.1.2 Fluxing Underfills Fluxing underfills include the fluxing chemistry for the soldering step in the underfill. The liquid is applied to the substrate, typically by dispensing. The die is then placed and reflowed. The underfill may cure during the reflow cycle or a post reflow cure may be required depending on the material. The process is illustrated in Figure 4. Fluxing underfills are commercially available from a number of suppliers. Placement head Fluxing Underfill PCB Figure 4. Illustration of Assembly with Fluxing Underfill. Within this parameter space design options exist and are discussed in the following section. However. Wafer Applied Underfill Assembly Process. 2. During the reflow cycle. In this design. the design process is simplified through industry standardized I/O configurations and recommended substrate pad designs. The process is illustrated in Figure 5. wafer applied underfills are coated onto all die on a wafer at one time. flip chip I/O configurations are custom to each die. 2. The PWB technology must provide line and space pitch equal to the pitch of the solder bumps as illustrated in Figure 6.1 Single Row Perimeter Flip chip die with a single row of perimeter solder bumps are the simplest to route. the underfill must be a dry (non-tacky) film for handling. Bumped Wafer Underfill Coated Wafer Assembly Figure 5. the copper trace width and the solder mask opening define the solderable copper area exposed to the solder ball. decreasing this gap height increases .3 Wafer Applied Underfills Rather than applying the underfill one die at a time during the assembly operation. The underfill may cure during the reflow cycle or may require a post-reflow cure step.Johnson Ch19 page 6 1.0 Substrate Design With packaged surface mount components. Increasing the solderable area decreases the gap height between the die face and the solder mask.1. 2. After coating. two row perimeter. In turn. The design will depend on the I/O pitch. Each presents its own design and substrate fabrication challenges. the underfill liquefies providing fluxing action. the arrangement of the I/O and the substrate technology. single row perimeter. therefore substrate pad designs have not been standardized. the number of I/O.1 Layout While flip chip bump patterns can be irregular. Wafer applied underfills are in the developmental stage and not commercially available. and full area array are most common.1. Variations in copper etching (trace width) and solder mask developing (trench width) from board-to-board will lead to variations in gap height. the solder balls on the two sides can be aligned. this will change the volume of material required to underfill the die. The placement in Figure 7a assumes copper defined fiducials are used. the underfill fillet must provide the reservoir to insure the die is completely underfilled. the solder balls do not line up with the pads. A second issue in PWB fabrication is the solder mask registration. “Trench” Design for Single Row Perimeter Flip Chip Die. the solder ball will rest on the edges of the solder mask and not make contact with the copper trace. adversely affecting the underfill process. If the solder mask opening (trench) becomes too narrow. Solder Mask “Trench” Copper Traces Solder Balls Figure 6. With gap variations there will be a corresponding variation in the amount of fillet formed.Johnson Ch19 page 7 the time required for capillary underfills to flow. At the top and bottom of the die the solderable pads are defined by the copper trace in the x-direction and the . the placement result is shown in Figure 7b. As illustrated in Figure 7. Therefore. If the gap becomes sufficiently small. if the solder mask is shifted to the right. If solder mask defined fiducials are used. In production. capillary underfill may not flow into the gap. In both cases. An open solder joint after reflow can be the result. the underfill dispense volume is not changed from board-to-board. decreasing the solderable area increases the risk of shorting between bumps. Consistent PWB fabrication is important. but the solder balls on the top and bottom are misaligned. In turn. PWB manufacturing variations must be considered. For fine pitched solder bumps. . With fine pitch solder bumps. no placement shift can compensate for solder mask misregistration. The surface tension of the molten solder during the reflow process will tend to center the chip creating approximately even solder joint distortion on all sides as shown in Figure 8. (b) Placement based on Solder Mask Defined Fiducials. On the other two sides of the die. (a) Placement based on Copper Defined Fiducials. the solderable pads are defined by the solder mask in the x-direction and the copper trace in the y-direction. The impact of this distortion on reliability has not been documented. Thus.Johnson Ch19 page 8 solder mask in the y-direction. Y X (a) (b) Figure 7. solder mask-to-copper misregistration increases the likelihood of solder bridging. Solder Mask Misregistration to the Right. Over etching of the copper is more critical in this design since over etching not only reduces the trace width. This design approach decreases the potential for bridging of fine pitch flip chip bumps. Solder Joint Distortion due to Solder Mask Misregistration. the die placement is based on copper fiducials. If the solder mask is misregistered as shown in Figure 9b. An alternate design can be used to address misregistration issues (Figure 9). In this design. the gap height will be less on the left side (more solderable copper area). . Over etching combined with a solder mask shift to the left can result in very small pads on the right-hand side.Johnson Ch19 page 9 Figure 8. Other designs for single row perimeter die are possible. but these two are the most common. but also the trace length. The maximum solder mask misregistration must be considered in the determination of the length of the exposed copper fingers. The die-to-PWB gap height is increased in this design by eliminating the solder mask under the die. This is necessary to prevent the underfill from flowing out through the hole during the underfill process. Figure 11 is a two row perimeter design with characteristics similar to Figure 9. If conventional PWB technology with plated through holes for z-axis interconnections is to be used. Plated through holes are typically tented with dry film solder mask. solder mask resolution and solder mask-to-copper registration are again critical. 2. LPI solder mask can not tent plated through holes. the plated through holes under the die must be tented or plugged.2 Two Row Perimeter The first determining factor for a two row perimeter design is the flip chip I/O pitch relative to the pitch of the PWB. The . The LPI solder mask can then coat over the plugged hole.Johnson Ch19 page 10 (a) (b) Figure 9. Alternate Design for Single Row Perimeter Flip Chip. the second row of bumps must be routed toward the center of the die and down through plated through holes or vias. Thus. The two trench approach would impede underfill flow. flip chip PWBs are almost exclusively fabricated with liquid photoimagable (LPI) solder mask to achieve thinner coatings and better resolution. Depending on pitch. Isolated solder mask openings (as shown) or two trenches can be used depending on the I/O pitch and the solder mask resolution. However.1. The solder mask misregistration should be less than 50% of the line-to-line spacing on the PWB. Consistent control of copper etching. (b) Solder mask is misregistered to the left. this may be challenging. If the PWB technology will not support one trace between solder bump pads. After plating the holes are filled (plugged) with epoxy and cured. Can a PWB trace be routed between adjacent solder ball pads (Figure 10)? The design in Figure 10 is similar to Figure 6. plugged holes are typically used for flip chip PWBs. (a) Perfect copper-to-solder mask registration. Figure 11. Illustration of Two Row Perimeter Design. Alternate Two Row Perimeter Design. .Johnson Ch19 page 11 Figure 10. one of the first HDI approaches. The SLC technology used a liquid. High density interconnect (HDI) substrates are required. The formation of vias . The HDI structure is illustrated in Figure 13.2 Area Array With smaller die or full area arrays. 6. The substrates are fabricated by build-up of sequential dielectric and copper layers processed on a laminate core. photoimageable dielectric layer with additive copper to fabricate the HDI layers. Two Row Perimeter Design with Plugged Plated Through Holes. Copper etching and solder mask-to-copper registration are critical to this design. The starting dielectric material may be either liquid (non-reinforced) or a dry film (reinforced or non-reinforced). the pad diameters for the plated through hole are too large to allow routing. A number of HDI approaches have since been developed. This figure is of the IBM surface laminar circuitry (SLC) technology.1. Tented or Plugged Vias Figure 12.Johnson Ch19 page 12 design is illustrated in Figure 12. Plasma Laser 1. .Johnson Ch19 page 13 is by photoimaging. laser or plasma as shown in Table 1. The vias are through only one layer of dielectric and are less than 125µm in diameter (Figure 14). HDI Dielectric Types and Via Processing. Laser Photoimage. Table 1. Example of HDI Via. S u rfa c e La m in a r C irc u it s ( S LC ) PTH p h o t o -s e n s i t i v e e p o x y p h o t o fo rm e d via s gla s s e p o x y s u b s t ra t e Figure 13.5 . In some approaches. Example of High Density Interconnect (HDI) Substrate. Laser. the vias are filled with a conductor filled epoxy.2 mil 2 -3 mil dia. Dielectric Type Non-reinforced Reinforced Form Liquid Dry film Dry film Via Processing Photoimage. Additive processing is commonly used for copper deposition/patterning. This is an advantage in “pad-in-via” designs to be discussed in a later paragraph. Figure 14. the absence of a solder mask and potential for misregistration is a benefit for this design. In addition to density. If the via pad can fit in the interstitial space between solder bump pads. Dog Bone Design for Area Array Flip Chip Using an HDI Substrate. . The vias may be either filled or plated solid to avoid entrapped voids during solder reflow. The impact of these voids on reliability has not been determined. which decreases the stand-off height. The second concern is the increased solder wettable area. area array flip chip die can be routed. The ultimate in density is achieved with a “via-in-pad” design (Figure 16).Johnson Ch19 page 14 With the smaller pads and vias achievable with HDI technology. The pitch of the vias must equal that of the solder bumps on the die. One concern with ‘via-in-pad’ design is the potential for voids trapped in the solder joint (Figure 17). Figure 15. a “dog bone” design similar to BGA and CSP patterns can be used (Figure 15). Pad-in-Via Design with HDI Substrate. (Courtesy of Jabil Circuits) .Johnson Ch19 page 15 Figure 16. Example of Pad-in-Via Design with and without Entrapped Void. Figure 17. Other finish alternatives include silver and tin. The thickness of the surface copper layer is the combination of starting foil thickness and the plating thickness required for reliable plated through holes in conventional PWB fabrication. fine pitch flip chip may require a tolerance of less than 2mil (50 µm). This is a challenge for the industry. Each design is unique and compromises must be considered. which is typical of most flip . In most HDI structures. solder mask registration is critical. the gold volume within the solder joint should be less than 3% and preferably less than 1% to avoid embrittlement of the joint and Au-Sn intermetallic formation. Foil thicknesses less than ¼ oz (8. In many designs. the solderable area is partially defined by the solder mask opening.0 Assembly with Capillary Flow Underfill The process flow for flip chip assembly with capillary flow underfill is illustrated in Figure 18. For long term reliability. While the industry standard registration tolerance is 3 mil (75µm). If the solder mask opening is too small. The number of reflow cycles and high temperature process steps and the processing sequence should be reviewed if OSPs are to be used. Solder mask resolution is also important. Electroless nickel/immersion gold is the most commonly used surface finish for flip chip assembly. It is a challenge to apply thin solder mask without having skips or exposed copper particularly at the edge of traces. The solder mask thickness impacts the gap height. solder bridging can result with fine pitch assemblies.3µm) are available. This process assumes the flux residue is not cleaned after reflow. Thinner copper reduces the probability of voids in the underfill at the base of the copper trace. particularly if processing 18” x 24” panels for manufacturing efficiency. As the pitch of the flip chip device decreases. 3. no beginning foil is used and the surface copper thickness is determined by the plating thickness. Typical plated through-hole copper thicknesses range from ½ oz (16. As discussed in the previous section.Johnson Ch19 page 16 2. Some OSP coatings are formulated to withstand more high temperature exposures. The solder mask impacts the assembly process and yield.2 Copper and Solder Mask Requirements Voids (air pockets) can be trapped during underfill flow at steep topology features such as the edge of a thick copper trace. The thickness of the plated through-hole copper required is a function of the total board thickness and the reliability (thermal cycle) requirements. the solder mask opening may be too small for the solder ball to touch the copper pad. but more expensive and difficult to process. Increasing the solderable area decreases the gap height making the underfill process more difficult. resulting in an open connection. Proper board design.6µm) for consumer/portable electronics applications to 1 oz (33. The effectiveness of OSPs decreases with multiple high temperature exposures. thinner copper is also required to fabricate finer lines and spaces. Organic solderability preservative (OSP) coatings are also commonly used for flip chip boards. As the solder ball volume decreases the maximum gold thickness decreases. In the extreme case. materials selection and fabrication are important to flip chip assembly yield and reliability. The solder mask thickness over the copper traces should be less than 12µm.2µm) for automotive applications. In both cases the die are inverted. For high volume assembly. Each of the process steps and the associated materials will be discussed in the following sections. but are limited in the number of die they contain.Johnson Ch19 page 17 chip assemblies. intermediate handing steps are eliminated. By placing die directly from the wafer. This is an issue both for pick and place from wafers and for placing of die into waffle packs or tape from the wafer. Motorola has shown ejector pin damage of the die backside can lead to die fracture during assembly or in the field [6]. This adds an extra step to the pick and place operation. as a single reel will hold hundreds of die. in waffle packs or in tape and reel. The individual die cavities in the waffle pack or tape should be only slightly larger than the die to avoid rotation and translation of the die in the cavity. Illustration of Flip Chip Assembly with Capillary Flow Underfill. Since wafers are sawn bump side up. solder balls down for direct pick and place. Care must be taken that ejector pins used to assist in the removal of die from the expanded tape do not cause microcracks or flaws in the backside of the die. 3. Waffle packs are commonly used for flip chip die. Pick Die Reflow Flux Dispense Underfill Place Die Cure Underfill Figure 18.2 Flux and flux application . tape and reel is preferred. the die must be picked from the bump side and inverted for placement. 3.1 Die presentation Die can be presented for pick and place either as sawn wafers. The dipping operation is performed on the pick & place system and adds to the flip chip placement cycle time. The cost analysis of print versus dip is product and assembly line dependent. Since the flux is exposed to the atmosphere as a thin layer. Illustration of Flux Dipping. increases solder wetting and self-centering of die placed off center. Stencil or screen printing has also been used for flux application [7]. Flux Application Options.Johnson Ch19 page 18 In standard SMT assembly. increasing throughput at pick & place. This in turn. Flux printing can apply flux to multiple sites on a board in one pass and eliminates the flux dip step from the pick & place operation. Flux application is required prior to placement of the flip chip. Flux. which may interfere with underfill flow and decrease reliability if a no-clean process is used. not solder paste. Increasing these variables increases the amount of flux transferred to the solder balls. the evaporation rate for volatile components must be extremely low at room temperature. High throughput for boards/panels with No-clean or solvent clean many flip chip die Low viscosity. the flux is printed first. viscosity. However. Flux Comment Med. dip force and hold time. Fluxing options are listed in Table 2. increasing the volume of flux increases the amount of residue. viscosity. A step stencil (Figure 20) Option Dip Print Spray or Jetting Flood Dispense Doctor blade Table 2. . If both flip chip and SMT components are to be assembled to the board. Flow of flux substrate topology No (low) residue dependent Dip flip chip balls into flux Figure 19. The viscosity and surface tension of the flux also impact the flux transfer. The variables to control are flux depth. solder paste is stencil printed and the components are placed into the paste. is then used to print the solder paste. is generally used in the assembly of flip chip die. Flux applied over entire chip site No (low) residue including non-soldering areas Low viscosity. Dip fluxing is illustrated in Figure 19. Increases placement cycle time No-clean or solvent clean Med. Otherwise the print characteristics will change during the production run. The design of the stencil or screen and printing characteristics determines the flux volume. Example of Flux and Solder Paste Printing for Mixed SMT Assembly. Some pick & place systems are equipped with flood dispense capability. Since some wetting did occur. The coverage for flood dispense is dependent on substrate design/topology and the wetting characteristics of the substrate surfaces. Spray. the copper pad is small and pad adhesion to the laminate is the limiting factor in shear strength. These are low viscosity. flux printing characteristics. Spray dispense and jetting are more uniform and less topology dependent. the failure point for die shear of flip chip-on-laminate should either be at the die-to-solder ball interface (Figure 22) or the copper pad-to-laminate interface for small pad (fine pitch) designs. Stencil Flux Solder Board Figure 20. and the failure was at the solder ball-to-substrate pad interface. Separate fluid dispense systems can be used for flood. Thus. low solids content fluxes that are applied over the entire area of the chip site. the wetting at some pad sites was minimal. Slumping of the flux can cause solder bridging of fine pitch flip chips. electrical continuity was measured after assembly. . the evaporation rate for volatile components must be extremely low at room temperature.Johnson Ch19 page 19 Stencil/screen design. Similar to dip fluxing. electrical testing alone is not sufficient for process development. flux slumping and flux life on the stencil are important processing considerations when developing a flux printing process. The die shear strength and the failure mode can also be used to evaluate wetting. The wetting characteristics of the flux can be evaluated by cross-sectioning solder joints and examining the solder-to-pad interface (Figure 21). jetting and flood dispense are used with no (low) residue fluxes. In Figure 22. With fine-pitch flip chip die. jet and spray dispense. With good solder wetting. Mechanical shock and vibration in the conveyor systems as well as airflow in the reflow oven can cause chip movement. .Johnson Ch19 page 20 Figure 21. the flux must provide sufficient tack to hold the flip chip die in place prior to melting of the solder in the reflow process. the Solder Ball Remains on the PWB Pad. Example of Poor Solder Wetting at Two Sites. Cross-section Showing Excellent Solder Wetting of Copper Pad. The Failure is at the Die-to-Solder Ball Inferface. With all fluxes and application methods. Poor Wetting Figure 22. The Assembled Flip Chip Die was Sheared from the PWB. With Good Solder Wetting. TGA Plot of a No-clean Flux. These materials leave less than 2% by weight residue when tested using the same TGA temperature profile used in Figure 23. The surface tension of water is too high for cleaning in the small gap under the flip chip. Chemical interaction between the underfill and the flux residue during underfill curing can also degrade adhesion and reliability.Johnson Ch19 page 21 No-clean fluxes are most often used in flip chip assembly since cleaning in the small flip chip gap is difficult. The chemistry of these fluxes incorporates epoxy groups. solvent cleaning is typically used. Thus the fluxing activity and shelf-life must be balanced. After the thermal cycle. Figure 23. Centrifuge based cleaning systems have been . No (low) residue fluxes are being evaluated to minimize these issues. Fluxes and underfills must be evaluated as a materials system. Figure 23 is a TGA plot of a typical no-clean flux used for flip chip assembly [8]. Another no-clean alternative is epoxy flux. The challenge in the formulation of epoxy fluxes is the acids common to fluxes react with the epoxy groups to cross-link the material. The TGA thermal profile approximates a reflow cycle. flux residue can impede the flow of underfill material. the flux ‘residue’ is an adherent epoxy. After the reflow cycle is completed. No-clean fluxes leave residue after the reflow process. If cleaning is required. approximately 35% by weight of the flux remains as residue. As previously mentioned. Transforms are used to further increase the contrast and image recognition.3 Pick and Place Pick and place for flip chip die is similar to other fine pitch SMT devices with added emphasis on the vision system and placement accuracy. Because of the curvature of the solder balls and the resulting angles of reflection. a process control method must be developed since inspection is not a production option.Johnson Ch19 page 22 shown to be effective at cleaning in small gaps. Example of Vision System Lighting Options for Flip Chip Die. angled lighting can provide the required contrast. Vertical lighting (Figure 24) typically leads to reflection from both the solder balls and the die surface and often can not be used. Standard wafer sawing tolerances do not allow flip chip placement based on visioning of the die outline. If dip fluxing is used. Exceptions are very course pitch flip chip die or very tight sawing specifications. (Courtesy of Siemens Energy and Automation) The required placement accuracy (maximum misalignmnet) is often specified at 20% as defined in Figure 25. For under-the-hood automotive applications Delphi-Delco has described the evaluation of cleaning processes and materials for flip chip-onlaminate using quartz die and dyed fluxes [9]. 1 •High Resolution Vision Systems 2 3 CCD Camera 4 Filter Lens Camera Four separate light sources: 1) Vertical light source 2) Plane (ring lights) 3) Middle (quadratic) 4) Super plane (ring light) Figure 24. Sufficient contrast between the solder balls and the die surface is also required. The CCD camera in the vision system must have sufficient resolution to recognize individual solder balls. Lewis has shown that high assembly yields can be achieved with higher levels of . If flux cleaning is used. 3. fluxing before or after visioning must be considered as well as the impact of the flux on the image. increasing the volume of flux increases self-centering and improves assembly yield. (Courtesy of Siemens Energy and Automation) 3. Definition of Percent Misalignment. X-ray is often used to characterize the solder joints after reflow. X-ray (Figure 27) can also detect voids in the solder joint. air or nitrogen reflow can be used. the force of the gas flow on the die must not be sufficient to move the die.Johnson Ch19 page 23 misplacement due to the self-centering nature of molten solder [10]. Void formation during reflow can be reduced or eliminated by flux selection and reflow profile modifications to minimize vapor generation once the solder ball liquefies. 0% 50% 20% Figure 25. X-ray can be used to measure the initial placement accuracy (to characterize the placement system capability) and also to measure the alignment after reflow (to measure the limits of self-centering). Bridging between adjacent solder balls is easily detected by x-ray. As previously noted. The impact of voids on flip chip reliability has not been quantified. the number of solder balls. The voids may have existed in the solder balls as originally formed on the die or result from trapped flux vapors during the reflow profile. In forced convection reflow ovens. This will be a function of the die size. As previously mentioned. the tackiness of the flux and the change in tackiness during the reflow until the solder melts and wets the PWB metallization.4 Reflow The reflow temperature profile for flip chip assembly should follow the manufacturer’s recommended profile for the flux used and is similar to standard SMT reflow profiles. vibration in conveyors or reflow ovens can also cause die movement and low assembly yields. Voids in solder balls are also common to ball grid . Figure 26 is a typical x-ray image after reflow. Depending on the flux and board surface finish. X-Ray Image of a Flip Chip Assembly. This is aggravated by solder mask misalignment as has been previously discussed. An industry accepted limit of <20% void content is generally accepted for BGAs. Figure 26. Solder bridging can result from die misplacement or movement after placement prior to reflow.Johnson Ch19 page 24 array (BGA) and chip scale packages. X-ray can also be used to measure self-alignment during the soldering process and to detect shorts between solder balls. Insufficient wettable substrate pad area can also lead to bridging of fine pitch solder balls. (Courtesy of FeinFocus) . In this test. all relative to the initial ‘dry’ .Johnson Ch19 page 25 Figure 26.5 Dehydration If the printed wiring board has absorbed moisture from the environment. Moisture from the atmosphere is absorbed by both the PWB laminate and the solder mask. the PWBs (bare and with several different solder masks) were exposed to 85%RH at 85oC for 168 hours to fully saturate the boards. The weight gain was measured after humidity exposure. This reflow cycle is effective in removing a significant amount of moisture absorbed by the PWB (Figure 28). this moisture may be liberated and create moisture bubbles (voids) in the underfill during the underfill curing process. after one pass through the reflow cycle and after one pass through the reflow cycle followed by humidity exposure at 60%RH at 30oC for 6 hours. Example of Voids in Flip Chip Solder Joints As Detected by X-Ray. In an in-line SMT process. (Courtesy of FeinFocus) 3. the underfill dispense follows the reflow cycle. Heating the syringe to speed thawing is not recommended.2 0. prior to use. Thawing should be accomplished by placing the syringe at room temperature.6 0.Johnson Ch19 page 26 0. The reflow cycle drives-off the ‘easy-to-remove’ moisture. individual material combinations should be tested. weight of the test coupon.7 0. a dehydration bake may not be necessary with in-line flip chip assembly. . 3. Depending on the underfill and the solder mask selected. Percent Weight Gain After 168 Hours Exposure at 85%RH at 85oC. The underfill is loaded in to the syringe under vacuum and may be centrifuged to ensure there are no bubbles in the syringe.5 0. The re-exposure to 60%RH at 30oC for 6 hours after reflow was to simulate a delay between reflow and the underfill dispense related to possibly board testing prior to underfill or some production delay. The underfill must be completely thawed.1 C 3 FR 4 C 2 C 1 B 5 B 4 B 3 B 2 A 5 B 1 A 4 A 3 A 2 A 1 0 Solder Mask Figure 28.6 Underfill Dispense and Cure The manufacturer provides the underfill in syringes of various sizes.3 0. As can be seen.4 0. little moisture is absorbed during this 6 hour period. However. The underfill is shipped frozen and should be stored at –40oC until ready to use. After One Reflow Cycle and After 6 Hours Exposure at 60%RH at 30oC.8 168 hrs @ 85%RH/85C After Reflow 6 hrs @ 60%RH/30C Percent Weight Gain 0. The lower temperature underfill cure cycle is not likely to cause subsequent moisture release. Line. Volumetric control is achieved using a rotary valve or positive displacement dispense valve. the same parameters would be used and the corresponding volume or weight would be measured. will vary somewhat from board to board. If the amount of material dispensed was less than during the baseline case. the die size. the underfill time is longer and partial underfill curing can be a concern at the higher PWB temperatures. If the dispensed . The dispense pattern is a function of the underfill. PWB temperatures range from 60oC to 100oC depending on the underfill material and the die size. For large die. The needle travel speed. the valve rpms for a rotary valve system. The dispense pattern is critical to achieving complete underfilling without entrapping voids under the die. The fillet provides the reservoir to accommodate this variation. This material may get on top of the die or flow away from the die before it has an opportunity to flow under the die. Capillary forces then pull the material under the die. At a later calibration. the rpms would be increased to compensate. The volume of underfill dispensed is critical to ensure complete underfilling of the die and fillet formation. With current production dispense systems. The dispense needle must be placed close to the die so material contacts the gap between the die and the PWB. Since the viscosity of the underfill may increase with time at room temperature. A baseline volume or weight of underfill is dispensed with a known set of dispense parameters. if the underfill does not flow rapidly under the die. the dispense parameters may require minor adjustments over a period of time to maintain a constant volume. The density of the underfill is required in the weight based system to calculate actual dispense volume. Heating the underfill initially lowers its viscosity. However. Line Pattern Dot Pattern “L” Pattern Figure 29. the parameters can be automatically adjusted based on calibration using either volumetric measurement or weight based systems. the volume of underfill required to fill the space between the die and the board. From a production point of view. a large volume of material may accumulate beside the die. Board heating is typically used to increase the flow rate under the die. needle travel speed should be maximized. Conventional time-pressure dispense valves do not provide the required volume control and repeatability. the gap height and hence. For a rotary valve system these parameters would be dispense time and valve rpms. In production. the needle gauge and the travel length determine the volume of underfill dispensed. which increases its viscosity. the die bump pattern and the PWB topology and is determined experimentally. Common dispense patterns are shown in Figure 29. A design keep-out region must be defined around the flip chip die for underfill dispense. but also causes curing of the underfill. Dot and “L” Dispense Patterns.Johnson Ch19 page 27 Automated dispense systems are used to dispense a controlled volume of underfill in a precise pattern. The light area is due to reflection of the ultrasonic wave at the discontinuity caused by a large void in the underfill. The length of the line or the line segments of the “L” pattern must be adjusted to limit this ‘racing’ of material around the die perimeter. The gray area indicates complete underfill. some of the underfill may be ‘pulled’ to that component. a fillet dispense may be required to form a fillet around the die on the sides of the die where underfill was not originally dispensed (Figure 31). a void will be trapped under the die as the two perimeter flow fronts meet. A particular challenge with perimeter bumped die is the solder bumps tend to accelerate the flow of the underfill around the perimeter of the die. An example of this is shown in Figure 30. Scanning Acoustic Microscope Image of an Underfilled Flip Chip Die. If the flow around the perimeter exceeds the flow under the area of the die. trapping a void under the die. The underfill ‘raced’ around the perimeter solder bumps. The surface tension and wetting characteristics of the underfill continue to pull material under the die to form a fillet on the non-dispensed sides of the die. Time must be allowed for the underfill initially dispensed to flow completely under the die to prevent trapping a void under the die with the fillet dispense. Many fast flow underfills are selffilleting. eliminating the need for this step. Following the initial dispense of the underfill.Johnson Ch19 page 28 underfill contacts adjacent components. The variation in the amount ‘pulled’ would lead to a lack of underfill volume control for the flip chip die and possibly incomplete underfilling. . which is a scanning acoustic image through the flip chip die. Figure 30. Johnson Ch19 page 29 Line Pattern Dot Pattern “L” Pattern Figure 31. . The trend to finer pitch solder balls on the die (higher I/O counts) leads to a reduction in solder ball volume. The equation simplifies the actual flip chip structure by ignoring the presence of solder balls and their impact on increasing flow speed due to additional surface and capillary forces. 1 t = flow time µ = absolute viscosity L = distance traveled h = gap height γ = surface tension θ = wetting angle Figure 32 illustrates a common method to measure underfill flow speeds. ‘Dotted’ Lines Indicate Fillet Dispense Pattern. Underfill time is a critical issue in high volume production. The underfill is dispensed between two glass plates with a known separation and the time and distance traveled is measured. resulting in lower gap heights further increasing the flow time. no solder balls) described by equation 1 and the data can be plotted as t vs. Equation 1 relates the flow time (t) for a viscous fluid between two parallel plates with a spacing of h. L2. The wetting angle for the surfaces used in the test set-up may differ from the wetting angle of the surfaces in an actual flip chip assembly. This test method is equivalent to the conditions (parallel plates. This is a particular issue as the die size increases. Thus doubling the die size increases the flow time by a factor of four. The flow time increases as the square of the distance traveled and linearly with decreasing gap height. Newer generation ‘fast flow’ underfills have been introduced to increase production through-put. 3 µL2 t = hγ cos θ Eqn. An equation was developed to relate flow distance to the flow time (Eqn. 2). The underfill is dispensed into a reservoir and the flow distance versus time is measured. Sandia National Laboratories developed an alternate approach to measuring flow speed [12]. An example is shown in Figure 34. silicon or laminate Figure 32. Markers are also machined into the aluminum to facilitate measurement of underfill flow distance. X2 = (γ/µ) ∗ d ∗ f(α. The test uses a v-groove machined into an aluminum plate (Figure 33). Test Set-up for Measuring Underfill Flow Rate.Johnson Ch19 page 30 Underfill Glass Slides Spacer to Set Gap Glass.θ) = function of groove and contact angle Eqn .2 . The aluminum piece can be heated to investigate the effects of temperature on flow speed.θ) ∗ t X = distance traveled t = time γ = surface tension of fluid µ = viscosity of fluid d = characteristic depth of groove f(α. After underfill dispense. the material must be cured. Snap cure underfills with cure times .9674 1600 Distance Squared (mm^2) 2 2 2 R = 0.) Figure 34.942x y = 31.9961 R = 0. Cure conditions vary from supplier to supplier and range from 150oC to 165oC for 5 to 90 minutes. Distance Squared versus Flow Time as a Function of Temperature for a Commercial ‘Fast Flow” Underfill.012x 2 R = 0.9902 o o R = 0. Sandia National Laboratory Underfill Flow Test Method. 1800 y = 99.Johnson Ch19 page 31 Figure 33.215x y = 17.797x 1400 1200 1000 800 600 400 200 0 0 20 40 60 80 100 120 140 Flow Time (sec.9708 o 70 C o 85 C 100 C 115 C y = 12. the resin rich region in contact with the silicon die will have a higher CTE than the filler rich area. Solder extrusion from the solder balls into adjacent voids during thermal cycling also leads to early electrical failures. rework of field return units is often a consideration. 14]. if rework is required after underfill.7 Rework The removal and replacement of a defective flip chip is relatively straight-forward prior to underfill. To attach a replacement die. the die is aligned using split optics and the solder is reflowed by hot air. With continued heating the excess liquid solder remaining on the pads after die removal can be vacuumed or wicked away. Figure 32 is a C-mode SAM image of a good underfill dispense with no voids. After die . The chemical must not attach the PWB or surrounding components. In particular. care must be used in handling and probing. The purpose of underfill is to strongly bond the flip chip die to the PWB. Filler separation results in a nonuniform CTE within the underfill. This process requires application of the appropriate chemical to the die site and penetration of the chemical into the underfill under the die. The underfill is also now ready for easy removal from the PWB for site preparation. testing is not done prior to underfill dispense and cure. The second approach is thermally reworkable underfills [13. the optics and placement resolution must be greater for flip chip rework.Johnson Ch19 page 32 less than 10 minutes can be cured using in-line conveyor ovens. which in turn leads to electrical failures. flux is applied to the solder balls on the die by dipping. Cross sections and flat sections (polishing either the PWB or the die away) are used to compliment and verify SAM results. However. can fracture the delicate flip chip solder joints. some mechanism must exist for decreasing the underfill structural strength for die removal and site preparation. Figure 34 is a cross section illustrating filler separation. 3. The first is to chemically attach the underfill material. Two approaches have been taken to address rework. The underfill is designed to breakdown when heated to solder reflow (rework) temperature. In addition. while the 90 minute cures are usually performed in batch convection ovens. This breakdown of the thermoset network is a result of the incorporation of a monomer which has a special linkage designed to break apart upon heating. In many cases. and the die is removed with a slight twisting motion. Voids can lead to early delamination. High frequency transducers (>100MHz) are used to provide the necessary resolution to detect small defects. The breakdown of the network reduces the adhesion to the die allowing easy removal of the die. Scanning acoustic microscopy (SAM) is commonly used to develop underfill processes and dispense patterns as well as in-process sampling and process re-qualification. particularly the thin PWBs used in portable products. If boards are to be tested prior to underfill. while Figure 33 shows small voids in the underfill. The SAM can also be used to detect filler separation during the underfill flow process (Figure 33). Flexing of the PWB. The process is similar to ball grid array or chip scale package removal and replacement. Using a conventional hot air rework station the die is heated to typical reflow temperatures of 220oC. The die can be heated using a hot air rework station until the solder balls melt and the die can be removed. However. Johnson Ch19 page 33 removal. The flat-end horsehair brush provided the best cleaning with the least amount of damage to the board and the brush. A flat-end nylon brush wore away before one die site was cleaned. Figure 37 shows the site after preparation by brushing. A custom cleaning machine has been designed and fabricated (Figure 36). The machine provides x. significant underfill material remains on the PWB and must be removed prior to placement of the new die (Figure 35). Figure 35. Disk style brushes are not recommended because the disk is more difficult to control in the small work area. die that have been underfilled with this material can not be subjected to subsequent reflow cycles in the manufacturing process. reflow and underfill. Several different brush styles and materials were tested. Die Site after Die Removal. Since the thermally reworkable underfill is triggered at the rework (reflow) temperature. The die site is then ready for die placement. . Mechanical brushing is used to clean the die site. These materials will require a higher rework temperature. Reworkable underfills with higher trigger temperatures are being developed to allow reflow after underfill. and because its hard core can cause damage to the pads. y and z control. The assembly concept is illustrated in Figure 38. then dispense sufficient quantity of the fluxing underfill on the die site prior to die placement to serve as both the flux for soldering and when cured. The idea was to incorporate fluxing activity into the underfill material. The post reflow underfill dispense and associated . Pennisi [15] patented an adhesive and encapsulant material with fluxing properties. Automated Brushing Machine for Site Preparation. Die Site after Brush Cleaning.0 Assembly with Fluxing Underfills To reduce the number of process steps associated with flip chip assembly. The flux application step is replaced by the fluxing underfill dispense.Johnson Ch19 page 34 Figure 36. the underfill. 4. Figure 37. The fluxing underfill may cure during the reflow cycle eliminating another process step or it may require a post-reflow cure depending on the material. Acids are typically found in solder fluxes to provide the fluxing action of removing metal oxides to allow metallugical wetting. The formulation of a fluxing underfill is challenging. Illustration of Fluxing Underfill Assembly Process. . By increasing the acid content. the reflow cycle follows the dispense of the fluxing underfill and the potential exists for voids to form due to moisture release from the PWB or solder mask during the reflow cycle. potentially eliminating the need for a dehydration bake. If filler particles are trapped between the solder ball and the PWB pad during placement. the CTE of the fluxing underfill is significantly higher than traditional capillary underfills. the fluxing activity increases. Without filler. Shelf life. With fluxing underfills. A second source of gas generated voids in the fluxing underfill is outgassing from incompletely cured soldermask.Johnson Ch19 page 35 capillary flow time are eliminated. A dehydration bake is recommended prior to fluxing underfill dispense to remove moisture and to ensure the solder mask is completely cured. 4.1 Substrate Dehydration As previously discussed. but the shelf life decreases. Addition of filler to the fluxing underfill can decrease assembly yield. acids initiate the crosslinking of epoxies. fluxing underfills meet the thermal cycling requirements for many applications [17]. dehydration may not be necessary if the board goes immediately from side one reflow to second side assembly. this may be an added process step compared to the capillary flow underfill process and should be included in cost models. If a dehydration step is required. Fluxing underfills have no or low filler content. PWB laminate and solder mask absorb moisture from the atmosphere. In a two-sided SMT assembly process with the flip chip assembly on side two. fluxing activity level and lot-to-lot consistency are issues being addressed by the material suppliers and newer material systems are being introduced [16]. the PWB has passed through a reflow cycle just prior to underfill dispense and much of the absorbed moisture has been removed. they may prevent the solder ball from touching the PWB pad during reflow and wetting will not occur. Dispense Fluxing Underfill Place Die Reflow/Cure Figure 38. In the capillary underfill approach. However. Reliability studies have shown that even with the higher CTE. Shifting of the die with respect to the PWB pads can also result from die floating. the fluxing underfill should contact the center of the die first and then spread radially as the die continues to move toward the PWB. domed shape and the center of the die should first make contact with the underfill. Insufficient volume will result in non-wetting by some solder balls and incomplete underfilling. the underfill must flow outward as the die nears the PWB in a ‘squeeze flow’ process. 3) can be used to approximate the force [19-20]. The force also increases as the disc approaches the substrate (h0 decreases). die sizes. the force increases with increasing placement velocity. but this approach does not produce the smooth. the placement of a flat. and placement velocities. the Stefan equation (Eqn. If Funderfill equals the placement force before the solder balls contact the PWB pads (h0 > solder ball height). dome shaped deposit that is required for void-free die placement [18]. To understand the interaction of variables in the ‘squeeze flow’ process. If the outward movement is too fast. the fluxing underfill should have a smooth. Volume control is important in dispensing fluxing underfill. As the die proceeds downward. Stencil printing has been proposed as a higher speed application method. opens will occur.3 Die Placement During placement of a flip chip die in fluxing underfill. During placement. there is a potential to form voids behind the solder balls as the underfill flows outward. As the underfill is squeezed between the die and the PWB. 4. 3) Funderfill = force exerted by underfill R = radius of the disk µ = viscosity of underfill v = placement velocity h0 = height between disk and substrate From this equation. As previously mentioned. Placement experiments should . circular disc on a substrate with a Newtonian fluid in between can be considered analogous to the placement of a flip chip die in fluxing underfill. If the die ‘floats’ and the solder balls do not contact the pads on the PWB during reflow. and disc (die) size. the underfill is squeezed outward and the underfill contact circle with the die surface will expand outward dispelling air as it advances.2 Application of Fluxing Underfill The fluxing underfill is applied to the substrate by dispensing. Funderfill = 3πR4µ(-v) h03 (Eqn. For practical underfill viscosities.Johnson Ch19 page 36 4. while excess fluxing underfill can cause the die to ‘float’. it generates a force opposing the placement force. Assuming the disc and substrate are parallel and the volume between the disc and substrate is filled with underfill. underfill viscosity. then sufficient hold time must be programmed into the placement program to allow the die under constant force to traverse the remaining distance. Other dispense patterns have been used [16]. excessive placement force or hold times are not required to place flip chip die into fluxing underfills with high yields. Three approaches can be taken to address the profile issue. Figure 38. Cross Section Illustrating Good Solder Joint Formation with a Fluxing Underfill. complete curing of the underfill is not achieved during the reflow cycle and a post reflow cure is required. The first approach is to limit the cross-linking rate of the underfill by selection of the catalyst and the amount used. due to the slow cross-linking rate. 4. reducing the process advantage of fluxing underfills. increasing the viscosity. With a slower cross-linking rate. These underfills can be reflowed in a conventional SMT reflow profile (Figure 40).4 Reflow The reflow profile for a fluxing underfill is critical to high assembly yields. the post reflow cure time may be longer than the cure time for snap-cure capillary flow underfills.Johnson Ch19 page 37 be conducted to optimize the placement process for high electrical interconnection yield and no voiding. Figure 38 is an example of a good solder joint using fluxing underfill. In fact. While the viscosity of the underfill decreases with temperature. . The viscosity of the fluxing underfill must remain low until the solder balls melt to allow collapse of the die as the solder wets the PWB pads. the thermal energy input to the fluxing underfill during the early stages of the reflow profile accelerates cross-linking of the polymer. This reduces the sensitivity to the reflow profile. Figure 39 is a cross section illustrating the effect if the underfill viscosity increases before the solder melts. but adds a cure step similar to the capillary underfills. Cross Section Illustrating Poor Solder Joint Formation when the Fluxing Underfill Viscosity Increases too much in the Reflow Profile Prior to the Melting of the Solder. minimizing the thermal exposure of the underfill prior to the melting of the solder. Typical SMT Reflow Profile. In a mixed assembly with SMT components and solder paste to be simultaneously reflowed with the fluxing underfill. The second approach is the use of a ‘volcano’ reflow profile shown in Figure 41. Figure 40. This profile rapidly heats the assembly to the soldering temperature.Johnson Ch19 page 38 Figure 39. the compatibility of the SMT components and solder paste with this fast temperature rise profile must be established. . fluxing and wafer applied assembly approaches are compared in Figure . Example of ‘Volcano’ Reflow Profile. With mixed SMT assembly. Work is on-going to develop and refine these materials. the underfill is much less sensitive to the temperature and duration of the soak time in a conventional SMT reflow profile. Tem perature °C 200 150 100 50 0 56 112 168 224 Time (seconds) 280 336 392 448 Figure 41. 4. the challenge will be getting large SMT components to temperature without the flip chip die and underfill soaking at too high a temperature prior to solder melting. Advanced profiling tools are available to assist in profile development. fluxing underfills have not been commercialized but are under development.0 Wafer Applied Underfills To achieve a flip chip manufacturing process that is transparent to a standard SMT assembly line. which does not initiate cross-linking until temperatures slightly above the melting point of the solder. Since the underfill has not fully cured. These underfills typically cure during the reflow cycle. 5. The capillary. (courtesy of Emerson & Cumming) The third approach is to use a catalyst. the fluxing underfill should be applied at the wafer level and should cure during the reflow cycle [21].Johnson Ch19 page 39 250 207°C @ 112 sec. it has not achieved its full adhesion and mechanical strength and the die may be removed. It has been noted that the fluxing underfills that do not fully cure during reflow can be ‘reworked’ prior to the post reflow cure. New materials are being introduced into the market.5 Rework Reworkable. With this approach. Further work is required to develop truly reworkable fluxing underfills. Johnson Ch19 page 40 42. coating and assembly processes are currently being developed in the industry. Several . Fluxing and Wafer Applied Underfill Assembly Processes. eliminating the need for underfill dispense for each die individually at the assembly stage. Applying the fluxing underfill to the wafer simultaneously coats hundreds of die. wafer applied underfills are not commercially available at the time of this writing. The materials. 5. Current Process Flow with Capillary Flow Underfills Flux Dispense Place SMT Parts & Flip Chip Solder reflow Underfill Dispense Underfill Cure Solder Print Current Process Flow with Fluxing Underfills Fluxing Underfill Dispense Place SMT Parts & Flip Chip Solder reflow Underfill Cure if Necessary Solder Print Wafer Applied Underfill Process Flow Place SMT parts & Flip Chip Solder reflow Solder Print Figure 42. Comparison of Capillary.1 Application to wafer Finding a consistent and accurate coating method by which the material may be deposited onto the wafer is crucial to the successful implementation of wafer applied underfill. While significant progress has been made. with the silicon pad conforming to the shape of the substrate.4 µm. specially designed fluid pumping and delivery system. with a fine resolution and a locational accuracy of +/. This unique technique holds great potential for coating bumped wafers. Ink is spread onto the cliché and a silicone pad is pressed against the cliché then lifted. First. with the ink adhering to the silicone pad. A thin film of ink is deposited on the part. Pad printing has the ability to print over irregular surfaces. . Experimental Wafer Coating In recent work. The extrusion coating process has been extensively used for thick film application on semiconductors wafers up to 300mm in diameter. and the pad is pressed against the part and lifted off. The part to be printed is then aligned under the pad. where the gravure or cliché is patterned with the artwork to be printed and ink is transferred from the cliché to the part using a silicon pad. It is this characteristic that gives it great potential for coating a bumped wafer. A thin uniform coating layer with clean solder balls and clean saw streets were produced (Figure 43). A uniform coating thickness that does not coat the tops of the solder balls is required.6mm wafer.Johnson Ch19 page 41 techniques could potentially be used for coating a bumped wafer: 1) screen/stencil printing. the wafer-applied underfill was successfully applied on a 101.25. and other related items. flexible circuits. Pad Printing Pad printing is an offset gravure printing method. Extrusion Coating Extrusion coating is the direct application of process fluids to a substrate via a patented. artwork is transferred to a stainless steel cliché plate using a photo-etch process. This creates a highly uniform coating over the entire substrate with virtually no waste. with the ink transferring to the part. The challenge in this process is the irregular surface topology presented by the solder bumps. Screen/Stencil Printing The stencil and screen-printing processes are widely used in the electronics industry for the fabrication of printed circuit boards. 2) pad printing and 3) extrusion coating. In evaluating underfill color. 5. but the results to date are encouraging. If the coating process coats underfill into the saw streets. One additional issue that is being addressed is the sawing of the wafer.2 Placement The placement issues with a wafer applied underfill are vision recognition and holding the die in place after placement. In a typical wafer sawing operation. As the materials and coating process mature additional vision studies will be required. water is used to remove sawing debris and cool the saw blade. storage and automated pick-and-place. The compatibility of the b-staged underfill with water must be understood. the saw characteristics of the underfill must be examined particularly any tendency to ‘gum’ the saw blade.Johnson Ch19 page 42 Figure 43. . The shelf life and required storage conditions for the b-staged underfill are still being determined. Vision studies have been performed using standard pick-and-placement equipment used for traditional flip chip placement. the underfill is b-staged to produce a tack-free surface compatible with die placement in tape-and-reel for shipping. After coating. but must be compatible with transportation and inventory management. Photographs of Wafer Applied Underfill. black was found to be the best (Figure 44). it can be soften by heating to produce a tacky surface. Good solder wetting is observed. It is proposed that a focused heat source or soft beam laser be used to slightly heat the die just prior to placement. The wafer applied underfill is tack-free after b-staging. However. Figure 45 shows a cross section of a solder joint reflowed with wafer applied underfill. The necessary pick-and-place equipment modifications are being investigated. 5. . In flip chip assembly with capillary underfill. a tacky flux is used while the fluxing underfill provides the tack in that assembly process. The underfill cures during the reflow cycle. Comparison of Visual Contrast with White and Black Underfill. eliminating the need for a post reflow cure step.Johnson Ch19 page 43 White Coated Die Black Coated Die Coated die Cross Coated die Cross Section Figure 44.3 Reflow The reflow cycle for the wafer applied underfill is a standard SMT profile. Tack is required to hold the die in place during the time between placement and the melting of the solder. Laboratory tests are typically a single test . It is important in defining laboratory testing that new failure modes that do not occur in the field are not introduced while accelerating the test. the flip chip must meet the reliability requirements of the final product. electronic products are not exposed to a single test condition. In a board level assembly. This will be discussed in the next section.Johnson Ch19 page 44 Figure 45. accelerated laboratory conditions are used.4 Rework The ultimate wafer applied underfill will incorporate reworkability. As a component. The environmental exposure and expected product life varies significantly for mainframe computers. the flip chip must first survive the board level assembly process and then still meet the reliability requirements of the final product. If the wafer applied underfill must be exposed to multiple reflow cycles in the assembly process flow. The potential field failure modes for the product must be determined and appropriate laboratory tests requirements defined. but see combined environmental stresses. Cross Section of a Solder Joint Assembled with Wafer Applied Underfill. but it is too early in the development cycle demonstrate this capability. Since the actual field use conditions can not be used for the reliability testing due to the test time required. In field use. If flip chip technology is used to assemble a die into a package that is to subsequently be assembled onto a board. An example would be a flip chip reflowed onto a laminate carrier to create a flip chip BGA package (Figure 46). such as high temperature.0 RELIABILITY The reliability requirements of flip chip assemblies fall into two broad categories: 1) component level and 2) board or product level. 5. The primary concerns are the effects of moisture and reflow cycles on reliability. 6. Potential flip chip failure modes and test methods are shown in Table 4. pagers and automotive engine controllers. a higher rework temperature will be required if a thermally activated rework chemistry/process are used. component level testing is required. high temperature.). Table 4. thermal shock. Qualification testing of new materials and processes is time consuming and expensive. power cycling. accurate material . Failure Mode Underfill delamination Corrosion Test Methods Thermal cycling. sequential testing is often not practical. etc. highly accelerated stress testing (HAST) Thermal cycling. Effort has been devoted to developing ‘physics of failure’ models to evaluate new product designs in an attempt to reduce test time and cost. Sometimes. However. potentially superior new materials are not used because of the time and cost associated with their qualification. HAST Electromigration Excess intermetallic formation Die fracture Silicon cratering Alpha particles High temperature storage with current flow High temperature storage Thermal cycling. flexing High temperature storage.Johnson Ch19 page 45 Figure 46. thermal shock. This requires complete. flexing Electrical testing Solder fatigue Creep condition (thermal cycling. thermal cycling. humidity. Example of a Flip Chip BGA. Potential Flip Chip Failure Mechanisms and Test Methods. flexing Thermal cycing. thermal shock. There has been some effort to define tests that expose the assembly to multiple tests in a prescribed sequence. humidity. with ever decreasing time-to-market pressures. thermal shock. thermal shock Humidity. Moisture exposure can reduce the adhesion of the underfill.1 Component Level Testing As previously mentioned.Johnson Ch19 page 46 properties. Table 5. During reflow. the laminate and the solder mask may also absorb moisture. If the component is exposed to the atmosphere longer than the time specified. 60%RH for only 72 hours. the component must be used in assembly within the time limit indicated by its moisture sensitivity level. JEDEC J-STD-020A Definition of Moisture Sensitivity Level Level 1 2 2a 3 4 5 5a 6 2 Assembly Floor Life Time Conditions Unlimited <30oC/85%RH 1 year <30oC/60%RH 4 weeks <30oC/60%RH 168 hours <30oC/60%RH 72 hours <30oC/60%RH 48 hours <30oC/60%RH 24 hours <30oC/60%RH Time on Label <30oC/60%RH Soak Requirements Time (hrs. the component may be exposed to <30oC. In a flip chip package. If a laminate substrate is used in the package. This assembly failure mode is known as ‘pop corning’ as the mechanism is the same for popping popcorn. . Once the dry bag is opened.org) has developed test methods and an industry accepted definition of moisture sensitivity (J-STD-020A). A combination of modeling and stress testing is commonly used in the design for reliability and qualification processes. the rapid heating during the reflow cycle can liberate this absorbed moisture in the form of pressurized steam that can delaminate or crack the package. 6. 90%RH. component level testing adds assembly related exposure of the component to the product level reliability testing requirements.2 Moisture Sensitivity JEDEC Solid State Technology Association (www. The moisture exposure test conditions and factory storage conditions are listed in Table 5. the underfill can absorb moisture. If the component package absorbs moisture from the environment. If a component passes Level 1 test conditions it is deemed moisture insensitive and can be stored indefinitely at <30oC. Moisture sensitive components are dehydration baked to remove moisture and sealed in dry bags by the manufacturer for shipment and storage. 6. which are often not available.jedec.) Conditions 168 85oC/85%RH 168 85oC/60%RH 6962 30oC/60%RH 2 192 30oC/60%RH 962 30oC/60%RH 2 72 30oC/60%RH 482 30oC/60%RH Time on Label 30oC/60%RH Standard soak time includes a default value for semiconductor manufacturer’s exposure time between bake and bag plus the maximum time allowed out of the bag at the distributor’s facility of 24 hours. delamination at the die-to-underfill and the underfill-tolaminate interfaces may occur.1. At Level 3. it must be dehydrated prior to use to avoid pop corning during reflow. The moisture sensitivity level is marked on the dry bag. The primary issue is the exposure to multiple reflow cycles. To moisture precondition the component. thermal cycling. The growth rate for Sn-Cu intermetallics is greater than for Sn-Ni intermetallics. solder ball shear strength and cross sections after multiple reflow cycles can be examined. Electrical failure. etc. . the intermetallic will be either SnCu or Sn-Ni.Johnson Ch19 page 47 To determine the sensitivity level of a package. In this case. If the sensitivity level is not known. dewetting or embrittlement. Depending on the flip chip underbump metallurgy. tests must be preformed at multiple levels to determine the lowest level the package can pass.). The objective of moisture preconditioning is to induce any potential degradation of the component due to assembly to simulate the condition of the component on an actual assembly prior to environmental testing. Following the three reflows. temperature and humidity conditions specified for the sensitivity level of interest in the left column (soak requirements) of Table 5. cracking or delamination are criteria for failure at a given sensitivity level. Figure 47 plots the solder ball shear strength as a function of reflow cycles. temperature and humidity test level (left column of Table 6) consistent with the moisture sensitivity level rating of the component. the components are subjected to three reflow cycles defined in the J-STD-020A. The reflow cycles are to follow no sooner than 15 minutes after removal from the humidity chamber and not longer than 4 hours after removal.2 Preconditioning For environmental testing of components.1. Following exposure. moisture preconditioning is often specified. Multiple melting of the solder ball during reflow cycles can lead to excess intermetallic formation. To evaluate intermetallic formation. the component is exposed to three reflow cycles (240oC peak) within 0. 6. Excess intermetallic formation can lead to failure by delamination. The inspection includes a visual inspection for cracks and scanning acoustic imaging for any delamination. the components are electrically tested and inspected. Then the components are exposed to the time. The component is then tested (electrical. no degradation in strength was observed. After the temperature and humidity exposure. the components are first electrically tested and inspected.5 to 4 hours. visual and acoustic microscopy) and ready for subsequent environmental testing (thermal shock. it is exposed to the time. (courtesy of Flip Chip Technologies) 6. . Fatigue failure results from cyclic stress.2 Environmental and Board Level Tests 6. will creep is a failure under constant stress or load. Figure 48 shows creep failure of flip chip solder joints held at constant force at 165oC.1 Thermal Cycling and Thermal Shock Electronic products are normally exposed to variations in environmental temperatures in actual use. The mismatch in coefficients of thermal expansion (CTEs) of the materials used to construct the product result in mechanical stresses as the temperature varies.Johnson Ch19 page 48 Figure 47. Solder is susceptible to failure under stress by two failure modes. The creep failure rate increases with increasing temperature. Solder Ball Shear Strength as a Function of Reflow Cycles.2. The transfer of heat by liquid contact is very efficient. thermocouples are required to measure the actual temperature ramp rate and to ensure that all parts reach the temperature extremes. As mentioned in Section 1. Direct correlation of laboratory test results to actual field life is complex. During thermal cycling/thermal shock there is also stress on the underfill globally and locally at the underfill-to-die and underfill-to-laminate interfaces. the temperature range. . In laboratory testing. the heat transfer rate is less for the air-toair system. (Courtesy of Delphi Delco) Failure of flip chip solder joints in thermal cycling and thermal shock testing result from a combination of fatigue and creep. the cycle time is longer. solder joint fatigue failures can ultimately occur without delamination (Figure 50). While this may better represent the actual temperature cycle rate in the field. the temperature ramp rate and the hold times (particularly at the high temperature hold time). extending the test time. For air-to-air thermal shock. The temperature ramp rate is significantly slower. There is increasing use of thermal shock testing in the industry to accelerate testing to meet product development cycle requirements. A typical failure mode is delamination of the underfill (most commonly at the die-to-underfill interface) and then rapid failure of the nearby solder joint. An example is shown in Figure 49. In thermal shock. the test boards are moved from one liquid held at the high temperature to a second liquid held at the low temperature. In liquid-to-liquid thermal shock. underfill is used to increase the thermal cycle/thermal shock life of flip chip solder joints. With high adhesion underfills that do not match the CTE of the solder. Since the thermal mass of the test boards and any fixtures or test cables impacts the amount of heat to be transferred. the transition time from hot to cold and back is very rapid. while the hold times are decreased to accelerate the test and reduce test time. The air in the two chambers is maintained at the two test temperatures. While the rapid transfer between chambers is comparable between liquid-to-liquid and air-to-air. Thermal cycling often uses a single chamber that is alternately heated and cooled. the test boards are automatically shuttled between two chambers. the ramp rate and the temperature range are increased.Johnson Ch19 page 49 Figure 48. Creep Failure of Flip Chip Solder Joints with a Constant Force at 165oC. The role of each failure mechanism is dependent on the materials. The difference between thermal cycling and the thermal shock is the ramp rate. As discussed in the underfill dispense section. There was no delamination of the underfill. During thermal cycling. . voids in the underfill are a processing defect. Figure 50. C-SAM Image of Underfill Delamination Due to Thermal Shock Cycling. extrusion of solder into voids between adjacent solder balls can lead to shorts as shown in Figure 51. Solder Joint Fatigue Failure.Johnson Ch19 page 50 Figure 49. . Either the solder joint will ultimately fail open or the underfill may crack and solder will extrude into the crack forming a short (Figure 52). the solder is compressed by the underfill on the cold side of the cycle and is in tension in the z-direction on the hot side of the cycle.Johnson Ch19 page 51 Figure 51. Cross-Section of a Short Due to Extrusion of Solder into Void between Adjacent Solder Balls. If the CTE of the underfill is higher than that of the solder. This extruded solder could lead to shorts within the PWB. This can be explained using the illustration in Figure 53. Upon heating to the high temperature extreme.Johnson Ch19 page 52 Figure 52. Solder extrusion has been observed in PWB cracks at the base of solder balls. In-situ resistance monitoring is required for accurate thermal shock or thermal cycle testing of underfilled flip chip die. Cracking of the underfill fillet and cracking of the PWB are also observed in thermal cycle and thermal shock testing. Failures (high resistance/open circuits) have been observed with daisy chain test die in the hot bath hundreds of cycles before the failure is observed at room temperature or at the cold extreme. Propagation of these cracks can lead to either delamination or cracking of large silicon die. Flat Section (Die polished away) Showing Crack and Solder Extrusion in Underfill Between Adjacent Solder Balls after 3200 Thermal Shock Cycles. Thus periodic measurements for continuity at room temperature will not discover high temperature intermittent opens and will over estimate the reliability of the connections. However. at the cold temperature extreme the contraction of the underfill (the CTE of the solder is lower than that of the underfill) will hold the cracked solder joint together maintaining electrical continuity. From finite element modeling. particularly HDI boards. the expansion of the underfill will open the crack and a failure can be measured. . the maximum stress on the solder joint occurs at the low temperature extreme of the cycle since the ‘stress-free” temperature should be near the cure temperature of the underfill. Thermal cycling and thermal shock can also lead to die fracture. the backside of the silicon die is placed in tension during the cold side of the cycle. it bends or warps. Any defects in the backside of the die such as microcracks from ejector pins can serve as stress concentrators and a crack can propagate through the silicon. Example of Flip Chip Die Fracture (Courtesy of Flip Chip Technologies).Johnson Ch19 page 53 High Temperature Room Temperature Figure 53. Illustration of the Need for In-situ Monitoring. Since the PWB contracts most. As the structure is cycled. The underfill couples the silicon die to the PWB. Figure 54. . An example of die cracking is shown in Figure 54. the silicon die starts to expand before the underfill. the semiconductor devices dissipate power and get hot first. 6. bump alloy and service temperature determine the intermetallic growth rate. 6. UBM thickness. Adhesion loss and delamination is the common failure mode.2. Figure 55 is a cross section of a flip chip solder joint after 3000 hours storage at 150oC. delimitation and embrittlement.3 Flex Testing Many portable products have integrated keypads. bump alloy. A humidity level of 85%RH can be achieved at 121oC under two atmospheres of pressure. intermetallic formation can lead to dewetting. assembly processes and service temperature. Delimitation can occur. 6. and pressure combinations can also be used.2. solder and PWB do. Failure is detected by electrical failure.4 Temperature/Humidity/Bias Aging Electronic products are exposed to atmospheric moisture. Flip chips on the opposite side of the PWB would experience cyclic mechanical stresses. The potential failure mode is corrosion in the presence of humidity and electrical bias. shorts and opens. Thus. Other humidity.2.2 Power Cycling When an electronic product is turned-on. Pressing of the keypad flexes the thin PWB. temperature. The assembly .5 Autoclave and HAST An autoclave is a pressure vessel used to accelerate humidity/temperature testing. 6. Autoclave testing is sometimes used to rapidly screen underfill materials for moisture sensitivity. Temperature increases the moisture level and is an accelerating factor in corrosion. No clean flux residues are also formulated to be chemically inert after the reflow cycle. Underfill significantly increases the reliability in these applications. The epoxy underfills are formulated with very low extractable chlorine levels to minimize the potential for corrosion. The intermetallic formation at the solder-to-PWB pad and the solder-to-under bump metallurgy (UBM) is evident.2. As previously mentioned. Temperature/humidity/bias aging is used to evaluate the product reliability. Humidity and temperature can also result in degradation of underfill adhesion. HAST accelerates humidity/temperature/bias aging tests. A common test is 85%RH/85oC/+5V for 1000 hours.Johnson Ch19 page 54 6. The UBM metallurgy. Power cycling tests should be conducted for die that dissipate significant power and that are subject to power cycling in the product application.2. Power cycling can result in stress on the assembly and failure.6 High Temperature Storage and Electromigration High temperature storage examines potential decomposition of the underfill and intermetallic growth in the solder joint. Highly Accelerated Stress Test (HAST) is the addition of bias to the autoclave test. Factors affecting reliability are: UBM metallurgy. If current flows through the solder bumps at elevated temperature. Finally. Increasing the current density (number of electrons per unit area) and temperature increases electromigration. the Sn and Pb grains are separated by electromigration due to their different masses as evident from Figure 56. the UBM thickness determines the amount of metal available for consumption. In Sn/Pb eutectic solder.Johnson Ch19 page 55 process (number of reflow cycles. Since copper forms intermetallics with Sn-Pb eutectic solder at a faster rate than nickel. the maximum current a solder ball can carry decreases with increasing temperature and decreasing UBM/via size (increased current density). Electromigration is the movement of metal by momentum transfer from electrons. etc. Figure 55. (Courtesy of Delphi Delco) . electromigration may occur. From the plot. copper UBMs must be thicker than nickel UBMs. The concentration of Pb moves from the bottom of the solder ball to the top when the direction of current flow is reversed. Cross Section of Solder Ball Aged at 150oC for 3000 hours.) impacts the original intermetallic formation during assembly. reflow profile. Device Side + Current Carrying Capability (mA 500 UBM/Via 150/125 um UBM/Via 120/100 um 400 UBM/Via 100/80 um 300 200 100 0 150 Bump connected to the negative node of power supply.2. A high energy alpha particle (8MeV) could generate up to 2.7 Alpha Particles An alpha particle is the nucleus of a helium atom (He 4 ++) that is emitted through radioactive decay. but the data stored in the device is corrupted.Johnson Ch19 page 56 Device Side - Bump connected to the positive node of power supply. (Courtesy of Delphi Delco).5 x 106 electron-hole pairs and cause soft errors in a sensitive semiconductor device. is being addressed by the third party bumping companies. uranium (U). the availability of bumped die. polonium (Po). The soft error is not permanent damage to the device. The continuing increases in semiconductor speed. While the current assembly process with capillary underfills is more complex than standard SMT assembly with packaged components. Electromigration Test Results and Cross Sections. particularly memory. advances in materials and processes such as wafer applied underfills may soon address this. low alpha emission lead or lead and bismuth free solders can be used. die size and I/O count coupled with the explosion of the portable electronics market makes flip chip an attractive assembly technology.0 SUMMARY Flip chip technology has been in use for nearly four decades. In the future. 6. and lead isotopes (Pb 214 & Pb 210 ) are the primary sources of alpha particles in tin-lead solder. 7. Redistribution of perimeter I/O die designed for wire bonding significantly adds to the bumping cost. Trace amounts of thorium (Th). more die will be designed for flip . 140 130 120 Bump Temperature (degree C) Figure 56. Another limiting factor. To reduce soft errors. April. 3. Lawrence Crane. 270-274. “Process Limit Testing on Fluxes Used for Flip Chip Soldering. Paul Novak. Testing and burn-in of bumped die still remains a hurdle to widespread usage of flip chip. Michael Gibson.” Proceedings of the 1998 Surface Mount International Conference. May 1969. March 1991. McCreart. Orlando.” International Journal of Microcircuits and Electronic Packaging. New York. P. Varcoe. CA. Hybrids. San Jose.0 REFERENCES 1. 9. pp. 858-862. and Douglas Gullion. and Manufacturing Technology.” IEEE Transactions on Components. Z. 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