2012 Annual RELIABILITY and MAINTAINABILITY SymposiumElectronic Part Failure Analysis Tools and Techniques Walter Willing, Jonathan Fleisher & Michael Cascio Walter Willing, Jonathan Fleisher & Michael Cascio Northrop Grumman Corporation 7323 Aviation Blvd, Baltimore, MD, 21090, USA e-mail: [email protected]
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Tutorial Notes © 2012 AR&MS ............. 8......................... 2....................................................................... At Northrop Grumman he has 10 years of engineering experience in Failure Analysis and Reliability..... Member....................... System Supportability Engineering Department................................................. Jonathan Fleisher Mr..... Table of Contents 1................. 3.....................12 References .................................. Vice Chairman of the Baltimore Section)............ Fleisher received a BSME and an MSIE from New Mexico State University......................13 ii – Willing................. maintenance and support equipment for 20 two million dollar radars.......1 Basic Failure Analysis Techniques ... Willing is a Senior Advisory Reliability Engineer within the Northrop Grumman Corporation Electronic Systems Sector..................................................... He also directed the research and development upgrades on the enhancement of radar systems.................. Reliability and Failure Analysis................................. Mr. with multiple Systems Engineering responsibilities......... Michael Cascio Mr.. He has 16 years of engineering experience on a variety of defense related programs.. 6........ he has focused on reliability engineering for NGC Space Programs...7 Failure Analysis Case Study.................................12 Tutorial Visuals…………………………………………………………………………………….............. He has authored five peer reviewed technical papers and one RADC publication... 4.....11 Conclusions ............................................... ............ Walter Willing Mr.........................................................SUMMARY & PURPOSE The current emphasis on Physics of Failure (PoF) and accurate Root Cause Analysis (RCA) highlights the need for effective electronic part failure analysis processes and capabilities..... He is active in the IEEE (Sr................. Willing has over 30 years experience in space systems reliability........ 5................. Introduction ........................ He has over 20 years of electronic experience in Radar............7 Understanding Electronic Part Failure Mechanisms ..................... Cascio received a BSEE from The Pennsylvania State University............. He spent eleven years in the United States Air Force where he managed operations....................................................................... 9........ including Environmental Qualification Lead on several radar programs................. Fleisher & Cascio 2012 AR&MS Tutorial Notes ............................. In addition............................................................ the common failure mechanisms found in electronic hardware are explained and emphasized with a case study............................................. During the last several years..................................................... Cascio is a Failure Analysis and Reliability Engineer within the Product Integrity Department of the Northrop Grumman Electronics Systems Sector in Baltimore Maryland.................... He received a BSEE from the University of Delaware and an MSEE from the Loyola College of Maryland........................2 Suggestions for Your Own Failure Analysis Capabilities . This tutorial presents a “Process” as well as the tools and techniques required to perform effective failure analyses on electronic components..................................... IEST and serves on the RAMS Management Committee.... 7.... Fleisher is a Principal Reliability Engineer within the Northrop Grumman Corporation Electronic Systems Sector.........................1 Importance of Effective Failure Analysis.......... Mr......... Failure analysis can be as simple as visually inspecting a part and as extensive as performing sub-micron level cross-sectioning of silicon die using Focus Ion Beam (FIB) technology...... Mr............ System Supportability Engineering Department........................ tools and techniques that can be utilized to accurately determine why devices fail. Fleisher & Cascio . This tutorial discusses the fundamental electronic part failure analysis processes. Human body electrical static discharge (ESD) overstress is also a well-known and documented mechanism that damages components. devices can be de-lidded (or de-capsulated) and silicon die inspections and evaluations can be performed. after all non-invasive tests are completed. Plait award winning tutorial “Understanding Electronic Part Failure Mechanisms”. the “requirements” and methods within these standards provide a good baseline for evaluating failed parts. Root cause for 2012 AR&MS Tutorial Notes 1 – Willing. Moderate. First. It is important to know what the common part failure modes are as well as the failure analysis techniques used to find them. The failure analysis process is also important. Analysis and Corrective Action System). not “Lost” due to carelessness. space satellite systems. Subsequent steps should involve non-invasive examinations such as microscopic visual inspection. ICs rated below 250V for ESD are easily damaged by human handling without adequate ESD controls. 2. This tutorial is an expansion of the 1997 O. parts removed for failure analysis may “Re-Test OK” (RTOK) as a result of the wrong part being removed. All power inputs to electronic assemblies should be properly controlled to protect against fault conditions and unattended transients. A common term for the process of root cause determination and applying corrective action is called FRACAS (Failure Reporting. For example. Failure Analysis must be performed correctly to assure the failure mechanism is preserved. the packages are very brittle and susceptible to cracking due to stress risers from either surface anomalies or general mounting. when evaluating the wirebonds on a failed part. Effective root cause analysis of part failures is required to assure proper corrective action can be implemented to prevent reoccurrence. methods. Examples of solder joint failures are shown in Figure 1. deep well drilling systems. Advanced) as well as some examples of actual failure analyses to illustrate what actually occurs in failed hardware.25inch size are the parts that are most susceptible to solder joint wear out failures. It is also commonly responsible for latent failures due to joint fatigue driven by thermal cycling. it’s important to understand why they failed. the pull test limits in Mil-Std-883 (Method 2011) can provide insight as to whether the failure part has good wirebonds. Inadvertent connections or rapid switching to full amplitude voltage levels can lead to inrush or high transient conditions that can damage components. Finally. or the fact that testing does not properly capture the part’s failure mode (such as a subtle parameter shift) or a particular failure sensitivity (gain vs temperature) exists. Since it is important to preserve and characterize the failure mode to the greatest extent possible. However. For example. IMPORTANCE OF EFFECTIVE FAILURE ANALYSIS When electronic parts fail. it’s quite common to experience electrical overstress due to transients related to test setups.1. The following are some top causes for component failures experienced on various types of electronic equipment: 1) Electrical Overstress: During board level testing. 3) Solder joint failure: Solder joint workmanship is the most common issue related to initial assembly or board fabrication. this tutorial presents a suggested failure analysis flow. 4) Cracked Ceramic Packages: Ceramics are used for the majority of high reliability military and space applications. where failures are critical. it is important to verify and characterize the failure via electrical test. sections of which are repeated in this tutorial (refer to Section 5). X-ray and hermetic seal tests. Understanding the cause of the part failure allows for effective corrective action and the prevention of future occurrences. bypassing critical measurements or performing destructive analyses in an incorrect sequence. INTRODUCTION Organizations that produce electronic hardware should have some level of electronic part failure analysis capability and knowledge of where to go for extended failure analysis. Additional information on failure analysis methods can be found in Mil-Std-883 and Mil-Std1580. 2) Contamination: One of the more common causes of latent failure is due to contamination. Sources of contamination can typically be traced to either human byproducts (Spittle) or chemicals used in the assembly process. Determination of root cause is also important for High Reliability systems such as implantable medical devices. etc. once wirebonds are removed. Failure Analysis is the crucial part of the FRACAS process. For further investigation into advanced failure analysis techniques and component failure modes. While these specifications define test and evaluation methods. The following sections herein address basic failure analysis techniques.A. followed by non-invasive and finally invasive failure analysis techniques. ESD sensitive integrated circuits (IC) are the most commonly affected. Non compliant or leadless ceramic type components of >0. starting with full part failure characterization. Suggestions for several levels of failure analyses capabilities will be presented (Basic. as well as consumer products where the cost of a single failure mode can be replicated multiple times. The internal visual inspection criteria of Mil-Std-883 (Methods 2010 and 2017) help determine whether any anomalies are actually defects or allowed process variations. Furthermore. the reader is encouraged to become familiar with the International Reliability Physics Symposium (IRPS) as well as other venues. the part may not be able to be electrically tested. Contamination can also rapidly destroy wire bond interconnects and metallization. Contamination ultimately leads to failures stemming from corrosion or degradation related to active elements such as semiconductors. 5) Timing Issues: Inadequate timing margins are sometimes misdiagnosed as intermittent component behavior. improper reset sequencing. it is highly recommended that all resources available be used prior to replacing them. power. Invasive Tests Lid Removal / Decapsulate Die Examination Die Probing IR Microscopic Exam Liquid Crystal Cross-Sectioning SEM EDS/EDX FIB Auger SIMS FTIR TEM/STEM 3.these issues can typically be traced to either design implementation or process control. Examples include inadequate derating (voltage. contacting the vendor before removing high value parts is advised. The most common of these is due to mismanaging component thermal conditions and operating parts outside their rated power dissipation limits. 7) Design Implementation: Often component failures are related to poor design implementation rather than random defects in the components themselves. voltage or clock speed sensitivities associated with the part’s performance. Additional details pertaining to these tests and methods are discussed in this section Table 1. it is also recommended to photograph the part as installed for future reference. the cognizant Failure Analysis engineer should review the troubleshooting results while the part is still on the board witnessing any in-situ part measurements (for later verification in the FA lab) and noting any anomalies that exist on the board which may potentially have contributed to the part failure. General Failure Analysis Process Electrical Testing / Characterization Test / Characterize over temperature Curve Tracer I-V check of Inputs Non-Invasive Tests External Microscopic Exam / Photo Fine & Gross Leak Vacuum Bake (Non-Hermetic Parts) X-ray PIND XRF SAM / C-SAM Figure 1. the fault may still exist at the board level) and to determine if there are any temperature. As some devices can cost many thousands of dollars to replace. In addition. or applying low bias voltages. Another step in part characterization is to perform a curve tracer current vs. 3. Reviewing the failure data with the vendor can often identify external interfaces as the culprit rather than the suspected part. Defective Solder Joints 6) Power Sequencing Issues: Many of the IC technologies are susceptible to damage if bias voltages are not properly applied prior to control or data input voltages. as it is necessary to confirm the part has indeed failed (if not. BASIC FAILURE ANALYSIS TECHNIQUES The basic flow for effective part failure analysis starts before the component is removed from the board. Photos should be taken from various angles to capture the details of the installation. Prior to removing a part from the board.1 Electrical Part Testing and Characterization Electrical part testing and characterization is important. such as the solder attachment. All parts should be fully electrically tested at ambient. three (3) basic processes should be followed: • Electrical Testing and part characterization • Non-Invasive tests • Invasive tests This general failure analysis process is illustrated in Table 1. The Failure Analyst should also be consulted on the safest means for removing the part to preserve it to the greatest extent possible. cold and hot temperatures to determine if the failure is sensitive to temperature. Thorough timing analysis should be part of any design in particular when asynchronous signals are present. Fleisher & Cascio – 2 . floating CMOS inputs. Upon completion of the board troubleshooting and fault isolation process. Once the part is removed for failure analysis. and thermal). voltage (IV) characterization of each input signal 2012 Annual RELIABILITY and MAINTAINABILITY Symposium Willing. over temperature. die attach perimeter) • Solder joint quality for connectors • Insufficient or excessive solder • Substrate or printed wiring board trace integrity • Obvious voids in the lid seal • Foreign metallic particles within the package • Internal part orientation. first an X-ray is taken. as a Gross Leak site may be large enough to allow a full venting of the pressurized He.2. 3. It is important to perform both Fine Leak and Gross leak testing. forcing it through any large leak sites. which is usually sufficient to identify such items as external contamination and/or solder balls (possibly shorting out pins on the device). 3.e. Newer optical leak test equipment using laser imaging of package lid deflection to confirm hermeticity is also available. There are multiple types of X-ray equipment available. often referred to as X-ray.1 External Microscopic exam / Photo Using a stereo microscope. The authors were recently involved with a case where trapped moisture affected the performance of an RF cable. The principal limitation of film X-ray is that it only allows one exposure level at a time. a thorough external visual examination of the suspect part should be performed early in the failure analysis process.2 Non-Invasive Examinations Once the failed components have been fully characterized via electrical testing. damaged leads or package seals. 3. etc.3 Vacuum Baking If a non-hermetic part or cable is suspected to have a moisture related issue. While Xray techniques can be used to detect internal particles. it can provide evidence of internal particles. The following conditions should be specifically looked for: • Contamination • Mechanical damage • Thermal or electrical damage • Seal integrity • Lead integrity Photographs should be taken to document the condition of the part and to record any anomalies. and then a second X-ray is taken.2. voltage. from the basic film X-ray systems to real-time and 3-D X-ray systems. The resolution of a basic film X-ray is typically to a 1 mil particle size.2. the modern real-time X-ray provides a more extensive capability. another method is Particle Impact Noise Detection (PIND).2 Fine & Gross seal tests for hermetic devices Hermeticity testing (refer to Mil-Std-883 Method 1014) should be performed on hermetic parts to ensure no leaks that could have allowed moisture to enter the package exist. clock speed I/O Curve tracer assessments – Compare to known good devices 3. This allows one to identify particles that are free-floating within the package.4 um and allows for a continuous adjustment of exposure levels and conditions. Basic X-rays allow internal part examination looking for: • Internal particles • Internal wire bond dress • i. Magnification levels up to 100X can be employed to further examine any anomalies identified. A fine leak test often involves placing the part in pressurized helium (He) chamber in an attempt to force He into the device cavity through any leak sites. Real-time.2. real-time X-ray typically has a resolution range from 1um to 0. 2012 AR&MS Tutorial Notes 3 – Willing. Electrical Testing / Characterization Outline: Test / Characterize.5 PIND Test / Particle Impact Noise Detection (PIND) Cavity device failures can be caused by internal conductive particles shorting adjacent conductors. Not all characteristics can be observed at a single exposure level. Gross leak testing involves placing the part in a heated fluorocarbon bath and literally “Looking for Bubbles”. Any internal moisture might result in possible corrosion or provide a conductive path on the semiconductor die surface. However. or bond wires to 1 mil diameter. If the problem disappears after the vacuum bake process. is a very powerful tool for non-invasive failure analysis as X-ray can detect actual or potential defects within enclosed packages. thereby causing a failure.4 X-ray (Film. 3D) Radiograph (refer to Mil-Std-883 Method 2012). 3. PIND Testing can be subjective and may not be easily performed on complex hybrids. gross cracks in the package.(typically to ground) to determine if any input overstress have occurred. While film X-rays can be useful. A common technique employed is to perform X-ray and PIND together. The heated bath causes the atmosphere within the package to expand. It is important to perform all necessary noninvasive tests and examinations first. refer to Mil-Std-883 Method 2020. can make sure the wire bonds are not touching each other or package lids • Die attach quality (voiding. Fleisher & Cascio . 3. as well as real time part rotation to obtain the most revealing Xray view.2. a vacuum bake can be performed to drive out any residual moisture. humidity could have been the cause. so as to not destroy any “evidence” until a good set of non-invasive characteristics have been defined for the failed part. etc. then moving the part to a Helium detection chamber to see if any He leaks out. then the part is PIND tested. subsequently resulting in a false pass for the fine leak test. The IV characteristics of the failed part can be compared to a known good part with any deviations noted and recorded for later die examination. Conversely. It is also important that the failed part be clean of any external epoxy or contamination that could absorb the He and provide a false positive reading. non-Invasive examinations can be performed. Typical inspection scopes range from 10X to 30X magnification. Special digital filtering and image processing can also be used to detect possible delineations in the image not otherwise observable on the image screen. 2 Die Probing If the failure analyst is familiar with the part die.7 Acoustic tests (SAM / C-SAM) Acoustic testing is a popular test method to look for voids and delaminations or cracks in Plastic Encapsulated Microcircuits (PEMS) and ceramic capacitors. as changing the lighting conditions can help reveal anomalies.3 Invasive Examinations. RGA (refer to MilStd-883 Method 1018) involves “Poking a Hole” through the device lid. a chemical vapor deprocessing (desolving) of the encapsulant material must be performed. such as damaged metal traces. A second option is to punch a small hole in the thinned lid and cover it by adhesive tape. For water vapor. probing using micro-manipulators and special probes can be performed to determine if any die metallization traces are 2012 Annual RELIABILITY and MAINTAINABILITY Symposium Willing. 3. The X-rays excite atoms in the sample. then Residual Gas Analysis (RGA) should considered once all non-invasive tests are performed. Acoustic tests involve either reflected acoustic energy or energy transmitted through the part. an RGA test should be considered as cold temperature failures may be a result of excessive internal moisture condensing on the die surface. XRF is commonly used to examine platings for pure tin content.2. the acoustic energy is blocked and voids can be detected. the maximum allowed concentration is typically 5000 ppm. a microscopic die exam should be performed to look for obvious issues. As “Flip Chip” devices become more popular. chip to substrate “de-stacking” will be required. Fleisher & Cascio – 4 .3. it’s time to “Bite the Bullet” and dig deeper into the part. for a failure associated with a melted wire bond. The XRF equipment measures the energy and intensity of these X-rays and is capable of detecting elements from Al to U in the periodic table. Since the energy transmission medium is typically deionized water. For cavity parts. XRF can accurately quantify the elemental composition of the samples. often by grinding down the lid around the seal ring or weld seal. Acoustic tests rely on acoustic energy transfer through the part. this often involves a process called “delidding” where the device lid is removed. using a vacuum to remove the interior gas and performing a spectral analysis of the internal gases to determine their content. Part De-Lid / De-Process After all Non-Invasive examinations have been performed. Device with lid removed– Revealing open wire bond. In either case. The acoustic tests can also be tuned to attempt to determine the depth of any void. This corresponds to the dew point (sublimation point) of -2C where the partial pressure of the H20 prevents any liquid condensation. Figure 2.8 Residual Gas Analysis. XRF can determine concentrations ranging from parts per million to 100% at depths as great as 10µm. This procedure results in the particle being stuck on the tape. Figure 2 presents a part with the lid removed. The part can then be run on the PIND tester until the noise stops. exposing the particle of interest. broken or damaged wirebonds. Microscopes equipped with both dark and light field illumination are helpful. as well as for cadmium and zinc . causing them to emit X-rays with energies characteristic of each element present. If a cavity device has been determined to contain an internal particle via X-ray or PIND testing. one technique that can be used to capture the particle is to first grind down the lid in one corner to the point where the cover thickness in the corner is very thin. For this process. for a hermetic part suspected of having an internal moisture issue. etc. die cracks.5. Using reference standards. Finally the corner can be carefully pealed back. If there is a void.2. Deep UV optical microscopes can reach 16. 3.000X magnification and are capable of resolving 10 microns. Photographs should be taken to document the condition of the die and to record any anomalies. sending the parts back to the original manufacturer is recommended.Section 5. 3. 3. internal water vapor content Before transitioning to invasive examinations.3. 3. These examinations are typically performed using a microscope at magnifications of 100X to 1000X.6 X-ray Fluorescence (XRF) X-ray Fluorescence (XRF) is a non-destructive technique used to determine the elemental composition of solid and liquid samples. RGA can detect most of the gasses found within devices and report their individual concentrations.3 discusses loose particles detected during PIND test. 3.2. then try to “shake” the particle down to that corner. For Plastic Parts. the goal is to expose the top chip surface to allow for visual examination. parts to be examined must withstand exposure to water.1 DIE Exams Once the top surface of the die is exposed. If a part only fails at cold temperature. While a calibrated IR microscope can provide an actual die thermal measurement. The resolution of IR microscopes is on the order of 1 to 5 microns. transistor and diode failure analysis. It is often used for connector. The SEM can provide detailed images of up to120. The potted sample can be cut in half initially to target the failure site. is a technique used along with a SEM to identify the elemental composition of a sample. alternately known as EDS.6 Scanning Electron Microscope (SEM) A Scanning Electron Microscope is an important tool for semiconductor die failure analysis. is the liquid crystal die thermal mapping. an IR Microscope or liquid crystal die thermal mapping. By spectrographic analysis of the emitted X-rays. causing some of them to be knocked out of their orbits. It has a higher resolution to determine exactly where the hotspot exists on the die. These kinds of “ball lifts” are quite often a result of “Kirkendall voiding” and could represent a fundamental wire bond issue with the part. 3. Wire bonds should be checked. defects on semiconductor die are associated with “hot spots”. 3. the depth of field is fairly large.1. NANO SEMs can resolve features down to 10 Angstroms.3. There are two commonly used techniques to look for hot spots. Detailed knowledge of the die design is necessary when performing this type of probing. printed wiring board. Fleisher & Cascio be made. Figure 3.8. The more accurate technique. Of course. These electrons collide with the electrons within the sample.shorted or open or to confirm an internal bias level. especially if a bad interconnect is suspected. it can be further examined using high power microscope examinations. thereby providing a better overall three-dimensional view of the sample.000 to 100.3. so it needs to be in a state where the leads can be connected or the die pads can be probed and voltages applied. capacitor. More information on FIB techniques is discussed in section 3.3. Cross-Sectioning is exactly as the name implies.000 X magnification. EDAX or EDX. SEM examinations are often used to verify semiconductor die metallization integrity and quality (refer to Mil-Std-883 Method 2018). With a SEM image. the liquid crystal technique shows a relative hotspot as the liquid crystals change color with temperature. SEM or FIB. a sample is exposed to an electron beam inside the SEM. the elemental composition of the sample can be determined. photographs should be taken at all cross-section points for documentation. During EDS. Figure 3 is a cross-section of a solder joint.000X and features resolution down to 25 Angstroms. especially when looking for point site defects. Al. to allow for some loss of bond strength with time and thermal exposure.3.3 Thermal imagining of die Quite often. To gauge the proper bond pull strength. The vacated positions are filled by higher energy electrons that emit X-rays in the process. the depth of field is usually very small and only features in a single plane can be examined. or the cross-section can commence at one end of the sample and then progressively continue up to and through the failure site.1 discusses additional wire bond issues. as discussed below. 3. Figure 4 presents a SEM photo of a FET gate metallization structure. While high power microscopes can reach 1000 X. as well as metallurgical failure analysis. Section 5. A non-destructive pull test (NDPT) can be performed first (refer to Mil-Std-883 Method 2023) followed by an electrical retest of the part (if necessary).3. This progressive cross-sectioning can provide a “3D” view of the failure site. Prior to cross-sectioning. solder joint. These hot spots can be associated with shorts or circuits that are otherwise operating hotter than expected. Solder Joint Cross-Section 3. For thermo-compression or thermosonic ball bonds. Once the hot spot is located. If a high resistance bond is still suspected.4 Wire Bond Pull Test (NDPT and DPT) As part of the invasive Failure analysis examination.) and diameter of the wire. etc.3. 3. the sample is usually potted in a hard setting acrylic or polyester rosin. the failed item is literary cut in a cross-sectioned fashion then highly polished to allow detailed microscopic examinations to 5 – Willing. Wire bond pull strength depends on the type (Au. resistor transformer. substrate. EDS 2012 AR&MS Tutorial Notes .7 EDS/EDX Energy dispersive X-ray analysis. any bond pull failure where the entire ball bonds lifts off of the pad should be examined in more detail. with typical magnifications of 50. a destructive bond pull test (DPT) should be performed (refer to Mil-Std-883 Method 2011). Cross-sectioning of semiconductor die can also be performed using a Focused Ion Beam (FIB). Both techniques require the die to be biased. the “post-seal” bond strength requirements of Method 2011 should be considered (~ 80% of initial pull strength).5 Cross Sectioning Cross-Sectioning is a very important means of failure analysis. The materials can be identified by the different energy level spectra unique to each material’s valence bands.9 Auger Electron Spectroscopy (AES) Auger (“O-J”) analysis is a technique where samples are exposed to an electron beam designed to dislodge secondary electrons (otherwise known as Auger electrons) from the materials being examined. if necessary. By ion milling deeper into the sample. SEM photo of a FET gate metallization structure 3. a Platinum ion beam can be used to actually deposit metallization and create new circuit traces. In this case.10 Fourier Transform Infrared Spectroscopy (FTIR) Fourier Transform Infrared Spectroscopy is an analytical technique used primarily to identify organic materials. it is usually useful to 1um deep. These secondary ions can range down to sub-parts-per-million trace levels . Tungsten ion beams may also be used. such as Time-of-Flight SIMS (TOF-SIMS) and Dynamic SIMS (D-SIMS). The FIB cross sections are very “polished” revealing features at 100 Angstrom resolution. Figure 5. Secondary ions formed during sputtering are analyzed with a mass spectrometer. provide additional means of elemental detection and resolution. or ESD damage sites. is an elemental technique that provides little compound information. The FIB can also be used to cut semiconductor metallization lines to isolate circuitry on the die and.is a powerful tool for microanalysis of elemental constituents .3. SIMS is a technique that can detect very low concentrations of dopants and impurities. die level design changes (known as “Device Editing”) can be implemented to allow for a design “try-out”. Fleisher & Cascio – 6 . SIMS works by sputtering the sample surface with a beam of primary ions.3. SIMS can provide elemental depth profiles over a depth range from a few angstroms to tens of microns. Auger detection systems are useful for detecting organic materials on the surface of the die since Auger is more sensitive to lighter elements than EDS. Advanced SIMS analyses. The 2012 Annual RELIABILITY and MAINTAINABILITY Symposium Willing.g. like EDS. 3. The FIB cross-sections can be examined by Scanning Electron Microscope (SEM) to see features such as die metallization construction. Auger profile of contamination on the surface of a wire bond pad.8 Focused Ion Beam (FIB) The Focused Ion Beam is a tool where an ion beam (typically a Gallium Liquid Metal Ion Source (LMIS)) is used to microscopically mil or ablate (e. ion milling) material away to allow for cross-sectioning of semiconductor die. FIB cross-section of a FET gate structure (see cut-out site in Figure 4) Figure 6. any EOS. Auger.3. 3. Figure 4. While some depth profiling can occur. pinhole in dielectrics (oxides/nitrides). but is most useful because it analyzes only the near surface region (~50 Angstroms analysis depth). such as solder flux contamination associated with a part failure. Figure 5 presents a FIB cross-section of a FET gate structure (see cut-out site in Figure 4). Figure 6 presents a Auger profile of the contamination on the surface of a wire bond pad. Hybrid. Fleisher & Cascio • Power Supplies / Signal generator • Oscilloscope Moderately Equipped Failure Analysis lab • SEM • Curve Tracer • Metallurgical Microscope (1000X) (Preferably with digital camera) • Chemical hood with decapsulating chemicals • Die Probe Station • Liquid Chrystal • Film X-ray Advanced Failure Analysis lab • Real Time X-ray • SEM/EDS • FIB • Auger Analysis System • RF Test Equipment (If necessary) 5. with guidelines to help choose the most effective corrective action. and an Integrated Circuit IC). the fingerprint itself is not like a typical spectrum with known peaks for each element.3. However. When running an FTIR analysis. Beyond these three levels. Basic. S/TEM requires significantly more sample preparation as samples need to be very thin. one might consider using commercial failure analysis laboratories for the more esoteric capabilities such as TEM.3. and generate images that highlight elemental contrast (dark field mode)—all from nm sized areas that can be precisely located . 3. thereby allowing for image resolutions on the order of 1 . SUGGESTIONS FOR YOUR OWN FAILURE ANALYSIS CAPABILITIES This section provides some suggestions for establishing Failure Analysis capabilities for a typical electronics firm. along with semiconductors and ICs. STEM or SIMS. examples of failures specific to each part type are reviewed.FTIR reveals infrared absorption spectra that provides information about the chemical bonds and molecular structure of a material. including resistors and capacitors. JEDEC and ESD Association Std ANSI/ESDA/JEDEC JS-001-2010). Basic Failure Analysis Lab • Basic Meters (DVMMs) • Stereo Microscope (10X to 30X) (Preferably with digital camera) • Cross Sectioning Equipment 7 – Willing. Figure 7. produce elemental maps (using EDS). Three levels of Failure Analysis capabilities are suggested. Moderate and Advanced. crystallographic orientation (both by diffraction mode experiments). S/TEM provides outstanding image resolution making it is possible to characterize crystallographic phase. most FTIR equipment requires a fairly large sample of the material in question. establishing their capabilities in-house. There are five subjects covered: • Interconnects • Semiconductor elements • Passive elements • Substrates • Packages. UNDERSTANDING ELECTRONIC PART FAILURE MECHANISMS  Excerpts from the 1997 Alan O. however. which is often not available with typical failures . a Transistor. S/TEM has better spatial resolution then a standard SEM and is capable of additional analytical measurements. Typical Transistor. created by using FIB techniques. Usually it is more cost effective to subcontract out those types of analyses vs. it is advisable to subject a known good part to ESD testing and compare the results to the failed device in question (Reference Mil-Std-883 Method 3015. 4. it helps to compare FTIR spectrums to known samples as it can be difficult to determine the exact components of the material just from the spectra itself.11 TEM (transmission electron microscopy STEM (scanning transmission electron microscopy) Transmission Electron Microscopy (TEM) and Scanning Transmission Electron Microscopy (STEM) use a high energy electron beam to image through an ultra-thin sample. Figure 7 illustrates three common part styles. Cataloged FTIR spectra exist to help identify the materials. The Hybrid contains multiple devices.12 ESD Testing If a part is suspected to be damaged by Electrostatic Discharge (ESD). Hybrid and IC In this section.2 Angstroms. Unfortunately. 2012 AR&MS Tutorial Notes . 3. The FTIR spectrum is like a "fingerprint" of the material. FTIR samples of the materials most suspect to be the culprit are often taken and then compared to the contamination sample’s FTIR “fingerprint”. Plait Award for Tutorial Excellence This section describes failure mechanisms commonly encountered with electronic parts. 1 Wire Bonding Wire bonding in microelectronics is generally performed in one of two ways. highly resistive bond that will eventually fail. Die attach serves three basic functions in a part. a thermal path. Various active and passive elements are bonded to a substrate that is then soldered to a package. Corrosion of indium solder joints. Soldering is used both to physically attach circuit elements to substrates or package headers and to physically attach substrates to package headers. will also be discussed in this section. In thermo-sonic wire bonding. Depending on the severity of the voiding and the power dissipation in the die. provides an electrical connection for the circuit.1. Contamination can greatly increase the formation of Kirkendall voids in a bimetallic system. a die attachment process problem. incomplete oxide removal. Incorrect bond placement on a bonding pad can result in shorts to nearby metallization tracks.1. usually gold and aluminum. Willing. wire dress. Indium and gold solder joints also form extremely brittle intermetallics when exposed to temperatures above 70 to 80C. Contamination by foreign substances. The optimum die attach would have 100% of the die's underside in contact with the header or substrate. Voiding in the substrate attach solder is a major concern. used for their ductile property. The bonding temperature is important in the thermo-sonic bonding. Therefore. Substrate attach using solder is similar to die attach with solder. bonding temperature. Fleisher & Cascio – 8 2012 Annual RELIABILITY and MAINTAINABILITY Symposium . Epoxy serves the same basic function as solder. Insufficient stress relief can cause wires to break or lift off of the bond pad during thermal excursions. aluminum wire is generally used. and in some cases. It also provides a thermal path for heat dissipation. due to either surface irregularities (die. to attach circuit elements to substrates or headers. In ultrasonic bonding. the attachment of circuit elements to a package header or substrate using a eutectic material system.2 Soldering Soldering is used in microelectronic parts to attach circuit elements to a substrate or a package header and substrates to package headers. it is important to assemble the device in a dry environment and ensure it is contained in a hermetically sealed package. In extreme cases. This can also result from using a too large diameter wire for the bonding target. The capillary is then raised and moved to the next bonding site where temperature and pressure form another bond (called a stitch bond). the force and ultrasonic energy applied by the wire bonding machine capillary. Wire bonding is used to electrically connect circuit elements to substrates. fine gold wire (typically 1 mill diameter) is used on a heated stage (~ 150C). Bondability refers to the ability of the two bonding surfaces to form a good bond. 5. bonding energy.5. The reliability of a wire bond using any of these methods is affected by bond placement. and any dissimilar metals used. can occur when subjected to high humidity environments. or incomplete nitride removal all affect bondability. incomplete photoresist removal. This is called a ball-bond. Substrate attach affords the substrate the same benefits that die attach affords the die in that it provides the substrate with physical attachment. it physically attaches the circuit elements to a substrate or header. The most common eutectic attachment system used in microelectronics is the gold/silicon system. This may result in the inability to form a bond or in a weak. 5. The eutectic composition of a material system (if there is one) is the composition of elements that give the lowest melting temperature.1 Interconnects Interconnects within components connect circuit elements and substrates to each other and to the device package. and in many cases. A ball is formed at the end of the wire via an electronic arc (older machines used a hydrogen gas flame) and the ball is bonded to the contact bond pad by the heat of the stage. the die may fail from overheating. There is no heated stage used in this process and the pressure of the wire bonding machine on the wire is incidental. too much pressure can deform the ball and cause damage to the bond pad. Wire dress refers to how wire bonds are routed and to the amount of stress relief used in the wire. In reality. Most of the energy is supplied by high-frequency acoustical movement of the wire against the bonding area. an electrical path. This energy is sufficient to break through the oxides surrounding the wire or bonding surface. thermo-sonic ball and stitch bonding or ultrasonic wedge bonding. Excessive stress relief can allow a wire bond to short to the lid of the package. or contamination. to package pins. poor die attach can result in an electrically open condition and the die breaking free of the header or substrate (refer to Figure 8). it provides a thermal path for heat dissipation. voiding at the intermetallic sites (Kirkendall voiding) can cause high electrical resistance and low mechanical strength. can also be a source of failures. Improper routing can cause wire bonds to short to other wire bonds or to conductors in a package. a weak bond may result. While the formation of gold/aluminum intermetallics are necessary to form a metallurgical bond between the two metals. substrate). The use of dissimilar metals. In thermo-sonic wire bonding. The voids interrupt the thermal path used to remove the heat from the die. excessive bonding energy (ultrasonic) can result in an unacceptable thinning of the wire at the heel or in microcracking in the underlying silicon. the die attach usually contains some voiding. Eutectic bonding. Insufficient bonding energy can cause weak bonds with all technologies. soldering also serves to establish an electrical connection. bondability of the surface. In ultrasonic wire bonding. The wire is cut instead of being flamed off. In many cases. If the bonding temperature is too low. This could lead to a break in the wire at the heel or a chipout at the bond pad. Bonding energy is the amount of energy used to form the bond. and to other circuit elements within a package. which melts at about 370°C. Conductive epoxy is used in place of nonconductive epoxy when an electrical connection is also needed. misalignment. A change in the vertical direction is called a step. however. Stress voiding is a relatively new Figure 8. Thinning in the metallization (usually aluminum) over a step is allowed to reduce to 50% of the metal thickness over a flat area. Conductive epoxy is selected when an electrical connection is also required. for example. Corrosion can occur due to the introduction of contaminants during processing or due to moisture penetrating into the cavity of a non-hermetic package.2. The advantages of using epoxy include ease of application. corrosion. electromigration. Electromigration is caused by a thermal activation of aluminum ions that are physically moved by momentum exchange with flowing electrons. both conductive (usually silver filled) and nonconductive. Poor Die Attachment 5. Corrosion of aluminum metallization is another failure mechanism. Adhesive ionic contaminant issues can be mitigated by selecting epoxies that meet Mil-Std-883 Method 5011 requirements. It can then be transported under the influence of an electric field in the package and cause shorting to adjacent metallization tracks or components. Mil-Prf-38535. can allow localized areas of current constriction to occur. The silver from the epoxy is corroded by the moisture and by other substances in the epoxy. and reworkability. Semiconductor element failures can be broken down into the three categories of metallization failures. This is especially true in hybrid microcircuits. Failures in the form of opens can result from this defect. specifies that the current density for glassivated aluminum metallization shall not exceed 5x105 A/cm2 for case operating temperatures up to 125°C. Electrolytic corrosion can occur in silver filled conductive epoxy when sufficient moisture is present in a package. This is of particular concern when Metal Oxide Semiconductor (MOS) devices are present. Improperly cured epoxy can outgas inside a hermetic package after it has been sealed. Metallization failures generally result in electrical opens. Corrosion can also occur if moisture is inadvertently sealed in a hermetic package. these ionic contaminants may shift the electrical parameters of electronic devices in the package. Epoxies do. releasing moisture and ionic contaminants into the internal cavity of the package. Aluminum bond pads are especially susceptible because they are not passivated. although shorts may also be experienced. oxide failures. open circuits can result. Fleisher & Cascio 2012 AR&MS Tutorial Notes . 5. It can also be affected by factors such as temperature and humidity. Step coverage on a semiconductor element refers to the thickness of a material deposited on an area with an uneven topography. design rules preclude this current density from being exceeded. Usually.3 Epoxy Epoxy can be used instead of solder in many microelectronic part assembly processes. Modern IC’s have multilayer planarized metallization which eliminates many of the step issues. discrete transistors. and stress voiding. such as poor step coverage or voiding. display several failure mechanisms.1 Metallization Metallization on a semiconductor element is a thin film pattern of metal deposited on a chip to connect electronic components contained on the chip or to establish contacts that may be connected externally. Misapplication of a device in a circuit can also lead to excessive current densities.2 Semiconductor Elements Semiconductor elements include discrete diodes. which are exposed to a large number of assembly steps. Epoxies. conductive epoxy may not be the best choice as earlier formulations exhibited changes in the electrical resistance over time. mechanical damage. Mechanical damage to metallization can result in shorts or opens. and integrated circuits. Defects in the metallization. step coverage. and failures induced by overstress. Poor adhesion of an epoxy to either the die or the substrate is another failure mechanism for epoxy. Electromigration failures are a function of the current density in an aluminum conductor and its temperature. Electromigration of metal results in an open circuit condition.under humid or dry conditions. can be applied to accomplish die attach and/or substrate attach and have become more popular as the quality of micro-electronic grade epoxies has improved.1. Because of their inherent charge. This type of failure is usually caused by improper cleaning or abrading of either joining surface. 9 – Willing. The semiconductor elements can be packaged individually or grouped together in a hybrid configuration. Mechanical damage to metallization can be introduced during probing or handling. 5. Misaligned metallization on an integrated circuit can result in poor contact to active circuit elements or to other metallization levels. If stable electrical resistance of the attachment is critical to circuit performance. If step coverage is poor (less than 50%). This type of defect is caused by poorly aligned masks during fabrication. low temperature curing. Metallization failures can be divided into the following specific categories. There are design criteria that are used to limit this phenomenon. oxide defects. If the crack extends between plates of opposite polarity. They are more troublesome in small geometry devices (found it VLSI devices). Severely thinned oxides can also reduce dielectric strength and cause breakdown. The thermal shock associated with the soldering of the capacitors can cause the ceramic to crack.3 volts. etc. Generally. Unique VLSI processing techniques can leave subtly damaged oxide which may result in more trapped charges. or a combination of the two (power). Another failure mechanism caused by ion migration in oxide is time dependent dielectric breakdown.failure mechanism that has been identified. the misapplication of a device in a circuit. One of the most challenging aspects of failure analysis can be to determine whether a device failed from an internal defect or an external overstress. Sources of static for ESD include work surfaces. the device's dielectric breakdown voltage will drop off and the device will short when voltage is applied to it. Thin film resistors are fabricated utilizing thin film technology. Physical defects in an oxide can cause failure. can migrate in the oxide and cause degraded device operation or failure. processing. One of the most common failure modes for ceramic capacitors occurs during their soldering to substrates or boards. Their typical failure mode involves cracked connections. Failure mechanisms include poor adhesion and EOS. They generally have two sets of interleaved plating to increase the area of the plates and thereby increase their capacitance. In this case. The damage that results from EOS can range from the leakage of a single gate in a Very Large Scale Integration (VLSI) device to the fusing of a discrete power transistor. and the particular metallization system used.2. It can be modeled as a capacitor discharging through a resistor. Hot carrier electrons can cause failures in integrated circuits. stressing the oxide with the appropriate voltage can screen out such devices. semiconductor material. Many times ESD damage is very subtle.3. and it is not as easily screened out.3.2 Resistors The term thick film resistor refers to the way the resistor was fabricated. Void formation is highly dependent on device geometry. particularly in the thin gate oxides of MOS devices. Resistors can be produced by both thick film and thin film technologies. the ions are emitted into the oxide from a gate metal during the operation of the device. Barrier metals must be used on end caps so that solder leaching will not occur. Overstresses can be divided into two basic groups: electrical overstress (EOS) and electrostatic discharge (ESD). if they should occur. Ceramic capacitors are probably the most common style of capacitor used. However. particularly in MOS devices. plastic bags. resulting in device failure. or the external application of excessive power to a device. 5. Voids form in the aluminum metallization on an integrated circuit due to a tensile stress that is exerted on it by the passivation. Failure modes Willing. The ESD event itself is a transient phenomenon. The voids tend to occur at aluminum grain boundaries. There are many different types of capacitors to choose from. which are highly mobile in oxide. The control of ESD is now itself an industry that supports electronics manufacturers. Tantalum capacitors use tantalum pentoxide as a dielectric. Hot carrier electrons are very energetic electrons which can affect the oxide by forming trapped charge regions. semiconductor elements exposed to sufficiently high levels of ESD will experience varying degrees of damage. Generally these “Mobile Ion” failure mechanisms have been eliminated from semiconductor processing. Thin film technology refers to the deposition of a material (usually less than 5 microns in thickness) onto a substrate by vacuum deposition or sputtering. 5. Ionic impurities can contaminate the oxide/nitride and affect device operation. usually about 200 nanoseconds when the source is a human body. when affected by an electrical bias. An EOS failure can be caused by the failure of another device in a circuit. This is because the ESD event is very short in duration. Sodium ions. Electrical overstress is one of the most common causes of failure for an electronic device. Fleisher & Cascio – 10 2012 Annual RELIABILITY and MAINTAINABILITY Symposium . Again. End caps are added to join the two sets of plates.3 Oxides / Nitrides Oxides (silicon dioxide) and Nitrides (silicon nitride) serve to provide an insulating barrier between conductors or between semiconductors and conductors. It can be a continuous event or it can be transient in nature. These ions. where geometries are shrunk but operating voltages (usually + 3.2. degraded performance or failure can result. down to +1. Thick film resistors are widely used in hybrids.2 Overstress Overstress refers to the application of voltage or current. to a device that exceeds its capabilities. Pin holes in the oxide can reduce its dielectric strength and result in breakdown. tantalum is usually the choice. There are three oxide/nitride failure mechanisms that will be discussed here: ionic impurities. Electrostatic discharge is the transfer of charge between two bodies that are at different potentials. oxide. 5. and the human body. Irreversible damage can result in the metallization. Semiconductor elements are sensitive to ESD. were a common impurity found in early semiconductor processes.3 Passive Elements Passive elements used in microelectronics include resistors and capacitors.1 Capacitors Ceramic capacitors are named for their ceramic dielectric material. They are also used as a passivation layer to protect the underlying structures. When a large amount of capacitance is required in a small volume. 5.0 volts) are held constant. Oxides can be deposited on a silicon chip or can be thermally grown. Thick film technology is a field of microelectronics in which special pastes are silk-screened onto a ceramic substrate and then fired at high temperature to bond the films to the substrate. and hot carrier effects. 5. The initial trouble shooting quickly isolated the problem to the multiplexer. EOS. Radiographic examination can then be used to verify the size and density of the particle before the device is delidded. The failure was caused by corrosion within the package.2 Insulation Resistance Insulation resistance between package pins and leads must be maintained for a device to function properly.4. The next step was performing real-time X-ray. Hermetic seals require the use of some combination of 11 – Willing. Nonhermetic packages (plastic packages) allow outside air to penetrate the package. A crack in a substrate can also propagate through an attached component (a die. save space inside a package and reduce its weight. It passed the fine and gross leak check.2 Metallization Metallization failures. glass. 5. Incomplete via fills (a via is an internal connection between two metallization layers) occur during substrate fabrication and result in open circuits. Fleisher & Cascio metal. The microcircuit used a standard high reliability package design consisting of a ceramic housing with a hermetic seal. the anomalous behavior was seen only during electrical testing below 0°C. The failure of a package to protect its internal components from the external environment can result in device failure. which were shown to occur on semiconductor die. refer to figure 9. 5. Cracks in a substrate can be caused by a thermal coefficient of expansion mismatch between a substrate and a package header. ESD due to their thin film nature. A fine leak is defined as a leak rate that is greater than 1 x 107 atm cc/sec (however this rate does depend on the package volume). 5. usually detectable by looking for bubbles from a package while immersed in a hot fluorocarbon.1 Hermeticity Microelectronics packages are either hermetic or nonhermetic. Hermetic packages effectively seal the internal components from the external atmosphere. Substrates. They also allow for electrical connection to other packages in an electrical system. The part was photographed and leak checked as a normal course of action.include poor adhesion.5. to mount circuit elements onto and to make electrical interconnections. particularly when manufacturing hybrids. Devices that fail hermeticity are referred to as fine leakers or gross leakers. At the time. 5. refer to figure 10. Lifting of the metallization from the substrate can occur. for example) causing the component to fail. 6.5. typically formed out of a ceramic material. with two additions.4 Substrates Substrates are used in microelectronics. Shorts between metallization layers also happen during substrate fabrication. Leaching of lead from the glass sealing material has historically caused insulation resistance failures. The inspection revealed signification corrosion. 5. usually resulting from an improperly cleaned substrate prior to metallization application. After exhibiting similar anomalous behavior it was delidded for internal inspection. and. 6. 2012 AR&MS Tutorial Notes . It was not until integration at a higher level assembly that an anomaly arose.5. the multiplexer was exposed to multiple temperature performance and environmental screening tests at the component and board level assembly. 5. This example presents the types of problems that are encountered and how proper failure analysis can help implement effective corrective action. A gross leak is any leak rate greater than 1 x 10-5 atm cc/sec. Leaching of gold metallization into solders can also occur if the proper barrier metals are not used. Poor metallization coverage is also a failure mechanism. or failures caused by loose particles within the package.3 Loose Particles Loose particles inside a package can cause a failure.3 Multilayer Substrates Multilayer substrates (substrates with two or more levels of metallization) suffer from the same failure mechanisms as single layer substrates.4. 5. This is especially true if the particles are conductive. it was removed for further investigation. cracking. which observed a possible open circuit. Moisture can lead to many forms of corrosion inside a package and is one of the most important contaminants to seal out. also occur on substrates. and/or ceramic in the package seal. Particle Impact Noise Detection (PIND) testing is used to detect loose particles inside a package. Substrates can fail from several different mechanisms as discussed below. Package failures can be classified as hermeticity failures. Prior to the failure. They can also be introduced by mechanical damage. insulation resistance failures. FAILURE ANALYSIS CASE STUDY This section discusses the failure analysis performed on a hermetically packaged integrated circuit (multiplexer). After careful assessment of the part as installed on the board. The part was then retested electrically at low temperature to demonstrate the issue was reproducible at the component level.4. Contamination on the exterior of a package can cause the insulation resistance to fail.1 Cracking Cracking in a substrate can cause a failure if the substrate crack propagates through a metallization stripe. A loose conductive particle in a package can cause a failure by creating a short between other conductors inside the package.5 Packages Packages physically protect circuit elements from the external environment.1 Mux Failure Analysis A multiplexer Integrated Circuit (Mux IC) failure was first discovered during a system level electrical test. 5. Fleisher & Cascio – 12 . The records showed the lot of devices passed qualification. Robert Pearson.com/ Evans Analytical Group. http://www. Tutorial Notes.e. CONCLUSIONS Figure 9.eaglabs.. Moisture can react with residual plating salts and cause significant corrosion between interconnecting joints especially in presence of an electrical field. 4. Richard Brooks. Figure 10. <5.eaglabs. 8. “Understanding Electronic Part Failure Mechanisms”. 15 November 2010 Mil-Prf-38535J. Given the overall findings and positive on site review. 7.eaglabs. They all passed the RGA tests as well as the inspection. the vendor was contacted and an on-site review was conducted. The interconnect was degraded to the point of being intermittent over temperature. 5. notably. Multiplexer IC After Lid Removal revealing corrosion on Pin 13 Military-Standard packages require Residual Gas Analysis Test (RGA) as a qualification for low moisture content (i. “Test Method Standard Microcircuits” 26 February 2010 Mil-Std-1580B. “Integrated Circuits (Microcircuits) Manufacturing.2 Military Standards Mil-Std-883H. REFERENCES Evans Analytical Group. http://www. “Destructive Physical Analysis For Electronic. John.eaglabs. 6. High moisture content is commonly due to an inadequate bake out and sealing process though other possibilities exist. In addition. http://www.Component Level” 8. The cause of corrosion is typically due to moisture trapped in packages prior to seal.2 Corrective action Given that the device was advertised as space grade high reliability.com/ Evans Analytical Group.com/ Evans Analytical Group. http://www. 1998 Annual Reliability and Maintainability Symposium. it indicates the moisture was trapped in the device prior to seal. Electromagnetic.1 Industry Standards ANSI/ESDA/JEDEC JS-001-2010. 6. W. Randall Lewis and Ronald Twist. 2. five devices from the same lot were checked for moisture via the RGA test procedure and then delidded for inspection. 2012 Annual RELIABILITY and MAINTAINABILITY Symposium Willing.eaglabs.com/ Evans Analytical Group. The authors would like to acknowledge all of the past and present Failure Analysis Engineers at Northrop Grumman Electronic systems for their contributions to this tutorial. the rest of the lot was ultimately exonerated and the failure was classified as an isolated issue. Since the device passed leak testing prior to lid removal. 3. Real-time X-ray of Multiplexer IC Revealed Possible Corrosion It is the goal of this tutorial that the audience has gained a good understanding of the failure analysis process and the tools and techniques available for performing failure analysis on electronic components. And Electromechanical Parts”. 8. (Jan) 1998. 28 December 2010 1. The authors hope this goal has been achieved. John Knepley. General Specification For”.000 ppmv).The corrosion primarily attacked the wire bond for Vcc which brings in external DC power. http://www. “Electrostatic Discharge Sensitivity Testing Human Body Model (HBM) .com/ Knepley.