Chapter 30 manufacturing

PROCESSING OFINTEGRATED CIRCUITS 1. 2. 3. 4. 5. 6. 7. Overview of IC Processing Silicon Processing Lithography Layer Processes Use in IC Fabrication Integrating the Fabrication Steps IC Packaging Yields in IC Processing ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e Integrated Circuit (IC)  A collection of electronic devices such as transistors, diodes, and resistors that have been fabricated and electrically intraconnected onto a small flat chip of semiconductor material  Silicon (Si) - most widely used semiconductor material for ICs  Less common: germanium (Ge) and gallium arsenide (GaAs) ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e Levels of Integration in Microelectronics Integration level Number devices Small scale integration (SSI) 10 ‑ 50 Medium scale integration (MSI) 50 ‑ 103 Large scale integration (LSI) 103 ‑ 104 Very large scale integration (VLSI) 104 ‑ 106 Ultra large scale integration (ULSI) 106 ‑ 108 Giga scale integration (GSI) 109 - 1010 Approx. year 1959 1960s 1970s 1980s 1990s 2000s ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e HISTORY OF INTEGRATED CIRCUITS ● ● ● ● Development of radar immediately before WWII (1939 – 1945) Transistor development Invention of the Integrated Circuit (IC) Commercial development if ICs ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e millions or billions of microscopic electronic devices  A chip is a square or rectangular flat plate that is about 0.2 to 1.5 mm (0. Inc. M P Groover.0 in) on a side  Each electronic device on the chip surface consists of separate layers and regions with different electrical properties combined to perform a particular function ©2013 John Wiley & Sons.Overview of IC Technology  An integrated circuit chip consists of hundreds.020 in) thick and typically 5 to 25 mm (0. Principles of Modern Manufacturing 5/e . thousand. IC Transistor  Cross section of a transistor in an integrated circuit feature sizes can be less than 40 nm ©2013 John Wiley & Sons. M P Groover. Inc. Principles of Modern Manufacturing 5/e . Principles of Modern Manufacturing 5/e .Integrated Circuit  Highly magnified image of an integrated circuit (photo courtesy of Intel Corporation) ©2013 John Wiley & Sons. Inc. M P Groover. M P Groover.Packaging of ICs  To connect the IC to the outside world. Inc. and to protect it from damage. Principles of Modern Manufacturing 5/e . the chip is attached to a lead frame and encapsulated inside a suitable package  The package is an enclosure. made of plastic or ceramic. that provides mechanical and environmental protection for the chip  The package includes leads by which the IC can be electrically connected to external circuits ©2013 John Wiley & Sons. Inc. M P Groover. Principles of Modern Manufacturing 5/e .IC Dual In-Line Package (DIP)  (a) Cutaway view showing the chip attached to a lead frame and encapsulated in a plastic enclosure. (b) the package as it would appear to a user ©2013 John Wiley & Sons. alter. Silicon processing . Inc.Processing Sequence for Silicon ICs 1. IC packaging .processing steps that add. IC fabrication . and remove thin layers in selected regions to form electronic devices (planar process)  Lithography is used to define the regions to be processed on wafer surface 3. M P Groover.sand is reduced to very pure silicon and then shaped into wafers 2. and the chips are packaged ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . cut into individual chips.wafer is tested. Sequence in IC Processing  (1) Pure silicon is formed from molten state into ingot and then sliced into wafers. Principles of Modern Manufacturing 5/e . and (3) wafer is cut into chips and packaged ©2013 John Wiley & Sons. M P Groover. Inc. (2) fabrication of integrated circuits on wafer. the scale of which continues to decrease each year ©2013 John Wiley & Sons.Clean Rooms  Much of the processing of ICs must be carried out in a clean room  Ambiance of a clean room is more like a hospital operating room than a production factory  Cleanliness is dictated by the microscopic feature sizes in an IC. Principles of Modern Manufacturing 5/e . M P Groover. Inc. Principles of Modern Manufacturing 5/e . Inc. M P Groover.Trends in IC Feature Size  Also shown is the size of common airborne particles that can contaminate the IC processing environment ©2013 John Wiley & Sons. g. Motorola PowerPC 601 0. Inc. Xeon E3-1230 (Ivy 16 nm (c.g. Intel 80386 800 nm (1989) e.g.g. Pentium II Klamath 250 nm (1998) e. Principles of Modern Manufacturing 5/e . Intel 8088 1.g.g. P5 Pentium 60 MHz 600 nm (1994) e.g. AMD K6-2 180 nm (1999) e.g.g. and comparison of sizes of semiconductor manufacturing process nodes with some microscopic objects and visible light wavelengths (see https://en.g.o rg/wiki/Semiconducto r_device_fabrication) 1 µm (1985) e. Core Duo 45 nm (2008) e. VIA C7 65 nm (2006) e.5 µm (1982) e. PowerPC 7447 90 nm (2002) e. Intel 80286 Progress of miniaturisation. Coppermine E 130 nm (2000) e.g.g. Core i3 (Clarkdale) 22 nm (2011) e.g. Core 2 (Wolfdale) 32 nm (2010) e.g. M P Groover.5 µm 350 nm (1995) e. Intel 8008 Violet light (400 nm wavelength) 3 µm (1975) e.Red light (700 nm wavelength) 10 µm (1971) e.wikipedia.g.2013) 11 nm (c.2015) Staphylococcus aureus bacterium Spermatozoon head Red blood cell cross-section Human immunodeficiency virus (HIV) ©2013 John Wiley & Sons. Silicon Processing    Microelectronic chips are fabricated on a substrate of semiconductor material Silicon accounts for more than 95% of all semiconductor devices produced in the world today Preparation of silicon substrate (wafers) can be divided into three steps: 1. Inc. Production of electronic grade silicon 2. Principles of Modern Manufacturing 5/e . Shaping of Si into wafers ©2013 John Wiley & Sons. Crystal growing 3. M P Groover. g. Inc.g. M P Groover. occurring naturally as silica (e.. Principles of Modern Manufacturing 5/e . sand) and silicates (e. which is very pure SiO2  Electronic grade silicon (EGS) is polycrystalline silicon of ultra high purity  Impurities are measured in parts per billion ©2013 John Wiley & Sons..Electronic Grade Silicon  Silicon is one of the most abundant materials in the earth's crust. clay)  Principal raw material for silicon is quartzite. Principles of Modern Manufacturing 5/e . Inc. M P Groover.Crystal Growing  The silicon substrate for microelectronic chips must be made of a single crystal whose unit cell is oriented in a certain direction  Substrate wafers must be cut in a direction that achieves the desired planar orientation  Most widely used crystal growing method is the Czochralski process  A single crystal boule is pulled from a pool of molten silicon ©2013 John Wiley & Sons. M P Groover. Principles of Modern Manufacturing 5/e . Inc.Czochralski Process  (a) Initial setup and (b) during crystal pulling to form boule ©2013 John Wiley & Sons. Ingot (boule) preparation 2. Wafer slicing 3. Wafer preparation ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . Inc. disc‑shaped wafers 1.Shaping of Silicon into Wafers  Processing steps to reduce the boule into thin. M P Groover. M P Groover. after boule is cut into wafers. Principles of Modern Manufacturing 5/e . Inc.Preparation of the Boule    The ends of the boule are cut off Cylindrical grinding is used to shape the boule into a more perfect cylinder One or more flats are ground along length of boule  Functions. are:  Identification  Orientation of ICs relative to crystal structure  Mechanical location during processing ©2013 John Wiley & Sons. M P Groover.Grinding Operations on Boule  (a) Cylindrical grinding provides diameter and roundness control and (b) a flat ground on the cylinder ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . Inc. M P Groover. Principles of Modern Manufacturing 5/e . greater thicknesses for larger wafer diameters  To minimize kerf loss.7 mm (0. and surface characteristics of the wafer  Wafers are cut  0.028 in.020‑0.Wafer Slicing  Cutting edge is a very thin ring-shaped saw blade with diamond grit on internal diameter  ID used for slicing rather than the OD for better control over flatness.) thick.013 in) ©2013 John Wiley & Sons. blades are very thin: thickness ~ 0.5‑0. thickness. parallelism.30 mm (0. Inc. Principles of Modern Manufacturing 5/e . M P Groover. Inc.Wafer Slicing  Wafer slicing using a diamond abrasive cut‑off saw ©2013 John Wiley & Sons. Inc. M P Groover.Wafer Preparation  Wafer rims are rounded by contour‑grinding wheel to reduce chipping during handling  Wafers are chemically etched to remove surface damage due to slicing  A flat polishing operation is performed to provide surfaces of high smoothness for photolithography processes to follow  Finally. Principles of Modern Manufacturing 5/e . wafer is chemically cleaned to remove residues and organic films ©2013 John Wiley & Sons. or remove layers in selected areas of the wafer surface  Each layer is determined by a geometric pattern representing circuit design information that is transferred to the wafer surface by lithography ©2013 John Wiley & Sons.Lithography  An IC consists of many microscopic regions on the wafer surface that make up the devices and intraconnections as specified in the circuit design  In the planar process. M P Groover. Principles of Modern Manufacturing 5/e . regions are fabricated by steps that add. alter. Inc. Principles of Modern Manufacturing 5/e . M P Groover.Lithographic Technologies  Several lithographic technologies are used in semiconductor processing:  Optical lithography known as Photolithography  Electron-beam lithography  X‑ray lithography  Ion beam lithography  The differences are in type of radiation used to transfer the mask pattern to the wafer surface by exposing the photoresist ©2013 John Wiley & Sons. Inc. M P Groover.Photolithography  Uses light radiation to expose a coating of photoresist on the surface of the wafer  Common light source in wafer processing is ultraviolet light. Inc. Principles of Modern Manufacturing 5/e . due to its short wavelength  A mask containing the required geometric pattern for each layer separates the light source from the wafer. so that only the portions of the photoresist not blocked by the mask are exposed ©2013 John Wiley & Sons. 080 in). while deposited film thickness is only ~ 1 m  The mask itself is fabricated by lithography  The pattern is based on circuit design data. usually the digital output from a CAD system used by circuit designer ©2013 John Wiley & Sons. M P Groover. Inc. Principles of Modern Manufacturing 5/e .Photolithography Mask  Flat plate of transparent glass onto which a thin film of an opaque substance has been deposited in certain areas to form the desired pattern  Thickness of glass plate is around 2 mm (0. Principles of Modern Manufacturing 5/e . M P Groover. Inc.Photoresist  Organic polymer that is sensitive to light radiation in a certain wavelength range  Sensitivity causes either increase or decrease in solubility of the polymer to certain chemicals  Typical practice in semiconductor processing is to use photoresists that are sensitive to UV light because of its shorter wavelength  Also permits fabrication areas in plant to be illuminated at low light levels outside UV band ©2013 John Wiley & Sons. M P Groover. Inc. (c) projection printing ©2013 John Wiley & Sons.Photolithography Exposure Techniques  (a) Contact printing. Principles of Modern Manufacturing 5/e . (b) proximity printing. Inc. Principles of Modern Manufacturing 5/e .Photolithography Processing Sequence  Surface of the silicon wafer has been oxidized to form a thin film of SiO2  It is desired to remove the SiO2 film in certain regions as defined by mask pattern  Sequence for a negative resist proceeds as follows: ©2013 John Wiley & Sons. M P Groover. (6) hard bake. (5) develop resist. (2) apply resist.Photolithography Processing Sequence  (1) Prepare surface. (7) etch. (4) align mask and expose. (3) soft bake. M P Groover. Inc. Principles of Modern Manufacturing 5/e . (8) strip resist ©2013 John Wiley & Sons. (8) strip resist ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . (7) etch.Photolithography Processing Sequence  (1) Prepare surface. (6) hard bake. M P Groover. Inc. (2) apply resist. (5) develop resist. (3) soft bake. (4) align mask and expose. M P Groover. Inc. A partially processed silicon wafer after several lithography steps (courtesy of George E. Kane Manufacturing Technology Laboratory. Principles of Modern Manufacturing 5/e . Lehigh University) ©2013 John Wiley & Sons. other lithography techniques that offer higher resolution are growing in importance  Extreme ultraviolet (EUV) lithography  Electron beam lithography  X‑ray lithography  Ion lithography ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e .Other Lithography Techniques  As feature sizes in integrated circuits continue to decrease and UV photolithography becomes increasingly inadequate. M P Groover. Inc. each layer requiring a separate mask. M P Groover. alter. and conducting areas that form the devices and their intraconnections in the IC  Layers are fabricated one at a time. Principles of Modern Manufacturing 5/e . until all of the details have been fabricated onto the wafer surface ©2013 John Wiley & Sons. Inc. or remove regions defined by photolithography  Regions are insulating. semiconducting.Layer Processes Used in IC Fabrication  Steps to fabricate ICs on a silicon wafer consist of chemical and physical processes that add. Layering Processes that add or alter layers in IC Fabrication  Thermal oxidation – adds SiO2 layer on Si substrate  Chemical vapor deposition - adds various layers  Diffusion and ion implantation - alter chemistry of an existing layer or substrate  Metallization processes - add metal layers for electrical conduction  Etching processes - remove portions of layers to achieve desired IC details ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e Thermal Oxidation of Silicon  Exposure of silicon wafer surface to an oxidizing atmosphere at elevated temperature to form layer of silicon dioxide  Oxygen or steam atmospheres are used, with the following reactions, respectively: Si + O2  SiO2 or Si + 2H2O  SiO2 + 2H2 ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e Thermal Oxidation  Growth of SiO2 film on a silicon substrate by thermal oxidation, showing changes in thickness that occur: (1) before oxidation and (2) after thermal oxidation ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e Functions of Silicon Dioxide  SiO2 is an insulator, compared to Si which is a semiconductor  Used as a mask to prevent diffusion or ion implantation of dopants into silicon  Can be used to isolate devices in circuit  Provides electrical insulation between levels in multi‑level metallization systems ©2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manufacturing 5/e Chemical Vapor Deposition (CVD) – typical reactions in IC fabrication      When a silicon dioxide film must be applied to surfaces other than silicon. M P Groover.5. Principles of Modern Manufacturing 5/e . SiO2. Inc. then direct thermal oxidation does not work An alternative process must be used. Si3N4 (silicon nitride) and various metallization materials Plasma-enhanced CVD is often used because it permits the reactions to take place at lower temperatures ©2013 John Wiley & Sons.2) CVD is widely used in the processing of integrated circuit wafers to add layers of Si. such as chemical vapor deposition (CVD) CVD involves growth of a thin film on the surface of a heated substrate by chemical reactions or decomposition of gases (Section 24. M P Groover.Chemical Vapor Deposition (CVD) – Epitaxial Deposition  Epitaxial Deposition: – is a film growing process where the film has a crystalline structure that is an extension of the substrate's structure.5. – can for example be used to grow a Si film on a Si substrate – Vapor-phase epitaxy: ● is more important in semiconductor processing ● is based on CVD ● – to grow Si on Si. lower temperatures (400°C to 900°C) than CVD ©2013 John Wiley & Sons. Inc.1) ● to grow Si on Si. closely controlled process and at higher temperatures (1200°C) than conventional CVD Molecular-beam epitaxy ● uses a vacuum evaporation process (Section 24. Principles of Modern Manufacturing 5/e . and antimony (Sb) Techniques for doping silicon: 1. Thermal diffusion 2. Principles of Modern Manufacturing 5/e . arsenic (As). Inc. phosphorous (P). Ion implantation ©2013 John Wiley & Sons.adding impurities into Si surface Common doping elements are boron (B).Introduction of Impurities into Silicon    IC technology relies on the ability to alter the electrical properties of silicon by introducing impurities into selected regions of the surface  Called Doping . M P Groover. losing energy and finally stopping at some depth in crystal structure determined by mass of ion and acceleration voltage  Advantages:  Can be accomplished at room temperature  Provides exact doping density  Disadvantage: High energy collisions can damage the crystal lattice structure – solved by annealing  Diffusion (Chapter 4) can also be used for ion implantation ©2013 John Wiley & Sons. Inc. Principles of Modern Manufacturing 5/e . M P Groover.Ion Implantation  Doping: Vaporized ions of impurity element are accelerated by an electric field and directed at silicon substrate  Atoms penetrate into surface. M P Groover. gates) of IC devices  Provide conduction paths between devices on chip  Connect the chip to external circuits ©2013 John Wiley & Sons..g. Principles of Modern Manufacturing 5/e . Inc.Metallization  Combines various thin film deposition technologies with photolithography to form very fine patterns of conductive material  Functions of conductive materials on wafer surface:  Form certain components (e. Principles of Modern Manufacturing 5/e . and nitrides (e. Mo). WSi2. W.g.g. and ZrN)  Applications such as gates and contacts ©2013 John Wiley & Sons. TiN.Metallization Materials 1) Aluminum . silicides (e.. gold (Au).g.most widely used metallization material  Satisfies most of the required properties 2) Other materials: silicon (Si). refractory metals (e.. M P Groover. Inc. TaN. TaSi2). MoSi2.. Principles of Modern Manufacturing 5/e .occasionally used to increase thickness of thin films ©2013 John Wiley & Sons. M P Groover.Metallization Processes 1) Physical Vapor Deposition (PVD) – PVD metallization processes include vacuum evaporation and sputtering 2) Chemical Vapor Deposition (CVD) – less common than PVD 3) Electroplating (Chapter 24) . Inc. Etching 1) Certain steps in IC manufacturing require material removal from surface. Principles of Modern Manufacturing 5/e . by masking areas that are to be protected and leaving other areas exposed 3) Two categories of etching process: a) Wet chemical etching b) Dry plasma etching ©2013 John Wiley & Sons. accomplished by etching away unwanted material 2) Usually done selectively. Inc. M P Groover. usually an acid.Wet Chemical Etching 1) Use of an aqueous solution (solvent is H2O).2) b)Process variables are immersion time. to etch away a target material a)Etchant is selected to chemically attack the specific material and not the protective layer (see Table 30. Principles of Modern Manufacturing 5/e . Inc. etchant concentration. M P Groover. and temperature c) In its simplest form. etching involves immersing the masked wafers for a specified time and then immediately rinsing to stop the etching ©2013 John Wiley & Sons. Inc. M P Groover. etching involves immersing the masked wafers for a specified time and then immediately rinsing to stop the etching c) Process variables are immersion time. to etch away a target material a)Etchant is selected to chemically attack the specific material and not the protective layer (see Table 30. and temperature ©2013 John Wiley & Sons. etchant concentration. usually an acid.Wet Chemical Etching 1) Use of an aqueous solution (solvent is H2O).2) b)In its simplest form. Principles of Modern Manufacturing 5/e . Principles of Modern Manufacturing 5/e . causing an undercut below protective mask 3) Mask pattern (resist) must be sized to compensate ©2013 John Wiley & Sons.Chemical Etching 1) Profile of a properly etched layer shown below 2) Chemical etching reaction is isotropic. M P Groover. Inc. M P Groover.Dry Plasma Etching 1) Uses an ionized gas to etch a target material a) Ionized gas is created by introducing an appropriate gas mixture into vacuum chamber and Radio Frequency (RF) electrical energy is used to ionize a portion of the gas to create a plasma b) The high energy plasma reacts with the target surface. vaporizing material to remove it c) The advantage of plasma etching over wet chemical etching is that it is much more anisotropic. In a fully anisotripic etch. Inc. the undercut below the protective mask is zero ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . M P Groover. Principles of Modern Manufacturing 5/e . ©2013 John Wiley & Sons. 3) The use of lithography to apply a particular process only to selected regions of the surface is illustrated in Fig 30.3 – summary of typical processes used to add or alter a layer of given material type. Inc.Process Integration in IC Fabrication (1 of 2) 1) Dealt with Lithography & Layer Processes – now looking at sequence of IC manufacturing steps 2) Table 30.17. although processes for these IC categories are similar 3) The device to be fabricated is illustrated in Fig 30. M P Groover.Process Integration in IC Fabrication (2 of 2) Process integration in IC fabrication example: 1) An n‑channel metal oxide semiconductor (NMOS) logic device will be used to illustrate processing sequence 2) Sequence for NMOS ICs is less complex than for CMOS or bipolar technologies. Inc.1 and shown on the next slide ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . M P Groover. Inc. Principles of Modern Manufacturing 5/e .N-Channel Metal Oxide Semiconductor (NMOS) ©2013 John Wiley & Sons. which will form the base of n‑channel transistor. Si3N4 mask is deposited by CVD on Si substrate.IC Fabrication Sequence (1 of 2) (1) Starting substrate is a lightly doped p‑type silicon wafer. (4) thin layer of SiO2 is grown by thermal oxidation ©2013 John Wiley & Sons. Inc. (2) SiO2 is grown by thermal oxidation in unmasked regions. M P Groover. Principles of Modern Manufacturing 5/e . (3) Si3N4 mask is stripped. (6) poly-Si is selectively etched using photo-lithography to define gate electrode.1) are formed by doping n+ in substrate. Principles of Modern Manufacturing 5/e . (8) Phosphosilicate glass (P-glass) is deposited onto surface by CVD for protection ©2013 John Wiley & Sons.IC Fabrication Sequence (2 of 2)  (5) Polysilicon is deposited by CVD and doped n type (n+) using ion implantation. M P Groover. (7) source and drain regions (see Fig 30. Inc. Principles of Modern Manufacturing 5/e .IC Packaging 1) Final series of operations to transform the wafer into individual IC chips a)Ready to connect to the external circuits b)Prepared to withstand the harsh environment of the world outside the clean room 2) Accomplished after all of the processing steps on the wafer have been completed ©2013 John Wiley & Sons. M P Groover. Inc. Design Issues in IC Packaging 1) Electrical connections to external circuits 2) Materials to encase chip and protect it from the environment a)Humidity and corrosion b)Temperature c) Vibration and mechanical shock 3) Heat dissipation 4) Performance. reliability. Inc. and service life 5) Cost ©2013 John Wiley & Sons. M P Groover. Principles of Modern Manufacturing 5/e . M P Groover. ©2013 John Wiley & Sons. Inc.Manufacturing Issues in IC Packaging 1) Chip separation ‑ cutting wafer into individual chips 2) Connecting it to the package 3) Encapsulating the chip 4) Circuit testing Most of the design issues are addressed in other texts. some engineering aspects of IC packages (a. Principles of Modern Manufacturing 5/e . chip carriers) and the types of packages are discussed.a.k. before describing the processing steps to make them. IC Package Design 1) Three of the factors related to the design of an integrated circuit package: a)Number of input/output terminals required for an IC of a given size b)Materials used in IC packages c) Package styles ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . M P Groover. Inc. Principles of Modern Manufacturing 5/e . M P Groover. Inc. the required number of I/O terminals also increases a) Rent’s Rule: nio = Cnicm b) The parameters C & m depend on the type of circuit and the design of the IC 3) The problem is aggravated by IC trends: a) Decreases in device size b) Increases in number of devices in IC ©2013 John Wiley & Sons.Determining the number of Input/Output (I/O) Terminals 1) Problem is to connect many internal circuits on the chip to I/O terminals so that the appropriate electrical signals can be communicated to the outside world 2) As the number of devices in the IC increases. mounted on heat spreader.org/wiki/Die_%28integrated_circuit%29 ©2013 John Wiley & Sons. Inc.900.000. Die is 22×23mm (506 mm2). M P Groover. Principles of Modern Manufacturing 5/e .000 transistors See https://en.Determining the number of Input/Output (I/O) Terminals Intel Xeon E7440 die.wikipedia. and contains 1. Principles of Modern Manufacturing 5/e . polyimides. Inc. M P Groover. and silicones) a)Not hermetically sealed. where very high reliability is not required ©2013 John Wiley & Sons.IC Package Materials 1) Ceramic (Alumina / aluminium oxide: Al2O3) a)Advantages: hermetic sealing of IC chip and highly complex packages can be produced b)Disadvantage: poor dimensional control due to shrinkage during firing 2) Plastic (epoxies. but cost is lower b)Generally used for mass produced ICs. and silicones) a)Not hermetically sealed. M P Groover. but cost is lower b)Generally used for mass produced ICs. polyimides. Principles of Modern Manufacturing 5/e .IC Package Materials 1) Ceramic (Alumina / aluminium oxide: Al2O3) a)Advantages: hermetic sealing of IC chip and highly complex packages can be produced b)Disadvantage: poor dimensional control due to shrinkage during firing 2) Plastic (epoxies. where very high reliability is not required ©2013 John Wiley & Sons. Inc. M P Groover. Through‑hole mounting.Two Basic Types of IC Package 1. Inc. Principles of Modern Manufacturing 5/e . also called pin‑in‑hole (PIH) technology a) IC package and other components have leads inserted through holes in PCB and soldered on underside 2. both top and bottom surfaces) ©2013 John Wiley & Sons. Surface mount technology (SMT) a) Components are attached to surface of board (in some cases. and (d) gull‑wing ©2013 John Wiley & Sons. M P Groover. and several styles of surface mount technology: (b) butt lead. (c) "J" lead. Principles of Modern Manufacturing 5/e . Inc.Two Basic Types of IC Package  Types of component lead attachment on a printed circuit board: (a) through‑hole. Principles of Modern Manufacturing 5/e . M P Groover.Major IC Package Styles 1) Dual in‑line package (DIP) 2) Square package 3) Pin grid array 4) Some of these are available in both through‑hole and surface mount styles. while others are designed for only one mounting method ©2013 John Wiley & Sons. Inc. Principles of Modern Manufacturing 5/e . M P Groover. Inc. shown here in through‑hole configuration and (b) square leaded chip carrier (LCC) for surface mounting with gull wing leads (a) (b) ©2013 John Wiley & Sons.Dual In-Line Package (DIP)  (a) Dual in‑line package with 16 terminals. center area of package has no pins because this region contains the IC chip ©2013 John Wiley & Sons. entire bottom surface of package is fully occupied by pins. However. M P Groover.Pin Grid Array (PGA) 1) Two dimensional array of pin terminals on underside of a square chip enclosure a)Square matrix maximizes number of leads on package b)Ideally. Inc. so pin count in each direction is square root of nio i. Principles of Modern Manufacturing 5/e . Pin Grid Array (PGA) chip carrier See https://en. M P Groover. Inc.wikipedia. Principles of Modern Manufacturing 5/e .org/wiki/Die_%28integrated_circuit%29 ©2013 John Wiley & Sons. M P Groover. Inc. Principles of Modern Manufacturing 5/e .Processing Steps in IC Packaging 1) Wafer testing 2) Chip separation 3) Die bonding 4) Wire bonding 5) Package sealing 6) Final testing ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e . Chips that fail are marked with an ink dot and are not packaged ©2013 John Wiley & Sons. Inc. tests indicate short circuits and other faults.Wafer Testing 1) Testing (called multiprobe) is accomplished by computer‑controlled equipment using needle probes that match connecting pads on the chip surface a)These tests are performed while IC chips are still on the wafer ‑ before separation b)As probes contact pads. followed by a functional test i. M P Groover. Adhesive tape holds individual chips in place during and after sawing ii. M P Groover.The frame is a convenience in subsequent handling of the chips b)Chips with ink dots are now discarded ©2013 John Wiley & Sons. Inc.Chip Separation 1) Wafer is cut into individual chips (dice) using a thin diamond impregnated saw blade a)The wafer is attached to a piece of adhesive tape mounted in a frame i. Principles of Modern Manufacturing 5/e . M P Groover. including: a)Eutectic die bonding – for ceramic packages b)Epoxy die bonding – for plastic packages ©2013 John Wiley & Sons.Die Bonding 1) Automated handling systems pick separated chips from tape frame and place them for die bonding 2) Various techniques are used to bond the chip to the packaging substrate. Principles of Modern Manufacturing 5/e . Inc. Principles of Modern Manufacturing 5/e .org/wiki/Die_%28integrated_circuit%29 ©2013 John Wiley & Sons. Inc. M P Groover.Die Bonding: 2 dice bonded to one chip carrier See https://en.wikipedia. electrical connections are made between contact pads on chip surface and package lead frame using small diameter wires ©2013 John Wiley & Sons. M P Groover. Principles of Modern Manufacturing 5/e . Inc.Wire Connections 1) After die is bonded to package. wikipedia. See https://en.org/wiki/Integrated_circuit ©2013 John Wiley & Sons. Inc. Principles of Modern Manufacturing 5/e . M P Groover.Wire Connections Integrated circuit from an EPROM memory microchip showing the memory blocks. the supporting circuitry and the fine silver wires which connect the integrated circuit die to the legs of the packaging. Inc. Principles of Modern Manufacturing 5/e . M P Groover.Packaging of IC Chip  (a) Cutaway view showing the chip attached to a lead frame and (b) encapsulated in a plastic enclosure ©2013 John Wiley & Sons. Final Testing 1) Upon completion of packaging sequence. Inc. have been damaged during packaging b)Measure performance characteristics of each device ©2013 John Wiley & Sons. M P Groover. Principles of Modern Manufacturing 5/e . each IC must undergo a final test 2) Purpose of test: a)Determine which units. if any. Yields in IC Processing 1) Fabrication of ICs consists of many processing steps performed in sequence a)In wafer processing in particular. M P Groover. Inc. resulting in loss of the wafer or portions of it corresponding to individual chips ©2013 John Wiley & Sons. there is a chance that something can go wrong. Principles of Modern Manufacturing 5/e . there may be hundreds of distinct operations performed on the wafer 2) At each step. M P Groover.Probability Model to Predict Yield 1) A simple probability model to predict the final yield of good product is: Y = Yc Ys Yw Ym Yt 2) Given the typical values at each step. Principles of Modern Manufacturing 5/e . Inc. the final yield compared to the starting amount of silicon is quite low ©2013 John Wiley & Sons. Sequence in IC Processing  (1) Pure silicon is formed from molten state into ingot and then sliced into wafers. Principles of Modern Manufacturing 5/e . M P Groover. and (3) wafer is cut into chips and packaged ©2013 John Wiley & Sons. (2) fabrication of integrated circuits on wafer. Inc. Inc. M P Groover. Crystal‑to‑slice yield Ys .material left after grinding boule and sawing into wafers (kerf losses): Ys  50% 3. Crystal yield Yc . Multiprobe yield Ym – proportion passing multiprobe test: Ym < 10% to Ym > 90% 5. Wafer yield Yw .material in boule relative to starting amount of electronic grade silicon: Yc  50% 2. Principles of Modern Manufacturing 5/e .Yields of Major Processing Steps 1. Final test yield Yt – proportion to pass final test after packaging: Yt = 90% to 95% ©2013 John Wiley & Sons.wafers surviving processing relative to starting quantity: Yw  70% 4. The Key to Successful IC Fabrication 1) Wafer processing: for an IC producer to be profitable. Inc. M P Groover. high yields must be achieved during wafer processing 2) This is accomplished by utilizing: a)Purest possible starting materials b)Latest processing technologies and equipment c) Good process control over processing steps d)Maintenance of clean room conditions e)Efficient and effective inspection and testing procedures ©2013 John Wiley & Sons. Principles of Modern Manufacturing 5/e .