1.1 Answering machine Alarm clock Automatic door Automatic lights ATM Automobile: Engine controller Temperature control ABS Electronic dash Navigation system Automotive tune-up equipment Baggage scanner Bar code scanner Battery charger Cable/DSL Modems and routers Calculator Camcorder Carbon monoxide detector Cash register CD and DVD players Ceiling fan (remote) Cellular phones Coffee maker Compass Copy machine Cordless phone Depth finder Digital Camera Digital watch Digital voice recorder Digital scale Digital thermometer Electronic dart board Electric guitar Electronic door bell Electronic gas pump Elevator Exercise machine Fax machine Fish finder Garage door opener GPS Hearing aid Invisible dog fences Laser pointer LCD projector Light dimmer Keyboard synthesizer Keyless entry system Laboratory instruments Metal detector Microwave oven
Model airplanes MP3 player Musical greeting cards Musical tuner Pagers Personal computer Personal planner/organizer (PDA) Radar detector Broadcast Radio (AM/FM/Shortwave) Razor Satellite radio receiver Security systems Sewing machine Smoke detector Sprinkler system Stereo system Amplifier CD/DVD player Receiver Tape player Stud sensor Talking toys Telephone Telescope controller Thermostats Toy robots Traffic light controller TV receiver & remote control Variable speed appliances Blender Drill Mixer Food processor Fan Vending machines Video game controllers Wireless headphones & speakers Wireless thermometer Workstations Electromechanical Appliances* Air conditioning and heating systems Clothes washer and dryer Dish washer Electrical timer Iron, vacuum cleaner, toaster Oven, refrigerator, stove, etc. *These appliances are historically based only upon on-off (bang-bang) control. However, many of the high end versions of these appliances have now added sophisticated electronic control.
= 8.85 x 1010 transistors/μP (2 ) N 2 1610x10 0.1548(Y2 −Y1 ) = = 10 0.1548(Y1 −1970) N1 1610x10 log2 (a) Y2 − Y1 = = 1.95 years 0.1548 log10 (b) Y2 − Y1 = = 6.46 years 0.1548 0.1548 Y −1970
1.6
−0.05806(2020−1970)
F = 8.00x10
μm = 10 nm .
No, this distance corresponds to the diameter of only a few atoms. Also, the wavelength of the radiation needed to expose such patterns during fabrication is represents a serious problem. 1.7
From Fig. 1.4, there are approximately 600 million transistors on a complex Pentium IV microprocessor in 2004. From Prob. 1.4, the number of transistors/μP will be 8.85 x 1010. in 2020. Thus there will be the equivalent of 8.85x1010/6x108 = 148 Pentium IV processors.
A 4 digit readout ranges from 0000 to 9999 and has a resolution of 1 part in 10,000. The number of bits must satisfy 2B ≥ 10,000 where B is the number of bits. Here B = 14 bits. 1.15 5.12V mV V 5.12V = 1.25 and VO = (1011101110112 )VLSB ± LSB = 12 bit 2 2 bits 4096 bits 11 9 8 7 5 4 3 VO = 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 1 1.25mV ± 0.0625V
VLSB =
(
)
10
VO = 3.754 ± 0.000625 or 3.753V ≤ VO ≤ 3.755V
1-3 6/9/06
1.16
IB = dc component = 0.002 A, ib = signal component = 0.002 cos (1000t) A 1.17
VGS = 4 V, vgs = 0.5u(t-1) + 0.2 cos 2000 t Volts 1.18
vCE = [5 + 2 cos (5000t)] V 1.19
vDS = [5 + 2 sin (2500t) + 4 sin (1000t)] V 1.20
V = 10 V, R1 = 22 kΩ, R2= 47 kΩ and R3 = 180 kΩ. +
(a) 3000(1− .01)≤ R ≤ 3000(1+ .01) or 2970Ω ≤ R ≤ 3030Ω
(b) 3000(1− .05)≤ R ≤ 3000(1+ .05) or 2850Ω ≤ R ≤ 3150Ω
(c) 3000(1− .10) ≤ R ≤ 3000(1+ .10) or 2700Ω ≤ R ≤ 3300Ω ΔV ≤ 0.05V
0.05 = 0.0200 or 2.00% 2.50
1.48
Vnom = 2.5V
1.49
20000μF (1− .5)≤ C ≤ 20000μF (1+ .2) or 10000μF ≤ R ≤ 24000μF
1.50
8200(1− 0.1)≤ R ≤ 8200(1+ 0.1) or 7380Ω ≤ R ≤ 9020Ω The resistor is within the allowable range of values.
T=
1-15 6/9/06
1.51
(a) 5V (1− .05)≤ V ≤ 5V (1+ .05) or 5.75V ≤ V ≤ 5.25V V = 5.30 V exceeds the maximum range, so it is out of the specification limits. (b) If the meter is reading 1.5% high, then the actual voltage would be 5.30 = 5.22V which is within specifications limits. Vmeter = 1.015Vact or Vact = 1.015 1.52
ΔR 6562 − 6066 Ω = = 4.96 o ΔT 100 − 0 C = R o + TCR (ΔT)= 6066 + 4.96(27)= 6200Ω
(a) (1.763 mA)(20.70 kΩ) = 36.5 V (b) 36 V (c) (0.1021 A)(97.80 kΩ) = 9.99 V; 10 V
1-19 6/9/06
CHAPTER 2 2.1 Based upon Table 2.1, a resistivity of 2.6 μΩ-cm < 1 mΩ-cm, and aluminum is a conductor. 2.2 Based upon Table 2.1, a resistivity of 1015 Ω-cm > 105 Ω-cm, and silicon dioxide is an insulator. 2.3 I max
⎛ 10−8 cm2 ⎞ ⎛ 7 A ⎞ = ⎜10 ⎟ = 500 mA ⎟(5μm)(1μm)⎜ 2 cm 2 ⎠ ⎝ ⎝ μm ⎠
2.4
EG ⎛ ⎞ ni = BT 3 exp⎜ − ⎟ −5 ⎝ 8.62 x10 T ⎠ 31 For silicon, B = 1.08 x 10 and EG = 1.12 eV: -10
3
ni = 2.01 x10 /cm
9
3
13
6.73 x10 /cm
30
For germanium, B = 2.31 x 10 and EG = 0.66 eV: 3
13
ni = 35.9/cm
3
2.27 x10 /cm
15
function f=temp(T) ni=1E14; f=ni^2-1.08e31*T^3*exp(-1.12/(8.62e-5*T)); 14
3
16
ni = 10 /cm3 for T = 739 K
for T = 506 K
2.6
⎛ ⎞ EG ni = BT 3 exp⎜ − −5 ⎟ ⎝ 8.62x10 T ⎠
with
B = 1.27x1029 K −3cm−6 6
3
T = 300 K and EG = 1.42 eV: ni = 2.21 x10 /cm 3
T = 100 K: ni = 6.03 x 10-19/cm
20
3
8.04 x 10 /cm .
2.5 Define an M-File:
ni = 10 /cm
3
8.36 x 10 /cm .
11
3
T = 500 K: ni = 2.79 x10 /cm
2.7
⎛ cm2 ⎞⎛ V ⎞ 6 cm vn = −μn E = ⎜ −700 ⎟⎜ 2500 ⎟ = −1.75x10 V − s ⎠⎝ cm ⎠ s ⎝ ⎛ V ⎞ cm2 ⎞⎛ 5 cm v p = +μ p E = ⎜ +250 ⎟⎜ 2500 ⎟ = +6.25x10 cm ⎠ V − s ⎠⎝ s ⎝ ⎛ 1 ⎞⎛ cm ⎞ 4 A jn = −qnvn = −1.60x10−19 C ⎜1017 3 ⎟⎜ −1.75x106 ⎟ = 2.80x10 s ⎠ cm ⎠⎝ cm2 ⎝ ⎛ 1 ⎞⎛ cm ⎞ −10 A j p = qnv p = 1.60x10−19 C ⎜103 3 ⎟⎜ 6.25x105 ⎟ = 1.00x10 s ⎠ cm 2 ⎝ cm ⎠⎝
(
)
(
)
2.8
⎛ E ⎞ ni2 = BT 3 exp⎜ − G ⎟ ⎝ kT ⎠
B = 1.08x1031
⎛ ⎞ 1.12 T 3 exp⎜ − ⎟ ⎝ 8.62x10−5 T ⎠ Using a spreadsheet, solver, or MATLAB yields T = 305.22K
(10 ) = 1.08x10 10
2
31
Define an M-File: function f=temp(T) f=1e20-1.08e31*T^3*exp(-1.12/(8.62e-5*T)); Then: fzero('temp',300) | ans = 305.226 K 2.9
v=
j − 1000 A / cm 2 cm = = − 105 2 Q s 0.01C / cm
2.10 C ⎞⎛ cm ⎞ MA ⎛ 6 A j = Qv = ⎜ 0.4 3 ⎟⎜10 7 =4 2 ⎟ = 4 x10 2 cm ⎠⎝ sec ⎠ cm cm ⎝
21
2.11
⎛ V ⎞ cm2 ⎞⎛ 6 cm vn = −μn E = ⎜−1000 ⎟⎜ −2000 ⎟ = +2.00x10 V − s ⎠⎝ cm ⎠ s ⎝ ⎛ V ⎞ cm 2 ⎞⎛ 5 cm v p = +μ p E = ⎜ +400 ⎟⎜ −2000 ⎟ = −8.00x10 V − s ⎠⎝ cm ⎠ s ⎝ ⎛ 1 ⎞⎛ cm ⎞ −10 A jn = −qnvn = −1.60x10−19 C ⎜103 3 ⎟⎜ +2.00x106 ⎟ = −3.20x10 s ⎠ cm2 ⎝ cm ⎠⎝ ⎛ 1 ⎞⎛ cm ⎞ 4 A j p = qnv p = 1.60x10−19 C ⎜1017 3 ⎟⎜ −8.00x105 ⎟ = −1.28x10 s ⎠ cm ⎠⎝ cm2 ⎝
(
)
(
)
2.12
(a )
E=
V 5V = 5000 −4 cm 10 x10 cm
(b )
(
)
V ⎞ ⎛ −4 V = ⎜105 ⎟ 10 x10 cm = 100 V cm ⎝ ⎠
2.13
⎛ 1019 ⎞⎛ cm ⎞ 7 A j p = qpv p = 1.60x10−19 C ⎜ 3 ⎟⎜10 7 ⎟ = 1.60x10 s ⎠ cm2 ⎝ cm ⎠⎝ ⎛ A ⎞ i p = j p A = ⎜1.60x10 7 2 ⎟ 1x10−4 cm 25x10−4 cm = 4.00 A cm ⎠ ⎝
(
)
(
)(
)
2.14 For intrinsic silicon, σ = q (μn ni + μ p ni )= qni (μn + μ p )
σ ≥ 1000(Ω − cm) for a conductor −1
ni ≥
σ
q (μn + μ p )
1000(Ω − cm)
−1
=
cm 2 1.602x10−19 C (100 + 50) v − sec 39 ⎛ ⎞ 1.73x10 E n 2i = = BT 3 exp⎜ − G ⎟ with 6 cm ⎝ kT ⎠
=
4.16x1019 cm3
B = 1.08x1031 K −3cm−6 , k = 8.62x10-5 eV/K and EG = 1.12eV
This is a transcendental equation and must be solved numerically by iteration. Using the HP solver routine or a spread sheet yields T = 2701 K. Note that this temperature is far above the melting temperature of silicon.
22
2.15 For intrinsic silicon, σ = q (μn ni + μ p ni )= qni (μn + μ p )
σ ≤ 10−5 (Ω − cm) for an insulator −1
ni ≥
σ
q (μn + μ p )
10−5 (Ω − cm)
−1
=
⎛ cm 2 ⎞ 1.602x10 C (2000 + 750)⎜ ⎟ ⎝ v − sec ⎠ ⎛ E ⎞ 5.152x1020 n 2i = = BT 3 exp⎜ − G ⎟ with 6 cm ⎝ kT ⎠
(
−19
)
=
2.270x1010 cm 3
B = 1.08x1031 K −3cm−6 , k = 8.62x10-5 eV/K and EG = 1.12eV
Using MATLAB as in Problem 2.5 yields T = 316.6 K. 2.16
Si
Si
Si
P
B
Si
Si
Si
Si
Donor electron fills acceptor vacancy
No free electrons or holes (except those corresponding to ni). 2.17
(a) Gallium is from column 3 and silicon is from column 4. Thus silicon has an extra electron and will act as a donor impurity. (b) Arsenic is from column 5 and silicon is from column 4. Thus silicon is deficient in one electron and will act as an acceptor impurity. 2.18 Since Ge is from column IV, acceptors come from column III and donors come from column V. (a) Acceptors: B, Al, Ga, In, Tl (b) Donors: N, P, As, Sb, Bi
23
2.19 (a) Germanium is from column IV and indium is from column III. Thus germanium has one extra electron and will act as a donor impurity. (b) Germanium is from column IV and phosphorus is from column V. Thus germanium has one less electron and will act as an acceptor impurity. 2.20 A ⎞ V ⎛ = jρ = ⎜10000 2 ⎟(0.02Ω − cm ) = 200 , a small electric field. cm ⎠ σ cm ⎝ j
E=
2.21
⎛ C ⎞⎛ cm ⎞ A jndrift = qnμn E = qnv n = 1.602x10−19 1016 ⎜ 3 ⎟⎜10 7 ⎟ = 16000 2 s ⎠ cm ⎝ cm ⎠⎝
(
)( )
2.22 ⎛ 1015 atoms ⎞ ⎛ 10−4 cm ⎞3 N =⎜ ⎟(1μm)(10μm)(0.5μm )⎜ ⎟ = 5,000 atoms 3 ⎝ cm ⎠ ⎝ μm ⎠
2.23 N A > N D : N A − N D = 1015 −1014 = 9x1014 /cm3
If we assume N A − N D >> 2ni = 1014 / cm 3 : p = N A − N D = 9x1014 /cm3 | n = If we use Eq. 2.12 : p =
9x1014 ±
ni2 251026 = = 2.78x1012 /cm3 p 9x1014
(9x10 ) + 4(5x10 ) = 9.03x10 14
2
13
2
14
2 and n = 2.77x10 /cm . The answers are essentially the same. 12
3
2.24 N A > N D: N A − N D = 5 x1016 − 1016 = 4 x1016 /cm 3 >> 2ni = 2 x1011 /cm 3 p = N A − N D = 4 x1014 /cm 3 | n =
ni2 10 22 = = 2.50 x10 5 /cm 3 p 4 x1016
2.25 N D > N A: N D − N A = 3x1017 − 2x1017 = 1x1017 /cm3
2ni = 2x1017 /cm3 ; Need to use Eq. (2.11) n= p=
24
1017 ±
( ) ( ) = 1.62x10 2
1017 + 4 1017
2
2
2 i
34
n 10 = = 6.18x1016 /cm3 n 1.62x1017
17
/cm3
2.26 N D − N A = −2.5x1018 / cm 3 Using Eq. 2.11: n =
−2.5x1018 ±
(−2.5x10 ) + 4(10 ) 18
2
10
2
2
ni2 = ∞. p No, the result is incorrect because of loss of significant digits
Evaluating this with a calculator yields n = 0, and n =
within the calculator. It does not have enough digits.
2.27
(a) Since boron is an acceptor, NA = 6 x 1018/cm3. Assume ND = 0, since it is not specified. The material is p-type. At room temperature, ni = 1010 /cm3 and N A − N D = 6 x1018 / cm3 >> 2n i ni2 10 20 /cm 6 So p = 6 x10 /cm and n = = = 16.7 /cm3 18 3 p 6 x10 /cm (b) ⎛ ⎞ 3 1.12 ⎟ At 200K, ni2 = 1.08x1031 (200) exp⎜⎜ − = 5.28x109 /cm6 −5 ⎟ ⎝ 8.62x10 (200)⎠ 18
3
ni = 7.27x10 4 /cm 3
N A − N D >> 2ni , so p = 6x1018 /cm3 and n =
5.28x109 = 8.80x10−10 /cm 3 18 6x10
2.28
(a) Since arsenic is a donor, ND = 3 x 1017/cm3. Assume NA = 0, since it is not specified. The material is n-type. At room temperature, n i = 1010 / cm 3 and N D − N A = 3 x1017 / cm 3 >> 2n i 10 20 /cm 6 ni2 = = 333 /cm 3 17 3 n 3x10 /cm ⎛ ⎞ 3 1.12 ⎟ = 4.53x1015 /cm6 (b) At 250K, ni2 = 1.08x1031 (250) exp⎜⎜− −5 ⎟ ⎝ 8.62x10 (250)⎠
So n = 3 x1017 /cm 3 and p =
ni = 6.73x10 7 /cm 3
N D − N A >> 2ni , so n = 3x1017 / cm 3 and n =
4.53x1015 = 0.0151/ cm 3 17 3x10
2.29
(a) Arsenic is a donor, and boron is an acceptor. ND = 2 x 1018/cm3, and NA = 8 x 1018/cm3. Since NA > ND, the material is p-type.
25
(b) At room temperature, n i = 1010 / cm3 and N A − N D = 6 x1018 / cm3 >> 2n i ni2 10 20 /cm 6 So p = 6 x10 /cm and n = = = 16.7 /cm3 18 3 p 6 x10 /cm 18
3
2.30
(a) Phosphorus is a donor, and boron is an acceptor. ND = 2 x 1017/cm3, and NA = 5 x 1017/cm3. Since NA > ND, the material is p-type. (b) At room temperature, ni = 1010 /cm3 and N A − N D = 3x1017 / cm3 >> 2n i ni2 10 20 /cm 6 So p = 3x10 /cm and n = = = 333 /cm3 17 3 p 3x10 /cm 17
3
2.31
ND = 4 x 1016/cm3. Assume NA = 0, since it is not specified. N D > N A : material is n - type | N D − N A = 4x1016 / cm3 >> 2ni = 2x1010 / cm 3 n = 4x1016 / cm3 | p =
n 2i 1020 = = 2.5x103 / cm 3 16 n 4x10
N D + N A = 4x1016 / cm3 | Using Fig. 2.13, μn = 1030
ρ=
26
1 qμn n
=
1
⎛ cm 2 ⎞⎛ 4x1016 ⎞ 1.602x10 C ⎜1030 ⎟⎜ ⎟ V − s ⎠⎝ cm 3 ⎠ ⎝
(
−19
)
cm2 cm 2 and μp = 310 V −s V −s
= 0.152 Ω − cm
2.32 NA = 1018/cm3. Assume ND = 0, since it is not specified. N A > N D : material is p - type | N A − N D = 1018 / cm3 >> 2ni = 2x1010 / cm 3 p = 1018 / cm3
|
n=
n 2i 1020 = 18 = 100 / cm 3 p 10
cm2 cm 2 N D + N A = 10 / cm | Using Fig. 2.13, μn = 375 and μp = 100 V −s V −s 1 1 ρ= = = 0.0624 Ω − cm ⎛ qμ p p cm 2 ⎞⎛ 1018 ⎞ −19 1.602x10 C⎜100 ⎟⎜ ⎟ V − s ⎠⎝ cm 3 ⎠ ⎝ 18
3
2.33 Indium is from column 3 and is an acceptor. NA = 7 x 1019/cm3. Assume ND = 0, since it is not specified. N A > N D : material is p - type | N A − N D = 7x1019 /cm3 >> 2ni = 2x1010 /cm3 p = 7x1019 /cm3
|
n=
ni2 1020 = = 1.43/cm3 19 p 7x10
cm2 cm 2 N D + N A = 7x10 / cm | Using Fig. 2.13, μn = 120 and μp = 60 V −s V −s 1 1 ρ= = = 1.49 mΩ − cm ⎛ qμ p p cm 2 ⎞⎛ 7x1019 ⎞ −19 1.602x10 C⎜ 60 ⎟⎜ 3 ⎟ ⎝ V − s ⎠⎝ cm ⎠ 19
3
2.34 Phosphorus is a donor : N D = 5.5x1016 / cm 3 | Boron is an acceptor : N A = 4.5x1016 / cm 3 N D > N A : material is n - type
|
N D − N A = 1016 / cm3 >> 2ni = 2x1010 / cm 3
ni2 1020 n = 10 /cm | p = = 16 = 10 4 /cm3 p 10 16
3
cm2 cm 2 N D + N A = 10 / cm | Using Fig. 2.13, μn = 800 and μp = 230 V −s V −s 1 1 ρ= = = 0.781 Ω − cm ⎛ qμ n n cm 2 ⎞⎛ 1016 ⎞ −19 1.602x10 C⎜ 800 ⎟⎜ ⎟ V − s ⎠⎝ cm 3 ⎠ ⎝ 17
27
3
2.35
1
ρ=
qμ p p
| μp p =
1
(1.602x10 C)(0.054Ω − cm) −19
=
1.16x1020 V − cm − s
An iterative solution is required. Using the equations in Fig. 2.8: NA
μp
μp p
1018
96.7
9.67 x 1020
1.1 x1018
93.7
1.03 x 1020
1.2 x 1017
91.0
1.09 x 1020
1.3 x 1019
88.7
1.15 x 1020
2.36
8.32x1018 ρ= | μp p = = qμ p p 1.602x10−19 C (0.75Ω − cm) V − cm − s 1
1
(
)
An iterative solution is required. Using the equations in Fig. 2.8: μp
NA 1016
μp p
406
4.06 x 1018
2 x 1016
363
7.26 x 1018
3 x 1016
333
1.00 x 1019
2.4 x 1016
350
8.40 x 1018
2.37 Based upon the value of its resistivity, the material is an insulator. However, it is not intrinsic because it contains impurities. Addition of the impurities has increased the resistivity. 2.38
ρ=
1 qμn n
| μ n n ≈ μn N D =
1
(1.602x10 C)(2Ω − cm) −19
=
3.12x1018 V − cm − s
An iterative solution is required. Using the equations in Fig. 2.8: ND
μn
μnn
1015
1350
1.35 x 1018
2 x 1015
1330
2.67 x 1018
2.5 x 1015
1330
3.32 x 1018
28
2.3 x 1015
29
1330
3.06 x 1018
2.39 (a) 1 1 6.24x1021 ρ= | μn n ≈ μn N D = = qμn n 1.602x10−19 C (0.001Ω − cm) V − cm − s
(
)
An iterative solution is required. Using the equations in Fig. 2.8: ND
μn
μnn
1019
116
1.16 x 1021
7 x 1019
96.1
6.73 x 1021
6.5 x 1019
96.4
6.3 x 1021
(b)
ρ=
1 qμ p p
| μp p ≈ μp N A =
1 6.24 x10 21 = (1.602x10−19 C)(0.001Ω − cm) V − cm − s
An iterative solution is required using the equations in Fig. 2.8: NA 1.3 x 1020
μp
μp p
49.3
6.4 x 1021
2.40
Yes, by adding equal amounts of donor and acceptor impurities the mobilities are reduced, but the hole and electron concentrations remain unchanged. See Problem 2.37 for example. However, it is physically impossible to add exactly equal amounts of the two impurities. 2.41 (a) For the 1 ohm-cm starting material: 1 1 6.25x1018 ρ= | μp p ≈ μpN A = = qμ p p 1.602x10−19 C (1Ω − cm) V − cm − s
(
)
An iterative solution is required. Using the equations in Fig. 2.8: NA
μp
μp p
1016
406
4.1 x 1018
1.5 x 1016
383
5.7 x 1018
1.7 x 1016
374
6.4 x 1019
30
To change the resistivity to 0.25 ohm-cm: 1 1 2.5x1019 ρ= | μp p ≈ μpN A = = qμ p p 1.602x10−19 C (0.25Ω − cm) V − cm − s
(
)
NA
μp
μp p
6 x 1016
276
1.7 x 1019
8 x 1016
233
2.3 x 1019
1.1 x 1017
225
2.5 x 1019 17
16
16
3
Additional acceptor concentration = 1.1x10 - 1.7x10 = 9.3 x 10 /cm (b) If donors are added: ND
ND + NA
μn
ND - NA
μnn
2 x 1016
3.7 x 1016
1060
3 x 1015
3.2 x 1018
1 x 1017
1.2 x 1017
757
8.3 x 1016
6.3 x 1019
8 x 1016
9.7 x 1016
811
6.3 x 1016
5.1 x 1019
4.1 x 1016
5.8 x 1016
950
2.4 x 1016
2.3 x 1019
16
3
So ND = 4.1 x 10 /cm must be added to change achieve a resistivity of 0.25 ohm-cm. The silicon is converted to n-type material. 2.42 Phosphorus is a donor: ND = 1016/cm3 and μn = 1250 cm2/V-s from Fig. 2.8. 2.00 σ = qμn n ≈ qμn N D = 1.602x10−19 C (1250) 1016 = Ω − cm -1 Now we add acceptors until σ = 5.0 (Ω-cm) :
(
)
( )
5(Ω − cm)
−1
σ = qμ p p
|
3.12x1019 μ p p ≈ μ p (N A − N D )= = 1.602x10−19 C V − cm − s
NA
ND + NA
μp
NA - ND
μp p
1 x 1017
1.1 x 1017
250
9 x 1016
2.3 x 1019
2 x 1017
2.1 x 1017
176
1.9 x 1017
3.3 x 1019
1.8 x 1017
1.9 x 1017
183
1.7 x 1016
3.1 x 1019
31
2.43
Boron is an acceptor: NA = 1016/cm3 and μp = 405 cm2/V-s from Fig. 2.8. 0.649 σ = qμ p p ≈ qμ p N A = 1.602x10−19 C (405) 1016 = Ω − cm -1 Now we add donors until σ = 5.5 (Ω-cm) :
(
)
( )
5.5(Ω − cm)
−1
σ = qμ n n
|
μn n ≈ μn (N D − N A )=
1.602x10−19 C
=
3.43x1019 V − cm − s
ND
ND + NA
μn
ND - NA
μp p
8 x 1016
9 x 1016
832
7 x 1016
5.8 x 1019
7 x 1016
901
5 x 1016
4.5 x 1019
5.5 x 1016
964
3.5 x 1016
3.4 x 1019
6 x 1016 4.5 x 1016
2.44
VT =
kT 1.38x10−23 T = = 8.62x10−5 T q 1.602x10−19
T (K)
50
75
100
150
200
250
300
350
400
VT (mV)
4.31
6.46
8.61
12.9
17.2
21.5
25.8
30.1
34.5
2.45
⎛ dn ⎞ dn j = −qDn ⎜− ⎟ = qVT μn dx ⎝ dx ⎠
⎛ cm2 ⎞⎛ 1018 − 0 ⎞ 1 kA j = 1.602x10−19 C (0.025V )⎜ 350 = −14.0 2 ⎟⎜ −4 ⎟ 4 V − s ⎠⎝ 0 −10 ⎠ cm cm ⎝
(
)
2.46
⎛ cm2 ⎞⎛ 1019 / cm 3 ⎞ ⎛ ⎞ dp x = −1.602x10−19 C ⎜15 ⎟⎜ − ⎟ exp⎜− ⎟ −4 −4 s ⎠⎝ 2x10 cm ⎠ ⎝ 2x10 cm ⎠ dx ⎝ ⎛ x ⎞ A j = 1.20x105 exp⎜−5000 ⎟ 2 cm ⎠ cm ⎝ ⎛ 10−8 cm2 ⎞ ⎛ A ⎞ I (0)= j (0)A = ⎜1.20x105 2 ⎟ 10μm2 ⎜ ⎟ = 12.0 mA 2 cm ⎠ ⎝ ⎝ μm ⎠ j = −qD p
(
)
(
32
)
2.47
j p = qμ p pE − qD p
⎛ dp 1 dp ⎞ 1 dp = qμ p p⎜ E − VT ⎟ = 0 → E = VT dx p dx ⎠ p dx ⎝
(
)
−1022 exp −10 4 x 1 dN A E ≈ VT = 0.025 14 N A dx 10 + 1018 exp −10 4 x E (0)= −0.025
(
)
22
10 V = −250 18 cm 10 + 10 22 10 exp(−5) V E 5x10−4 cm = −0.025 14 = −246 18 cm 10 + 10 exp(−5)
(
14
)
2.48
⎛ V ⎞ cm2 ⎞⎛ 1016 ⎞⎛ A jndrift = qμn nE = 1.60x10−19 C ⎜350 ⎟⎜ 3 ⎟⎜ −20 ⎟ = −11.2 2 cm ⎠ V − s ⎠⎝ cm ⎠⎝ cm ⎝ ⎛ V ⎞ cm2 ⎞⎛1.01x1018 ⎞⎛ A drift −19 −20 j p = qμ p pE = 1.60x10 C ⎜150 ⎟⎜ ⎟ ⎜ ⎟ = −484 2 3 cm ⎠ V − s ⎠⎝ cm cm ⎝ ⎠⎝ ⎛ A cm2 ⎞⎛ 10 4 −1016 ⎞ dn = −70.0 2 jndiff = qDn = 1.60x10−19 C ⎜ 350 ⋅ 0.025 ⎟⎜ −4 4⎟ s ⎠⎝ 2x10 cm ⎠ dx cm ⎝ ⎛ A cm2 ⎞⎛ 1018 −1.01x1018 ⎞ dp j pdiff = −qD p = −1.60x10−19 C ⎜150 ⋅ 0.025 ⎟⎜ ⎟ = 30.0 2 −4 4 s ⎠⎝ 2x10 cm ⎠ dx cm ⎝ A jT = −11.2 − 484 − 70.0 + 30.0 = −535 2 cm
(
)
(
)
(
)
(
2.49
)
NA = 2ND
EC ED
N
D
ND
ND
EA
NA
NA
NA
E V
Holes
2.50
(
)(
) )
−34 8 hc 6.626x10 J − s 3x10 m / s λ= = = 1.108 μm E (1.12eV ) 1.602x10−19 J / eV
33
(
NA
2.51 Al - Anode
Al - Cathode Si02 n-type silicon
p-type silicon
2.52 An n-type ion implantation step could be used to form the n+ region following step (f) in Fig. 2.17. A mask would be used to cover up the opening over the p-type region and leave the opening over the n-type silicon. The masking layer for the implantation could just be photoresist. Mask
Ion implantation
Photoresist Si02 n+
p-type silicon
n-type silicon
p-type silicon
n-type silicon
Structure following ion implantation of n-type impurity
Structure after exposure and development of photoresist layer
(b) V = l 3 = 0.543x10−9 m = 0.543x10−7 cm = 1.60x10−22 cm3 8 atoms atoms = 5.00x1022 1.60x1022 cm3 cm3 ⎛ g ⎞ (d ) m = ⎜ 2.33 3 ⎟1.60x1022 cm3 = 3.73x10−22 g cm ⎠ ⎝ (c) D =
(e) From Table 2.2, silicon has a mass of 28.086 protons. mp =
g 3.73x10−22 g = 1.66x10−24 proton 28.082(8)protons
Yes, near the actual proton rest mass.
34
CHAPTER 3 3.1
1019 ⋅ cm−3 )(1018 ⋅ cm −3 ) ( NA ND φ j = VT ln 2 = (0.025V )ln = 0.979V ni 10 20 ⋅ cm −6 2(11.7 ⋅ 8.854 x10−14 F ⋅ cm−1 )⎛ ⎞ 2εs ⎛ 1 1 ⎞ 1 1 w do = + ⎜ 19 −3 + 18 −3 ⎟ (0.979V) ⎜ ⎟ φj = −19 ⎝ 10 cm q ⎝ NA ND ⎠ 1.602x10 C 10 cm ⎠ w do = 3.73 x 10−6 cm = 0.0373μm w do 0.0373μm w do 0.0373μm -3 xn = = = μm 18 −3 = 0.0339 μm | x p = 19 −3 = 3.39 x 10 ND N 10 10 cm cm A 1+ 1+ 1+ 19 −3 1+ 18 −3 NA ND 10 cm 10 cm E MAX =
qN A x p
εs
(1.60x10 =
−19
C )(1019 cm −3 )(3.39x10−7 cm)
11.7 ⋅ 8.854 x10
−14
F /cm
= 5.24 x 10 5
V cm
3.2 p po = N A =
1018 cm 3
1015 n no = N D = cm 3
| n po =
n i2 10 20 10 2 = = p po 1018 cm 3
n i2 10 20 10 5 | p no = = = n no 1015 cm 3
1018 cm−3 )(1015 cm −3 ) ( NA ND φ j = VT ln 2 = (0.025V )ln = 0.748 V ni 10 20 cm−6 w do =
2(11.7 ⋅ 8.854 x10−14 F ⋅ cm−1 )⎛ ⎞ 2εs ⎛ 1 1 ⎞ 1 1 + φ = ⎜ 18 −3 + 15 −3 ⎟ (0.748V) ⎜ ⎟ j −19 ⎝ 10 cm 10 cm ⎠ q ⎝ NA ND ⎠ 1.602x10 C
w do = 98.4 x 10−6 cm = 0.984 μm 3.3
p po = N A =
1018 ni2 1020 102 | n = = = po p po 1018 cm3 cm3
1018 ni2 1020 102 nno = N D = 3 | p no = = = nno 1018 cm3 cm 1018 ⋅ cm−3 )(1018 ⋅ cm −3 ) ( NA ND φ j = VT ln 2 = (0.025V )ln = 0.921V ni 10 20 ⋅ cm −6 w do =
2(11.7 ⋅ 8.854 x10−14 F ⋅ cm−1 )⎛ ⎞ 2εs ⎛ 1 1 ⎞ 1 1 + φ = ⎜ 18 −3 + 18 −3 ⎟ (0.921V) ⎜ ⎟ j −19 ⎝ 10 cm 10 cm ⎠ q ⎝ NA ND ⎠ 1.602x10 C
w do = 4.881x10−6 cm = 0.0488 μm
34
3.4
p po = N A =
1018 ni2 1020 102 | n = = = po p po 1018 cm3 cm3
1018 ni2 1020 102 | p = = = no nno 1018 cm3 cm3 (1018 ⋅ cm−3 )(1020 ⋅ cm−3 ) = 1.04V N N φ j = VT ln A 2 D = (0.025V )ln ni 10 20 ⋅ cm −6 nno = N D =
2(11.7 ⋅ 8.854 x10−14 F ⋅ cm−1 )⎛ ⎞ 2εs ⎛ 1 1 ⎞ 1 1 w do = + ⎜ 18 −3 + 20 −3 ⎟ (1.04V) ⎜ ⎟ φj = −19 ⎝ 10 cm 10 cm ⎠ q ⎝ NA ND ⎠ 1.602x10 C w do = 0.0369 μm 3.5
p po = N A =
1016 ni2 1020 10 4 | n = = = po p po 1016 cm3 cm3
1019 ni2 1020 10 | p = = = no nno 1019 cm3 cm3 1019 ⋅ cm−3 1016 ⋅ cm −3 N AND φ j = VT ln = (0.025V )ln = 0.864V ni2 1020 ⋅ cm −6 nno = N D =
(
(
)(
)
)
2 11.7 ⋅ 8.854x10−14 F ⋅ cm−1 ⎛ ⎞ 2εs ⎛ 1 1 ⎞ 1 1 wdo = + ⎜ ⎟ φj = ⎜ 19 −3 + 16 −3 ⎟ (0.864V) −19 q ⎝ N A ND ⎠ 10 cm ⎠ 1.602x10 C ⎝ 10 cm wdo = 0.334 μm 3.6 wd = wdo 1+
1 2 j 1000 A⋅ cm −2 V = | E= n = = 500 −1 0.5 Ω ⋅ cm Ω ⋅ cm cm σ 2(Ω ⋅ cm)
35
3.9
j p = σE
|
E=
jn
σ
(
)
= jn ρ = 5000 A⋅ cm −2 (2Ω ⋅ cm)= 10.0
kV cm
3.10
⎛ 4x1015 ⎞⎛ 10 7 cm ⎞ A j ≅ jn = qnv = 1.60x10−19 C ⎜ ⎟ = 6400 2 3 ⎟⎜ cm ⎝ cm ⎠⎝ s ⎠
(
)
3.11
⎛ 5x1017 ⎞⎛ 10 7 cm ⎞ kA j ≅ j p = qpv = 1.60x10−19 C ⎜ ⎟ = 800 2 3 ⎟⎜ cm ⎝ cm ⎠⎝ s ⎠
(
3.12
j p = qμ p pE − qD p
)
⎛ D ⎞ 1 dp ⎛ kT ⎞ 1 dp dp = 0 → E = −⎜⎜ p ⎟⎟ = −⎜ ⎟ dx ⎝ q ⎠ p dx ⎝ μ p ⎠ p dx
⎛ x⎞ p( x) = N o exp⎜ − ⎟ | ⎝ L⎠
1 dp 1 V V 0.025V | E = − T = − −4 = = −250 L p dx L cm 10 cm
The exponential doping results in a constant electric field. 3.13
j p = qDn
dn dn dn 2000 A/ cm 2 1.00 x 1021 = qμnVT | = = dx dx dx 1.60x10−19 C 500cm2 /V − s (0.025V ) cm 4
(
3.14 10 = 10 4 ⋅10−16 exp(40VD )−1 + VD
[
]
3.15
f = 10 −10 4 I D − 0.025ln
ID + IS IS
)(
)
and the solver yields VD = 0.7464 V
| f ' = −10 4 −
0.025 ID + IS
| I'D = I D − -13
Starting the iteration process with ID = 100 μA and IS = 10 A: ID 1.000E-04 9.275E-04 9.426E-04 9.426E-04
36
f
f'
8.482E+0 0 1.512E01 3.268E06 9.992E16
-1.025E+04 -1.003E+04 -1.003E+04 -1.003E+04
f f'
3.16 (a)
Create the following m-file: function fd=current(id) fd=10-1e4*id-0.025*log(1+id/1e-13); Then: fzero('current',1) yields ans = 9.4258e-04 -15 (b) Changing IS to 10 A: function fd=current(id) fd=10-1e4*id-0.025*log(1+id/1e-15); Then: fzero('current',1) yields ans = 9.3110e-04
3.17
−19 qVT 1.60x10 C (0.025V ) T= = = 290 K k 1.38x10−23 J / K
3.18
(
)
−23 kT 1.38x10 J / K T VT = = = 8.63x10−5 T −19 q 1.60x10 C For T = 218 K, 273 K and 358 K, VT = 18.8 mV, 23.6 mV and 30.9 mV
3.19
⎡ ⎛ 40V ⎞ ⎤ D Graphing I D = I S ⎢exp⎜ ⎟ −1⎥ yields : n ⎝ ⎠ ⎦ ⎣ 6 5
(b)
4
(a)
3
2
1 (c)
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
37
3.20
(
)
1.38x10−23 J / K (300) kT = 1.04 = 26.88 mV nVT = n q 1.60x10−19 C
T = 26.88mV
1.602x10-19 = 312 K 1.38x10-23
3.21
⎡ ⎛v ⎞ ⎤ ⎛ i ⎞ vD = ln⎜1+ D ⎟ iD = I S ⎢exp⎜ D ⎟ −1⎥ or nVT ⎝ IS ⎠ ⎣ ⎝ nVT ⎠ ⎦ ⎛i ⎞ ⎛ 1 ⎞ v For i D >> I S , D ≅ ln⎜ D ⎟ or ln (I D )= ⎜ ⎟v D + ln (IS ) nVT ⎝ IS ⎠ ⎝ nVT ⎠
which is the equation of a straight line with slope 1/nVT and x-axis intercept at -ln (IS). The -4
values of n and IS can be found from any two points on the line in the figure: e. g. iD = 10 A -9
for vD = 0.60 V and iD = 10 A for vD = 0.20 V. Then there are two equations in two unknowns: ⎛ 40 ⎞ ⎛8⎞ ln 10-9 = ⎜ ⎟.20 + ln (IS ) or 9.21 = ⎜ ⎟ + ln (IS ) ⎝n⎠ ⎝n⎠ ⎛ 40 ⎞ ⎛ 24 ⎞ ln 10-4 = ⎜ ⎟.60 + ln (IS ) or 20.72 = ⎜ ⎟ + ln (IS ) ⎝n⎠ ⎝n⎠ -12 Solving for n and IS yields n = 1.39 and IS = 3.17 x 10 A = 3.17 pA.
( ) ( )
3.22
⎡ ⎛V ⎞ ⎤ ⎛ I ⎞ VD = nVT ln⎜1+ D ⎟ | I D = I S ⎢exp⎜ D ⎟ −1⎥ ⎝ IS ⎠ ⎣ ⎝ nVT ⎠ ⎦ ⎛ 7x10−5 A ⎞ ⎛ 5x10−6 A ⎞ = 1.05 0.025V ln (a) VD = 1.05(0.025V )ln⎜1+ = 0.837V | (b) V ⎟ ⎜1+ ⎟ = 0.768V ( ) D 10−18 A ⎠ 10−18 A ⎠ ⎝ ⎝ ⎡ ⎛ ⎞ ⎤ 0 (c) I D = 10−18 A⎢exp⎜ ⎟ −1⎥ = 0 A ⎣ ⎝1.05⋅ 0.025V ⎠ ⎦ ⎡ ⎛ −0.075V ⎞ ⎤ −19 (d) I D = 10−18 A⎢exp⎜ ⎟ −1⎥ = −0.943x10 A ⎣ ⎝ 1.05⋅ 0.025V ⎠ ⎦ ⎡ ⎛ ⎞ ⎤ −5V −18 (e) I D = 10−18 A⎢exp⎜ ⎟ −1⎥ = −1.00x10 A ⎣ ⎝1.05⋅ 0.025V ⎠ ⎦
3.23
⎡ ⎛V ⎞ ⎤ ⎛ I ⎞ VD = nVT ln⎜1+ D ⎟ | I D = I S ⎢exp⎜ D ⎟ −1⎥ ⎝ IS ⎠ ⎣ ⎝ nVT ⎠ ⎦ ⎛ 10−4 A ⎞ ⎛ 10−5 A ⎞ (a) VD = 0.025V ln⎜1+ −17 ⎟ = 0.748V | (b) VD = 0.025V ln⎜1+ −17 ⎟ = 0.691V ⎝ 10 A ⎠ ⎝ 10 A ⎠
ΔV = (−2.0mV / K )(25K ) = −50.0 mV (b) VD = 0.650 − 0.050 = 0.600 V
3.33
−23 ⎛ 2.5x10−4 ⎞ kT 1.38x10 (298) = = 25.67 mV | (a) V = 0.02567V ln ( ) ⎜1+ 10−14 ⎟ = 0.615 V D q 1.602x10−19 ⎝ ⎠
(b) ΔV = (−1.8mV / K )(60K )= −50.0 mV (c) ΔV = (−1.8mV / K )(−80K )= +144 mV
VD = 0.615 − 0.108 = 0.507 V VD = 0.615 + 0.144 = 0.758 V
3.34
mV dvD vD − VG − 3VT 0.7 −1.21− 3(0.0259) = = = −1.96 dT T 300 K
41
3.35 3 ⎡ ⎛ E ⎞⎛ 1 1 ⎞⎤ ⎛ T ⎞3 ⎡⎛ E ⎞⎛ T ⎞⎤ I S 2 ⎛ T2 ⎞ = ⎜ ⎟ exp⎢−⎜ G ⎟⎜ − ⎟⎥ = ⎜ 2 ⎟ exp⎢⎜ G ⎟⎜1− 1 ⎟⎥ I S1 ⎝ T1 ⎠ ⎣ ⎝ k ⎠⎝ T2 T1 ⎠⎦ ⎝ T1 ⎠ ⎣⎝ kT1 ⎠⎝ T2 ⎠⎦ ⎡⎛ E ⎞⎛ 1 ⎞⎤ 3 T x= 2 f (x ) = (x ) exp⎢⎜ G ⎟⎜1− ⎟⎥ T1 ⎣⎝ kT1 ⎠⎝ x ⎠⎦ Using trial and error with a spreadsheet yields T = 4.27 K, 14.6 K, and 30.7 K to increase the saturation current by 2X, 10X, and 100X respectively.
1016 cm −3 1015 cm −3 N AND φ j = VT ln = (0.025V )ln = 0.633 V ni2 1020 cm−6
(
)
2 11.7 ⋅ 8.854x10−14 F ⋅ cm−1 ⎛ ⎞ 2εs ⎛ 1 1 ⎞ 1 1 + wdo = ⎜ ⎟ φj = ⎜ 16 −3 + 15 −3 ⎟ (0.633V) −19 q ⎝ N A ND ⎠ 10 cm ⎠ 1.602x10 C ⎝10 cm wdo = 0.949 μm wd = 0.949μm 1+
42
|
wd = wdo 1+
VR
φj
10V = 3.89 μm 0.633V
|
wd = 0.949μm 1+
100V = 12.0 μm 0.633V
3.38
(
)(
)
1018 cm −3 1020 cm −3 N AND φ j = VT ln = (0.025V )ln = 1.04 V ni2 1020 cm−6
(
2 11.7 ⋅ 8.854x10−14 F ⋅ cm−1 2εs ⎛ 1 1 ⎞ wdo = + ⎟ φj = ⎜ q ⎝ N A ND ⎠ 1.602x10−19 C |
wd = 0.0368μm 1+
5 = 0.0887 μm 1.04
3.39
Emax =
3x105
2(φ j + VR ) wd
=
2(φ j + VR ) wdo 1+
VR
=
⎞ 1 1 + ⎟ (1.04V) 18 −3 1020 cm−3 ⎠ ⎝ 10 cm
VR
wdo = 0.0368 μm
wd = wdo 1+
)⎛⎜
φj
|
wd = 0.0368μm 1+
25 = 0.184 μm 1.04
2φ j V 1+ R wdo φj
φj
2(0.6V ) V V = −4 1+ R → VR = 374 V cm 10 cm 0.6
3.40
2(0.748V ) 2φ kV = 15.2 | E= j = −4 wdo 0.984x10 cm cm
E w φ j + VR = max do = 2 φj
3x105
(
V 0.984x10−4 cm cm 2 0.748V
)
VR = 291.3 − 0.748 = 291 V 3.41
VZ = 4 V; RZ = 0 Ω since the reverse breakdown slope is infinite. 3.42 Since NA >> ND, the depletion layer is all on the lightly-doped side of the junction. Also, VR >> φj, so φj can be neglected. Emax =
2(11.7) 8.854x10−14 ⎛ 1 2εS ⎛ 1 1 ⎞ 1 ⎞ −4 wdo = + + ⎟φ j = ⎜ ⎟0.864 = 1.057x10 cm ⎜ q ⎝ N A ND ⎠ 1.602x10−19 ⎝ 1015 1020 ⎠ C = " jo
εS
=
wdo
(
11.7 8.854x10−14 1.057x10−4
) = 9.80x10
-9
F / cm
2
| Cj =
C "jo A 1+
9.80x10-9 (0.05)
=
VR
= 188 pF
5 1+ 0.864
φj
3.44
φ j = VT ln
N AND 10181015 = 0.025ln = 0.748V ni2 1020
(
2(11.7) 8.854x10−14 2εS ⎛ 1 1 ⎞ wdo = + ⎟φ j = ⎜ q ⎝ N A ND ⎠ 1.602x10−19 C = " jo
εS wdo
=
(
11.7 8.854x10−14 0.984x10−4
3.45
(
) = 10.5x10
-9
(c) CD =
(
0.025V
3.46
(
)
) = 100 pF
(c) CD =
44
(
0.025V
| Cj =
C "jo A
)
) = 0.04 μF
=
10.5x10-9 (0.02)
VR
10 1+ 0.748
φj
(
)
(b) Q = I D τ T = 10−4 A 10−10 s = 10 fC
(
)
| Q = I D τ T = 5x10−3 A 10−10 s = 0.50 pC
−8 I D τ T 1A 10 s (a) CD = = = 0.400 μF VT 0.025V
100mA 10−8 s
1 ⎞ 1 0.748 = 0.984x10−4 cm + 18 15 ⎟ 10 10 ⎠ ⎝
1+
−4 −10 I D τ T 10 A 10 s (a) CD = = = 400 fF VT 0.025V
25x10−3 A 10−10 s
F / cm
2
)⎛⎜
(
)
(b) Q = I D τ T = 1A 10−8 s = 10.0 nC
(
)
| Q = I D τ T = 100mA 10−8 s = 1.00 nC
= 55.4 pF
3.47
N AND 10191017 = 0.025ln = 0.921V ni2 1020
φ j = VT ln
(
)
2(11.7) 8.854x10−14 ⎛ 1 2εS ⎛ 1 1 ⎞ 1 ⎞ wdo = + + ⎟φ j = ⎜ ⎟0.921 = 0.110 μm ⎜ q ⎝ N A ND ⎠ 1.602x10−19 ⎝ 1019 1017 ⎠ C jo =
εS A wdo
=
(
)( ) = 9.42 pF / cm
11.7 8.854x10−14 10−4 −4
0.110x10
C jo
| Cj =
2
1+
=
9.42 pF
= 3.72 pF
5 1+ 0.921
VR
φj
3.48
N AND 10191016 = 0.025ln = 0.864V ni2 1020
φ j = VT ln
(
)⎛⎜
11.7 8.854x10−14 0.25cm2
) = 7750 pF
2(11.7) 8.854x10−14 2εS ⎛ 1 1 ⎞ wdo = + ⎟φ j = ⎜ q ⎝ N A ND ⎠ 1.602x10−19 C jo =
εS A wdo
=
(
)( −4
0.334x10
1 ⎞ 1 + ⎟0.864 = 0.334μm ⎝ 1019 1016 ⎠ | Cj =
C jo 1+
=
7750 pF
= 3670 pF
3 1+ 0.864
VR
φj
3.49 L=
RFC
C VDC
10 μH
10 μH C
C=
C jo 1+
(b) C =
(a) C =
VR
φj
39 pF 10V 1+ 0.75V
39 pF 1V 1+ 0.75V
= 25.5 pF | f o =
= 10.3 pF | f o =
1 2π LC
=
2π
1 2π LC
(
1
=
)
2π
(
1
)
10−5 H 25.5 pF
10−5 H 10.3 pF
= 9.97 MHz
= 15.7 MHz
3.50
⎛ ⎛ 50 A ⎞ 50 A ⎞ (a) VD = (0.025V )ln⎜1+ −7 ⎟ = 0.501 V | (b) VD = (0.025V )ln⎜1+ −15 ⎟ = 0.961 V ⎝ 10 A ⎠ ⎝ 10 A ⎠
45
3.51
⎛ 4x10−3 A ⎞ ⎛ 4x10−3 A ⎞ (a) VD = (0.025V )ln⎜1+ = 0.025V ln = 0.495 V | (b) V ⎟ ⎜ ( ) 1+ 10−14 A ⎟ = 0.668 V D 10−11 A ⎠ ⎝ ⎝ ⎠
3.52
Rp = ρ p
RS = R p + Rn Rn = ρ n
Lp 0.025cm = (1Ω − cm) = 2.5Ω Ap 0.01cm 2
Ln 0.025cm = (0.01Ω − cm) = 0.025Ω An 0.01cm 2
RS = 2.53 Ω
3.53
⎛ ⎛ I ⎞ 10−3 ⎞ (a) VD' = VT ln⎜1+ D ⎟ = (0.025V )ln⎜1+ = 0.708V −16 ⎟ ⎝ IS ⎠ ⎝ 5x10 ⎠
VD = VD' + I D RS = 0.708V + 10−3 A(10Ω)= 0.718 V
(b) VD = VD' + I D RS = 0.708V + 10−3 A(100Ω)= 0.808 V
3.54
10Ω − μm2 ρ c = 10Ω − μm Ac = 1μm RC = = = 10Ω / contact Ac 1μm2 5 anode contacts and 14 cathode contacts 2
2
ρc
10Ω = 2Ω 5 10Ω = 0.71Ω Resistance of cathode contacts = 14 Resistance of anode contacts =
3.55
(a) From Fig. 3.21a, the diode is approximately 10.5 μm long x 8 μm wide. Area = 84 μm2. (b) Area = (10.5x0.13 μm) x (8x0.13μm) = 1.42 μm2.
46
3.56 (a) 5 = 10 4 I D + VD | VD = 0 I D = 0.500mA | I D = 0 VD = 5V 4.5V = 0.450 mA 10 4 Ω | VD = 0 I D = −2.00mA | I D = 0 VD = −6V
Forward biased - VD = 0.5 V I D = (b) − 6 = 3000I D + VD
−2V = −0.667 mA 3kΩ | VD = 0 I D = −1.00mA | I D = 0 VD = −3V
In reverse breakdown - VD = −4 V I D = (c) − 3 = −3000I D + VD
Reverse biased - VD = −3 V I D = 0 iD 2 mA
1 mA (a) Q-point
(c) Q-point -6
-5
-4
-3
-2
vD
-1 1
2
5
4
3
6
(b) Q-point -1 mA
-2 mA
3.57
(a) 10 = 5000I D + VD | VD = 0 I D = 2.00 mA | VD = 5 V I D = 1.00 mA 9.5V = 1.90 mA 5kΩ | VD = 0 I D = −2.00 mA | VD = −5 V I D = −1.00 mA
Forward biased - VD = 0.5V I D = (b) -10 = 5000I D + VD
−6V = −1.20 mA 5kΩ | VD = 0 I D = −1.00 mA | I D = 0 VD = −2 V
In reverse breakdown - VD = −4V I D = (c) − 2 = 2000I D + VD
Reverse biased - VD = −2 V I D = 0 iD 2 mA
(a) Q-point
1 mA (c) Q-point -6
-5
-4
-3
-2
v
-1 1
2
3
4
5
D
6
-1 mA (b) Q-point
-2 mA
47
3.58
*Problem 3.58 - Diode Circuit V 1 0 DC 5 R 1 2 10K D1 2 0 DIODE1 .OP .MODEL DIODE1 D IS=1E-15 .END
SPICE Results VD = 0.693 V ID = 0.431 μA
3.59 (a) −10 = 10 4 I D + VD | VD = 0 I D = −1.00 mA | VD = −5 V
I D = −0.500 mA
−10 − (−4)V = −0.600 mA 10kΩ | VD = 0 I D = 1.00 mA | VD = 5 V I D = 0.500 mA
In reverse breakdown - VD = −4 V I D = (b) 10 = 10 4 I D + VD
10 − 0.5V = 0.950 mA 10kΩ | VD = 0 I D = −2.00 mA | I D = 0
Forward biased - VD = 0.5 V I D = (c) − 4 = 2000I D + VD
Reverse biased - VD = −4 V I D = 0 iD 2 mA
1 mA
(b) Q-point
(c) Q-point -6
-5
-4
-3
-2
vD
-1 1
(a) Q-point -1 mA
-2 mA
48
2
3
4
5
6
VD = − 4 V
iD (A)
0.002
0.001
-7
-6
-5
-4
-3
-2
v D (V)
-1
1
2
3
4
5
6
7
-0.001
-0.002
49
3.60 R i
D
+ v
+
V
-
D
-
The load line equation: V = iD R + vD
We need two points to plot the load line.
(a) V = 6 V and R = 4kΩ: For vD = 0, iD = 6V/4 kΩ = 1.5 mA and for iD = 0, vD = 6V. Plotting this line on the graph yields the Q-pt: (0.5 V, 1.4 mA). (b) V = -6 V and R = 3kΩ: For vD = 0, iD = -6V/3 kΩ = -2 mA and for iD = 0, vD = -6V. Plotting this line on the graph yields the Q-pt: (-4 V, -0.67 mA). (c) V = -3 V and R = 3kΩ: Two points: (0V, -1mA), (-3V, 0mA); Q-pt: (-3 V, 0 mA) (d) V = +12 V and R = 8kΩ: Two points: (0V, 1.5mA), (4V, 1mA); Q-pt: (0.5 V, 1.4 mA) (e) V = -25 V and R = 10kΩ: Two points: (0V, -2.5mA), (-5V, -2mA); Q-pt: (-4 V, -2.1 mA) i (A) D
.002
Q-Point (0.5V,1.45 mA) (d)
.001
Q-Point (-3V,0 mA) -7
-6
-5
-4
-3
Q-Point (0.5V,1.4 mA)
-2
-1
1
2
Load line for (a) 3
4
5
6
7
v (V) D
(c)
Q-Point (-4V,-0.67 mA)
-.001
Load line for (b) -.002 Q-Point (-4V,-2.1 mA)
50
(e)
3.61 -9 Using the equations from Table 3.1, (f = 10-10 exp ..., etc.) VD = 0.7 V requires 12 iterations, VD = 0.5 V requires 22 iterations, VD = 0.2 V requires 384 iterations - very poor convergence because the second iteration (VD = 9.9988 V) is very bad. 3.62 Using Eqn. (3.28), ⎛i ⎞ V = iD R + VT ln⎜ D ⎟ ⎝ IS ⎠
(
)
or 10 = 10 4 iD + 0.025ln 1013 iD .
(
4 13 We want to find the zero of the function f = 10 −10 iD − 0.025ln 10 iD
iD
f
.001
-0.576
.0001
8.48
.0009
0.427
.00094
0.0259 - converged
)
3.63
⎛ I ⎞ 0.025 f = 10 −10 4 ID − 0.025ln⎜1+ D ⎟ | f ' = −10 4 − ID + IS ⎝ IS ⎠ x
function fd=current(id) fd=10-1e4*id-0.025*log(1+id/1e-13); Then: fzero('current',1) yields ans = 9.4258e-04 + 1.0216e-21i
51
3.65 The one-volt source will forward bias the diode. Load line: 1 = 10 4 I D + VD | I D = 0 VD = 1V | VD = 0 I D = 0.1mA → (50 μA, 0.5 V )
[
]
−9 Mathematical model: f = 1−10 exp(40VD )−1 + VD → (49.9 μA, 0.501 V )
Ideal diode model: ID = 1V/10kΩ = 100μA; (100μA, 0 V) Constant voltage drop model: ID = (1-0.6)V/10kΩ = 40.0μA; (40.0μA, 0.6 V) 3.66 Using Thévenin equivalent circuits yields and then combining the sources
I
1.2 k Ω 1.2 V
-
+
V
I
1k Ω
-
+
+
-
-
V
2.2 k Ω
+
+
1.5 V
-
0.3 V
(a) Ideal diode model: The 0.3 V source appears to be forward biasing the diode, so we will assume it is "on". Substituting the ideal diode model for the forward region yields 0.3V I= = 0.136 mA . This current is greater than zero, which is consistent with the diode 2.2kΩ being "on". Thus the Q-pt is (0 V, +0.136 mA). I -
V
V
on
-
+
2.2 k Ω
+
I 0.6 V
+
-
Ideal Diode:
2.2 k Ω +
0.3 V
-
0.3 V
CVD:
(b) CVD model: The 0.3 V source appears to be forward biasing the diode so we will assume it 0.3V − 0.6V = −136 μA . is "on". Substituting the CVD model with Von = 0.6 V yields I = 2.2kΩ This current is negative which is not consistent with the assumption that the diode is "on". Thus the diode must be off. The resulting Q-pt is: (0 mA, -0.3 V). -
V +
I=0
2.2 k Ω
+
52
0.3 V
(c) The second estimate is more realistic. 0.3 V is not sufficient to forward bias the diode into -15 significant conduction. For example, let us assume that IS = 10 A, and assume that the full 0.3 V appears across the diode. Then ⎡ ⎛ 0.3V ⎞ ⎤ iD = 10−15 A⎢exp⎜ ⎟ −1⎥ = 163 pA , a very small current. ⎣ ⎝ 0.025V ⎠ ⎦ 3.67 The nominal values are: ⎛ R2 ⎞ ⎛ 2kΩ ⎞ VA = 3V ⎜ ⎟ = 3V ⎜ ⎟ = 1.20V ⎝ 2kΩ + 3kΩ ⎠ ⎝ R1 + R2 ⎠
and RTHA =
2kΩ(3kΩ) R1 R2 = = 1.20kΩ R1 + R2 2kΩ + 3kΩ
⎛ R4 ⎞ ⎛ 2kΩ ⎞ 2kΩ(2kΩ) R3 R4 VC = 3V ⎜ = = 1.00kΩ ⎟ = 3V ⎜ ⎟ = 1.50V and RTHC = R3 + R4 2kΩ + 2kΩ ⎝ 2kΩ + 2kΩ ⎠ ⎝ R3 + R4 ⎠ ⎛ 1.50 −1.20 ⎞ V I Dnom = ⎜ = 136 μA ⎟ ⎝1.20 + 1.00 ⎠ kΩ For maximum current, we make the Thévenin equivalent voltage at the diode anode as large as possible and that at the cathode as small as possible. VA =
⎛ 1.65 −1.06 ⎞ V I Dmax = ⎜ = 274 μA ⎟ ⎝ 0.990 + 1.17 ⎠ kΩ For minimum current, we make the Thévenin equivalent voltage at the diode anode as small as possible and that at the cathode as large as possible.
The diode is essentially off - VD = 0.3 V and ID = 0.109 nA. This result agrees with the CVD model results. 3.69 (a)
(a) Diode is forward biased :V = 3 − 0 = 3 V | I =
3 − (−7)
= 0.625 mA 16kΩ 5 − (−5) = 0.625 mA (b) Diode is forward biased :V = −5 + 0 = −5 V | I = 16kΩ (c) Diode is reverse biased : I = 0 | V = −5 + 16kΩ(I )= −5 V | VD = −10 V
(d ) Diode is reverse biased : I = 0 | V = 7 −16kΩ(I ) = 7 V | VD = −10 V (b) (a) Diode is forward biased :V = 3 − 0.7 = 2.3 V | I =
2.3 − (−7)
= 0.581 mA 16kΩ 5 − (−4.3) (b) Diode is forward biased :V = −5 + 0.7 = −4.3 V | I = = 0.581 mA 16kΩ (c) Diode is reverse biased : I = 0 | V = −5 + 16kΩ(I )= −5 V | VD = −10 V
(d ) Diode is reverse biased : I = 0 | V = 7 −16kΩ(I ) = 7 V | VD = −10 V 3.70 (a)
3 − (−7)
= 100 μA 100kΩ 5 − (−5) (b) Diode is forward biased :V = −5 + 0 = −5 V | I = = 100 μA 100kΩ (c) Diode is reverse biased : I = 0 A | V = −5 + 100kΩ(I )= −5 V | VD = −10 V
(a) Diode is forward biased :V = 3 − 0 = 3 V | I =
(d ) Diode is reverse biased : I = 0 A | V = 7 −100kΩ(I )= 7 V | VD = −10 V (b)
54
2.4 − (−7)
= 94.0 μA 100kΩ 5 − (−4.4) (b) Diode is forward biased :V = −5 + 0.6 = −4.4 V | I = = 94.0 μA 100kΩ (c) Diode is reverse biased : I = 0 | V = −5 + 100kΩ(I ) = −5 V | VD = −10 V (a) Diode is forward biased :V = 3 − 0.6 = 2.4 V | I =
(d ) Diode is reverse biased : I = 0 | V = 7 −100kΩ(I ) = 7 V | VD = −10 V
3.71 (a) (a) D1 on, D2 on : I D2 = D1 : (409 μA, 0 V )
D1 : (0 A, − 0.452 V ) D2 : (0 A, − 0.948 V ) D3 : (1.16 mA, 0.600 V )
3.75 *Problem 3.75(a) (Similar circuits are used for the other three cases.) V1 1 0 DC 10 V2 4 0 DC 5 V3 6 0 DC -5 R1 2 3 3.3K R2 3 5 6.8K R3 5 6 2.4K D1 1 2 DIODE D2 4 3 DIODE D3 0 5 DIODE .MODEL DIODE D IS=1E-15 RS=0 .OP .END
NAME D1 D2 D3 MODEL DIODE DIODE DIODE ID 9.90E-04 -1.92E-12 7.98E-04 VD 7.14E-01 -1.02E+00 7.09E-01 NAME D1 D2 MODEL DIODE DIODE ID 4.74E-04 -4.22E-13 VD 6.95E-01 -4.21E-01 NAME D1 MODEL DIODE ID 8.79E-03 VD 7.11E-01
NAME D1 D2 D3 MODEL DIODE DIODE DIODE ID -4.28E-13 -8.55E-13 1.15E-03 VD -4.27E-01 -8.54E-01 7.18E-01 For all cases, the results are very similar to the hand analysis. 3.76
The simulation results are very close to those given in Ex. 3.8. 3.78 3.9kΩ = 6.28V | RTH = 11kΩ 3.9kΩ = 2.88kΩ 3.9kΩ + 11kΩ 6.28 − 4 IZ = = 0.792mA > 0 | (I Z ,VZ )= (0.792 mA,4 V ) 2.88kΩ
VTH = 24V
60
3.79
−6.28 = 2880I D + VD | I D = 0,VD = −6.28V | VD = 0, I D = -6
-5
-4
-3
-2
-1 v
Q-point
−6.28 = −2.18mA 2880
D
-1 mA
-2 mA
i
3.80
IS = 3.81
IS =
D
Q-Point: (-0.8 mA, -4 V)
27 − 9 9V = 1.20mA → I L < 1.20 mA | RL > = 7.50 kΩ 15kΩ 1.2mA 27 − 9 = 1.20mA | P = (9V )(1.20mA) = 10.8 mW 15kΩ
3.82
⎛ 1 VS − VZ VZ VS 1⎞ − = − VZ ⎜ + ⎟ | PZ = VZ I Z RS RL RS ⎝ RS RL ⎠ ⎛ 1 30V 1 ⎞ nom I Znom = − 9V ⎜ + ⎟ = 0.500 mA | PZ = 9V (0.500mA)= 4.5 mW 15kΩ 15kΩ 10kΩ ⎝ ⎠ ⎞ ⎛ 30V (1.05) 1 1 ⎟ = 0.796 mA I Zmax = − 9V (0.95)⎜⎜ + ⎟ 10kΩ(1.05) 15kΩ(0.95) 15kΩ 0.95 ( ) ⎠ ⎝ IZ =
3.85 Using MATLAB, create the following m-file with f = 60 Hz: function f=ctime(t) f=5*exp(-10*t)-6*cos(2*pi*60*t)+1;
Then: fzero('ctime',1/60) yields ans = 0.01536129698461 and T = (1/60)-0.0153613 = 1.305 ms. ΔT =
1 120π
ΔT =
1 120π
3.86
IT 5 2Vr | Vr = = = 0.8333V VP C 0.1(60) 2(0.8333) 6
= 1.40 ms
⎛ I ⎞ ⎛ 48.6 A ⎞ VD = nVT ln⎜1+ D ⎟ = 2(0.025V )ln⎜1+ −9 ⎟ = 1.230 V ⎝ 10 A ⎠ ⎝ IS ⎠
62
3.87
⎛ I ⎞ Von = nVT ln⎜1+ D ⎟ | VD = Von + I D RS ⎝ IS ⎠ ⎛ 100 A ⎞ VD = 1.6(0.025V )ln⎜1+ −8 ⎟ + 100 A(0.01Ω) = 1.92 V ⎝ 10 A ⎠ ⎛100 A ⎞⎛ 1ms ⎞ I ΔT = 0.92V ⎜ Pjunction ≅ Von I DC = Von P ⎟⎜ ⎟ = 2.75 W 2T ⎝ 2 ⎠⎝16.7ms ⎠ 2 4⎛ T ⎞ 2 4 ⎛16.7ms ⎞ PR ≅ ⎜ ⎟ I DC RS = ⎜ ⎟(3A) 0.01Ω = 2.00 W 3 ⎝ ΔT ⎠ 3 ⎝ 1ms ⎠ Ptotal = 4.76 W
3.88
VDC =
1⎡
T
∫ v (t )dt = T ⎢⎣(V
1 T
P
− Von )T −
0
VDC = 0.975(18V )= 17.6 V
0.05(VP − Von )⎤ TVr ⎤ ⎡ ⎥ = 0.975(VP − Von ) ⎥ = ⎢(VP − Von )− 2 ⎦ ⎢⎣ 2 ⎥⎦
3.89
1 PD = T
2 1 ΔT 2 ⎛ t ⎞ ∫ i (t )RS dt = T ∫ I P ⎜⎝1− ΔT ⎟⎠ RS dt 0 0
T
2 D
ΔT
2 ⎛ 2t t2 ⎞ I P2 RS ⎛ t2 t3 ⎞ 1− + dt = t − + ⎟ ⎟ ⎜ ⎜ ∫ ΔT ΔT 2 T ⎝ ΔT 3ΔT 2 ⎠ ⎠ 0 ⎝ 0 2 I R ⎛ ΔT ⎞ 1 2 ⎛ ΔT ⎞ PD = P S ⎜ΔT − ΔT + ⎟ = I P RS ⎜ ⎟ T ⎝ 3 ⎠ 3 ⎝ T ⎠
3.93 *Problem 3.93 VS 1 0 DC 0 AC 0 SIN(0 10 60) D1 2 1 DIODE R 2 0 0.25 C 2 0 0.5 .MODEL DIODE D IS=1E-10 RS=0 .OPTIONS RELTOL=1E-6 .TRAN 1US 80MS .PRINT TRAN V(1) V(2) I(VS) .PROBE V(1) V(2) I(VS) .END
+0.000e+000
+10.000m
+20.000m
+30.000m
I P = I dc
64
9 2 1 2T = = 923A ΔT 0.25 60 1.3ms
Time (s) +50.000m
+10.000
+5.000
+0.000e+000
-5.000
-10.000
V(2)
*REAL(Rectifier)*
SPICE Graph Results: VDC = 9.29 V, Vr = 1.05 V, IP = 811 A, ISC = 1860 A I T 9.00V 1 1 Vdc = −(VP − Von ) = −(10 −1)= −9.00V | Vr = = = 1.20V C 0.25Ω 60s 0.5F
I SC = ωCVP = 2π (60)(0.5)(10)= 1890 A | ΔT =
+40.000m
2(1.2) 1 2Vr = = 1.30ms ω VP 2π (60) 10 1
+60.000m
+70.000m
Circuit3_93b-Transient-11 (Amp)
+0.000e+000
+20.000m
+40.000m
+60.000m
+80.000m
Time (s) +100.000m
+120.000m
+140.000m
+10.000
+5.000
+0.000e+000
-5.000
-10.000
V(1)
V(2)
*REAL(Rectifier)*
SPICE Graph Results: VDC = -6.55 V, Vr = 0.58 V, IP = 150 A, ISC = 370 A Note that a significant difference is caused by the diode series resistance. 3.94
(
)
(a) Vdc = −(VP − Von )= − 6.3 2 −1 = −7.91V
(
)
2(.25) 2Vr 2T 7.91 2 1 1 = = 94.3μs | I P = I dc = = 839 A ΔT ω VP 2π (400) 6.3 2 .5 400 94.3μs 1
Simulation Results: VDC = 2981 V, Vr = 63 V The doubler circuit is effectively two half-wave rectifiers connected in series. Each capacitor is discharged by I = 3000V/3000 = 1 A for 1/60 second. The ripple voltage on each capacitor is 33.3 V. With two capacitors in series, the output ripple should be 66.6 V, which is close to the simulation result. 3.100
(
)
(a) Vdc = −(VP − Von ) = − 15 2 −1 = −20.2 V (b) C = (c) PIV ≥ 2VP = 2 ⋅15 2 = 42.4 V (e) ΔT =
( )
(d ) I surge = ωCVP = 2π (60)(1.35) 15 2 = 10800 A
2(.25) 1 20.2V ⎛ 1 ⎞ 1 2Vr T = = 0.407 ms | I P = I dc = = 1650 A ⎜ s⎟ ω VP 2π (60) 15 2 ΔT 0.5Ω ⎝ 60 ⎠ 0.407ms 1
3.101
(
)
(a) Vdc = −(VP − Von )= − 9 2 −1 = −11.7 V (b) C = (c) PIV ≥ 2VP = 2 ⋅ 9 2 = 25.5 V (e) ΔT =
I ⎛ T ⎞ 20.2V ⎛ 1 ⎞⎛ 1 ⎞ ⎜ ⎟= ⎜ ⎟⎜ ⎟ = 1.35 F Vr ⎝ 2 ⎠ 0.5Ω ⎝ 0.25V ⎠⎝120s ⎠
I ⎛ T ⎞ 11.7V ⎛ 1 ⎞⎛ 1 ⎞ ⎜ ⎟= ⎜ ⎟⎜ ⎟ = 0.780 F Vr ⎝ 2 ⎠ 0.5Ω ⎝ 0.25V ⎠⎝120s ⎠
( )
(d ) I surge = ωCVP = 2π (60)(0.780) 9 2 = 3740 A
⎞ 2(.25) 1 1 2Vr T 11.7V ⎛ 1 ⎞⎛ = = 0.526 ms | I P = I dc = ⎜ s⎟⎜ ⎟ = 958 A ω VP 2π (60) 9 2 ΔT 0.5Ω ⎝ 60 ⎠⎝ 0.407ms ⎠ 1
67
3.102 *Problem 3.102 VS1 1 0 DC 0 AC 0 SIN(0 14.14 400) VS2 0 2 DC 0 AC 0 SIN(0 14.14 400) D1 3 1 DIODE D2 3 2 DIODE C 3 0 22000U R303 .MODEL DIODE D IS=1E-10 RS=0 .OPTIONS RELTOL=1E-6 .TRAN 1US 5MS .PRINT TRAN V(1) V(2) V(3) I(VS1) .PROBE V(1) V(2) V(3) I(VS1) .END
20V
10V
vS
0V
-10V
vO
Time -20V 0s
1.0ms
2.0ms
3.0ms
4.0ms
Simulation Results: VDC = -13.4 V, Vr = 0.23 V, IP = 108 A VDC = VP − Von = 10 2 − 0.7 = 13.4 V | Vr = ΔT =
1 120π
I P = I dc
2Vr 1 = VP 120π
2(0.254) 14.1
1 13.4 1 = 0.254 V 3 800 22000μF
= 0.504 ms
1 T 13.4V 1 = s = 150 A 3Ω 60 0.504 ms ΔT
Simulation with RS = 0.02 Ω. Circuit3_102-Transient-15 +0.000e+000
+2.000m
+4.000m
+6.000m
+8.000m
Time (s) +10.000m
+12.000m
+14.000m
+15.000
+10.000
+5.000
+0.000e+000
-5.000
-10.000
-15.000
V(1)
V(2)
*REAL(Rectifier)*
Simulation Results: VDC = -12.9 V, Vr = 0.20 V, IP = 33.3 A, ISC = 362 A. RS results in a significant reduction in the values of IP and ISC.
68
5.0ms
3.103 (a) C =
1 ⎛ 1s ⎞⎛ 30 A ⎞ VP − Von 1 T = ⎜ ⎟⎜ ⎟ = 3.03 F (b) PIV = 2VP = 2(3.3 + 1)V = 8.6 V R 0.025 ⎝120 ⎠⎝ 3.3V ⎠ Vr 3.3 + 1
⎞ ⎛ 1 ⎞⎛ T 1 = 30 A⎜ s ⎟⎜ ⎟ = 962 A | I surge = ωCVP = 2π (60 / s)(3.03F )(4.3V )= 4910 A ΔT ⎝ 60 ⎠⎝ 0.520ms ⎠
3.104
(a) C =
I T 1 1 = = 139 μF Vr 2 3000(0.01) 2 ⋅120
(c) VS = I P = I dc
3000
= 2120 V
(d ) ΔT =
2
1
2
ω
⎛ 1 ⎞⎛ ⎞ 1 T = 1⎜ s ⎟⎜ ⎟ = 44.4 A ΔT ⎝ 60 ⎠⎝ 0.375ms ⎠
(b) PIV ≥ 2VP = 6000 V
Vr 1 = 2(0.01) = 0.375 ms VP 2π (60) (e) I surge = ωCVP = 2π (60 / s)(139μF )(3000V )= 157 A
3.105 The circuit is behaving like a half-wave rectifier. The capacitor should charge during the first 1/2 cycle, but it is not. Therefore, diode D1 is not functioning properly. It behaves as an open circuit. 3.106
(
)
(a) Vdc = −(VP − 2Von )= − 15 2 − 2 = −19.2 V (b) C = (c) PIV ≥ VP = 15 2 = 21.2 V
( )
(d ) I surge = ωCVP = 2π (60 / s)(1.28F ) 15 2 = 10200 A
⎞ 2(.25) 1 2Vr T 19.2V ⎛ 1s ⎞⎛ 1 = = 0.407 ms | I P = I dc = ⎜ ⎟⎜ ⎟ = 1570 A ω VP 2π (60) 15 2 ΔT 0.5Ω ⎝ 60 ⎠⎝ 0.407ms ⎠ 1
(e) ΔT = 3.107
(a) C = (c) VS = I P = I dc
I ⎛ T ⎞ 19.2V ⎛ 1 ⎞⎛ 1 ⎞ s⎟ = 1.28 F ⎜ ⎟= ⎜ ⎟⎜ Vr ⎝ 2 ⎠ 0.5Ω ⎝ 0.25V ⎠⎝ 120 ⎠
I ⎛ T ⎞ 19.2V ⎛ 1 ⎞⎛ 1 ⎞ ⎜ ⎟= ⎜ ⎟⎜ ⎟ = 1.28 F Vr ⎝ 2 ⎠ 0.5Ω ⎝ 0.25⎠⎝120 ⎠
(
)
(d ) I surge = ωCVP = 2π (60 / s)(1.28F ) 15V 2 = 10200 A
⎞ 2(.25) 1 2Vr T 19.2V ⎛ 1 ⎞⎛ 1 = = 0.407 ms | I P = I dc = ⎜ s ⎟⎜ ⎟ = 1570 A ΔT 0.5Ω ⎝ 60 ⎠⎝ 0.407ms ⎠ ω VP 2π (60) 15 2 1
3.112 3.3-V, 15-A power supply with Vr ≤ 10 mV. Assume Von = 1 V.
Rectifier Type
Half Wave
Full Wave
Full Wave Bridge
Peak Current
533 A
266 A
266 A
PIV
8.6 V
8. 6 V
5.3 V
Filter Capacitor
25 F
12.5 F
12.5 F
(i) The large value of C suggests we avoid the half-wave rectifier. This will reduce the cost and size of the circuit. (ii) The PIV ratings are all low and do not indicate a preference for one circuit over another. (iii) The peak current values are lower for the full-wave and full-wave bridge rectifiers and also indicate an advantage for these circuits. (iv) We must choose between use of a center-tapped transformer (full-wave) or two extra diodes (bridge). At a current of 15 A, the diodes are not expensive and a four-diode bridge should be easily found. The final choice would be made based upon cost of available components. 3.113 200-V, 3-A power supply with Vr ≤ 4 V. Assume Von = 1 V.
Rectifier Type
Half Wave
Full Wave
Full Wave Bridge
Peak Current
189 A
94.3 A
94.3 A
PIV
402 V
402 V
202 V
12,500 μF
6250 μF
6250 μF
Filter Capacitor
(i) The the half-wave rectifier requires a larger value of C which may lead to more cost. (ii) The PIV ratings are all low enough that they do not indicate a preference for one circuit over another. (iii) The peak current values are lower for the full-wave and full-wave bridge rectifiers and also indicate an advantage for these circuits. (iv) We must choose between use of a center-tapped transformer (full-wave) or two extra diodes (bridge). At a current of 3 A, the diodes are not expensive and a four-diode bridge should be easily found. The final choice would be made based upon cost of available components.
71
3.114 3000-V, 1-A power supply with Vr ≤ 120 V. Assume Von = 1 V.
Rectifier Type
Half Wave
Full Wave
Full Wave Bridge
Peak Current
133 A
66.6 A
66.6 A
PIV
6000 V
6000 V
3000 V
Filter Capacitor
41.7 μF
20.8 μF
20.8 μF
(i) A series string of multiple capacitors will normally be required to achieve the voltage rating. (ii) The PIV ratings are high, and the bridge circuit offers an advantage here. (iii) The peak current values are lower for the full-wave and full-wave bridge rectifiers but neither is prohibitively large. (iv) We must choose between use of a center-tapped transformer (full wave) or extra diodes (bridge). With a PIV of 3000 or 6000 volts, multiple diodes may be required to achieve the require PIV rating. 3.115 5V 5 − VD 5 − 0.6 = 5 mA | I F = = = 4.4 mA 1kΩ 1kΩ 1kΩ ⎛ −3 − 0.6 4.4mA ⎞ Ir = = −3.6 mA | τ S = (7ns) ln⎜1− ⎟ = 5.59 ns 1kΩ ⎝ −3.6mA ⎠
In case (a), the charge in the diode does not have time to reach the steady-state value given by Q = (1mA)(50ns) = 50 pC. At most, only 1mA(7.5ns) = 7.5 pC can be stored in the diode. Thus is turns off more rapidly than predicted by the storage time formula. It should turn off in approximately t = 7.5pC/3mA = 2.5 ns which agrees with the simulation results. In (b), the diode charge has had time to reach its steady-state value. Eq. (3.103) gives: (50 ns) ln (1-1mA/(3mA)) = 14.4 ns which is close to the simulation result. 3.119
[
]
IC = 1−10−15 exp(40VC )−1 A | For VC = 0, I SC = 1A VOC =
1 ⎛ 1 ⎞ ln⎜1+ −15 ⎟ = 0.864 V 40 ⎝ 10 ⎠
[
[
]]
P = VC IC = VC 1−10−15 exp(40VC )−1
[
]
dP = 1−10−15 exp(40VC )−1 − 40x10−15 VC exp(40VC ) = 0 dVC Using the computer to find VC yields VC = 0.7768 V, IC = 0.9688 A, and Pmax = 7.53 Watts 3.120 (a) For VOC, each of the three diode teminal currents must be zero, and 1 VOC = VC1 + VC 2 + VC 3 = V ln(1.05x1015 )+ ln(1.00x1015 )+ ln(0.95x1015 ) = 2.59 V 40 (b) For ISC, the external currents cannot exceed the smallest of the short circuit current
[
]
of the individual diodes. Thus, ISC = min[1.05A,1.00A,0.95A] = 0.95 A Note that diode three will be reversed biased in part (b). Using the computer to find VC yields VC = 0.7768 V, IC = 0.9688 A, and Pmax = 7.53 Watts 3.121 hc λ= E
) = 1.11 μm - far infrared 1.12eV (1.602x10 j / eV ) 6.625x10 J − s(3x10 m / s) = 0.875 μm - near infrared (b) λ = 1.42eV (1.602x10 j / eV ) (a) λ =
(
6.625x10−34 J − s 3x108 m / s −19
−34
8
−19
74
CHAPTER 4 4.1 (a) VG > VTN corresponds to the inversion region (b) VG 0 → enhancement - mode transistor 395 (4 − VTN ) μA = 2 → VTN = 1.5 V → K n = 125 140 (3 − VTN ) V2 2
78
4.19 Using the parameter values from problem 4.22: 800uA
VGS = 5 V
VGS = 4.5 V
Drain Current (A)
600uA
VGS = 4 V
400uA
VGS = 3.5 V 200uA
VGS = 3 V VGS = 2.5 V VGS = 2 V
0 A 0V
1.0V
2.0V
3.0V
4.0V
5.0V
6.0V
Drain-Source Voltage (V)
4.20 (a) For VGS = 0, VGS ≤ VTN and ID = 0 (b) For VGS = 1 V, VGS = VTN and ID = 0
(c ) VGS − VTN ID =
mA 375 μA ⎛ 5μm ⎞ μA ⎛ 5μm ⎞ 2 2 ' W = 375 2 ⎜ ⎟ = 3.75 2 ⎟(2 −1) V = 1.88 mA | K n = K n 2 ⎜ V 2 V ⎝ 0.5μum ⎠ L V ⎝ 0.5um ⎠
(d) VGS − VTN ID =
= 2 -1 =1V and VDS = 3.3 | VDS > (VGS − VTN ) so the saturation region is correct
= 3 -1 = 2V and VDS = 3.3 | VDS > (VGS − VTN ) so the saturation region is correct
375 μA ⎛ 5μm ⎞ 2 2 ⎟(3 −1) V = 7.50 mA 2 ⎜ 2 V ⎝ 0.5μm ⎠
4.21 (a) For VGS = 0, VGS < VTN and ID = 0 (b) For VGS = 1 V, VGS < VTN and ID = 0
(c ) VGS − VTN ID =
200 μA ⎛10μm ⎞ μA ⎛ 10μm ⎞ mA 2 2 ' W V = 250 μ A | K = K = 200 2 −1.5 ⎜ ⎟ ⎟ = 2.00 2 ( ) n n 2 2 ⎜ 2 V ⎝ 1um ⎠ L V ⎝ 1um ⎠ V
(d) VGS − VTN ID =
= 2 -1.5 = 0.5V and VDS = 4 | VDS > (VGS − VTN ) so the saturation region is correct
= 3 -1.5 =1.5V and VDS = 4 | VDS > (VGS − VTN ) so the saturation region is correct
200 μA ⎛10μm ⎞ 2 2 ⎟(3 −1.5) V = 2.25 mA 2 ⎜ 2 V ⎝ 1μm ⎠
79
4.22 (a) VGS - VTN = 2 - 0.75 = 1.25 V and VDS = 0.2 V. VDS < VGS - VTN so the transistor is operating in the triode region.
⎛ V ⎞ 0.2 ⎞ W⎛ μA ⎞⎛10 ⎞⎛ ⎜VGS − VTN − DS ⎟VDS = ⎜200 2 ⎟⎜ ⎟⎜ 2 − 0.75 − ⎟0.2 = 460 μA ⎝ 2 ⎠ 2 ⎠ L⎝ V ⎠⎝ 1 ⎠⎝ (b) VGS - VTN = 2 - 0.75 = 1.25 V and VDS = 2.5 V. VDS > VGS - VTN so the transistor is operating in the saturation region. ⎛ 200 μA ⎞⎛10 ⎞ K' W 2 2 ID = n ⎟(2 − 0.75) = 1.56 mA (VGS − VTN ) = ⎜ 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 2 L (c) VGS < VTN so the transistor is cutoff with ID = 0. ⎛ 300 ⎞ ID ∝ K n' so (a) ID = ⎜ (d) ⎟460μA = 690μA (b) ID = 2.34 mA (c) ID = 0 ⎝ 200 ⎠ ID = K n'
4.23 (a) VGS - VTN = 4 V, VDS = 6 V. VDS > VGS - VTN --> Saturation region
(b) VGS < VTN --> Cutoff region (c) VGS - VTN = 1 V, VDS = 2 V. VDS > VGS - VTN --> Saturation region (d) VGS - VTN = 0.5 V, VDS = 0.5 V. VDS = VGS - VTN --> Boundary between triode and saturation regions (e) The source and drain of the transistor are now reversed because of the sign change in VDS. Assuming the voltages are defined relative to the original S and D terminals as in Fig. P4.11(b), VGS = 2 - (-0.5) = 2.5 V, VGS - VTN = 2.5 - 1 = 1.5 V, and VDS = 0.5 V --> triode region (f) The source and drain of the transistor are again reversed because of the sign change in VDS. Assuming the voltages are defined relative to the original S and D terminals as in Fig. P4.11(b), VGS = 3 - (-6) = 9 V, VGS - VTN = 9 - 1 = 8.0 V, and VDS = 6 V --> triode region D --> 'S' -
D --> 'S' G
G
6.0 V
0.5 V +
+ 2V (e)
+ S --> 'D' VG'S' = +2.5 V VD'S' = +0.5 V
80
3V (f)
+ S --> 'D' V G'S' = +9.0 V V D'S' = +6.0 V
4.24 (a) VGS - VTN = 2.6 V, VDS = 3.3 V. VDS > VGS - VTN --> Saturation region
(b) VGS < VTN --> Cutoff region (c) VGS - VTN = 1.3 V, VDS = 2 V. VDS > VGS - VTN --> Saturation region (d) VGS - VTN = 0.8 V, VDS = 0.5 V. VDS < VGS - VTN --> triode region (e) The source and drain of the transistor are now reversed because of the sign change in VDS. Assuming the voltages are defined relative to the original S and D terminals as in Fig. 4.54(b), VGS = 2 - (-0.5) = 2.5 V, VGS - VTN = 2.5 – 0.7 = 1.8 V, and VDS = 0.5 V --> triode region (f) The source and drain of the transistor are again reversed because of the sign change in VDS. Assuming the voltages are defined relative to the original S and D terminals as in Fig. 4.54(b), VGS = 3 - (-3) = 6 V, VGS - VTN = 6 – 0.7 = 5.3 V, and VDS = 3 V --> triode region 4.25
R
R 2
4
D
V
DD
G B
+ -
S R
R
1
3
4.26 +V DD
D G
I B
S
+V DD
D D
G
B
G
I B
S S
D
D
B
B
G
G
S
S
(a)
(b)
4.27 81
VDS = 3.3V, VGS – VTN = 1.3 V; VDS > VGS - VTN so the transistor is saturated.
(a) gm = K n (VGS − VTN ) = 250
μA ⎛ 20μm ⎞ ⎜ ⎟(2 − 0.7) = 6.50 mS V 2 ⎝ 1μm ⎠
(b) gm = K n (VGS − VTN ) = 250
μA ⎛ 20μm ⎞ ⎜ ⎟(3.3 − 0.7) = 13.0 mS V 2 ⎝ 1μm ⎠
4.28
(a) gm =
ΔiD 760 −140 μA = = 310 μS | As a check, we can use the results from Problem 4.22. ΔvGS 5−3 V
4.32 (a) The transistor is saturated by connection. 12V − VGS 100x10−6 ⎛10 ⎞ A 2 ID = = ⎜ ⎟ 2 (VGS − 0.75V ) 4 ⎝ 1 ⎠V 5x10 Ω 2 31.25VGS2 − 45.88VGS + 5.58 = 0 VGS = 0.0588V , 1.401V ⇒ VGS = 1.401 V since VGS must exceed the threshold voltage. 12 −1.401 100x10−6 ⎛10 ⎞ A 2 = 212 μ A Checking : I = ⎜ ⎟ 2 (1.401− 0.75V ) = 212 μA D 4 ⎝ 1 ⎠V 5x10 2 −6 12V − VGS 1000x10 A 2 = V − 0.75V ) (1+ 0.02VGS ) (b) ID = 4 2 ( GS 5x10 Ω 2 V ID =
Starting with the solution from part (a) and solving iteratively yields VGS = 1.3925 V and IDS = 212 μA, essentially no change 4.33 (a) Since VDS = VGS and VTN > 0 for both transistors, both devices are saturated. K n' W K n' W 2 2 I = V − V and I = ( GS1 TN ) (VGS 2 − VTN ) . Therefore D1 D2 2 L 2 L From the circuit, however, ID2 must equal ID1 since IG = 0 for the MOSFET: K n' W K n' W 2 2 I = ID1 = ID 2 or (VGS1 − VTN ) = (VGS 2 − VTN ) 2 L 2 L which requires VGS1 = VGS2. Using KVL:
VDD = VDS1 + VDS 2 = VGS1 + VGS 2 = 2VGS 2 V VGS1 = VGS 2 = DD = 5V 2 ' K W 100 μA 10 2 2 I= n (VGS1 − VTN ) = (5 − 0.75) V 2 = 9.03 mA 2 2 V 1 2 L (b) The current simply scales by a factor of two (see last equation above), and ID = 18.1 mA. (c) For this case,
83
K n' W K n' W 2 2 V − V 1 + λ V and I = ( GS1 TN ) ( (VGS 2 − VTN ) (1 + λVDS2 ). DS1 ) D2 2 L 2 L Since VGS = VDS for both transistors K n' W K n' W 2 2 ID1 = (VGS1 − VTN ) (1 + λVGS1 ) and ID 2 = (VGS 2 − VTN ) (1 + λVGS2 ) 2 L 2 L and ID1 = ID2 = I K' W K n' W 2 2 (VGS1 − VTN ) (1 + λVGS1 ) = n (VGS 2 − VTN ) (1 + λVGS2 ) 2 L 2 L which again requires VGS1 = VGS2 = VDD/2 = 5V. K' W 100 μA 10 2 2 I= n (VGS1 − VTN ) (1+ λVDS ) = (5 − 0.75) V 2 (1+ (.04 )5) = 10.8 mA 2 2 L 2 V 1 ID1 =
4.34 (a) Since VDS = VGS and VTN > 0 for both transistors, both devices are saturated (“by
connection”).
K n' ⎛ W ⎞ K n' ⎛ W ⎞ 2 2 ID1 = ⎜ ⎟ (VGS1 − VTN ) and ID 2 = ⎜ ⎟ (VGS 2 − VTN ) . Therefore 2 ⎝ L ⎠1 2 ⎝ L ⎠2 From the circuit, however, ID2 must equal ID1 since IG = 0 for the MOSFET: K n' ⎛ 10 ⎞ K n' ⎛ 40 ⎞ 2 2 V − V = I = ID1 = ID 2 or ⎜ ⎟( GS1 TN ) ⎜ ⎟(VGS 2 − VTN ) 2 ⎝1⎠ 2 ⎝1⎠ which requires VGS1 = 2VGS2 - VTN. Using KVL: VDD = VDS1 + VDS 2 = VGS 2 + VGS1 = 3VGS 2 − VTN V + VTN 10 + 0.75 VGS 2 = DD = = 3.583V VGS1 = 6.417 3 3 100 μA 10 K' W 2 2 I= n (VGS1 − VTN ) = (6.417 − 0.75) V 2 = 16.1 mA 2 2 V 1 2 L 100 μA 40 2 Checking : I = (3.583 − 0.75) V 2 = 16.1 mA which agrees. 2 2 V 1 (b) For this case with VGS = VDS for both transistors and ID1 = ID2, K' ⎛W ⎞ K' ⎛W ⎞ 2 2 ID1 = n ⎜ ⎟ (VGS1 − VTN ) (1 + λVGS1 ) and ID 2 = n ⎜ ⎟ (VGS 2 − VTN ) (1 + λVGS2 ) 2 ⎝ L ⎠1 2 ⎝ L ⎠2
where VGS2 = VDD – VGS1. Therefore, K ' ⎛ 40 ⎞ K n' ⎛10 ⎞ 2 2 ⎜ ⎟(VGS1 − VTN ) (1 + λVGS1 ) = n ⎜ ⎟(10 − VGS1 − VTN ) (1 + λ(10 − VGS1 )) 2 ⎝1⎠ 2 ⎝1⎠ VGS1 = 6.3163, VGS2 = 3.6837, ID1 = 20.4 mA, Checking: ID2 = 20.4 mA which agrees.
84
4.35 (a) Since VDS = VGS and VTN > 0 for both transistors, both devices are saturated (“by
connection”).
K n' ⎛ W ⎞ K n' ⎛ W ⎞ 2 2 V − V and I = ⎜ ⎟ ⎜ ⎟ (VGS 2 − VTN ) . ( ) GS1 TN D2 Therefore 2 ⎝ L ⎠1 2 ⎝ L ⎠2 From the circuit, however, ID2 must equal ID1 since IG = 0 for the MOSFET: K n' ⎛ 25 ⎞ K n' ⎛12.5 ⎞ 2 2 I = ID1 = ID 2 or ⎜ ⎟(VGS1 − VTN ) = ⎜ ⎟(VGS 2 − VTN ) 2 ⎝1⎠ 2 ⎝ 1 ⎠ Solving for VGS2 yields: VGS 2 = 2VGS1 − 2 −1 VTN ID1 =
100 μA ⎛ 25 ⎞ K n' W 2 2 2 ⎟(4.271− 0.75) V = 15.5 mA (VGS1 − VTN ) = 2 ⎜ 2 V ⎝1⎠ 2 L 100 μA ⎛ 12.5 ⎞ 2 2 Checking : I = ⎟(5.729 − 0.75) V = 15.5 mA - agrees. 2 ⎜ 2 V ⎝ 1 ⎠ (b) For this case with VGS = VDS for both transistors and ID1 = ID2, K' ⎛W ⎞ K' ⎛W ⎞ 2 2 ID1 = n ⎜ ⎟ (VGS1 − VTN ) (1 + λVGS1 ) and ID 2 = n ⎜ ⎟ (VGS 2 − VTN ) (1 + λVGS2 ) 2 ⎝ L ⎠1 2 ⎝ L ⎠2 I=
where VGS2 = VDD – VGS1. Therefore, K n' ⎛ 40 ⎞ K n' ⎛10 ⎞ 2 2 ⎜ ⎟(VGS1 − VTN ) (1 + λVGS1 ) = ⎜ ⎟(10 − VGS1 − VTN ) (1 + λ(10 − VGS1 )) 2 ⎝1⎠ 2 ⎝1⎠ VGS1 = 4.3265 V, VGS2 = 5.6735 V, ID1 = 19.4 mA, Checking: ID2 = 19.4 mA – both agree 4.36 VGS - VTN = 5 - (-2) = 7 V > VDS = 6 V so the transistor is operating in the triode region. 6⎞ −6 ⎛ (a) ID = 250x10 ⎜5 − (−2) − ⎟6 = 6.00 mA ⎝ 2⎠ (b) Our triode region model is independent of λ, so ID = 6.00 mA. 4.37 Since VDS = VGS, and VTN < 0 for an NMOS depletion mode device, VGS - VTN will be greater than VDS and the transistor will be operating in the triode region.
85
4.38 (a) VDS = 6V | VGS − VTN = 0 − (−3) = 3V so the transistor is saturated 2 Kn 250 μA 2 0 − (−3V )] = 1.13 mA (VGS1 − VTN ) = 2 [ 2 V 2 2 250 μA 0 − (−3V )] (1+ 0.025(6)) = 1.29 mA (b) ID = 2 [ 2 V
ID =
4.39
D G
+10 V
-10 V
100 k Ω
100 k Ω
I DS
S G
W = 10 L 1 S
(a)
I DS W = 10 L 1
D (b)
(a) If the transistor were saturated, then 100x10−6 ⎛ 10 ⎞ 2 ID = ⎜ ⎟(−2) = 2.00 mA ⎝1⎠ 2 but this would require a power supply of greater than 200 V (2 mA x 100 kΩ). Thus the transistor must be operating in the triode region. 10V − VDS VDS ⎞ −3 ⎛ = 10 0 − −2 − ⎜ ⎟VDS ( ) ⎝ 10 5 Ω 2 ⎠ 10 − VDS = 50VDS (4 − VDS ) and VDS = 0.0504V using the quadratic equation. ⎛ 0.0504 ⎞ 10V − VDS ID = 10−3 ⎜2 − = 99.5 μA ⎟0.0504 = 99.5 μA Checking : ⎝ 2 ⎠ 10 5 Ω (b) For R = 50 kΩ and W/L = 20/1, ⎛ 10V − VDS V ⎞ = 2x10−3⎜ 0 − (−2) − DS ⎟VDS 4 ⎝ 5x10 Ω 2 ⎠ 10 − VDS = 50VDS (4 − VDS ), the same as part (a). ⎛ 0.0504 ⎞ 10V − VDS ID = 2x10−3 ⎜2 − = 199 μA ⎟0.0504 = 199 μA Checking : ⎝ 5x10 4 Ω 2 ⎠ (c) In this circuit, the drain and source terminals of the transistor are reversed because of the power supply voltage, and the current direction is also reversed. However, now VDS = VGS and since the transistor is a depletion-mode device, it is still operating in the triode region.
86
⎛ 10V − VDS V ⎞ = 1000x10−6 ⎜VDS − (−2) − DS ⎟VDS 5 ⎝ 10 Ω 2 ⎠ 10 − VDS = 50VDS (4 + VDS ) and VDS = 0.04915V using the quadratic equation. ⎛ 0.04915 ⎞ 10V − VDS ID = 10−3 ⎜0.04915 − (−2) − = 99.5 μA ⎟0.04915 = 99.5 μA Checking : ⎝ 10 5 Ω 2 ⎠ (d) In this circuit, the drain and source terminals of the transistor are reversed because of the power supply voltage, and the current direction is also reversed. However, now VDS = VGS and since the transistor is a depletion-mode device, it is still operating in the triode region. ⎛ 10V − VDS V ⎞ = 2000x10−6⎜VDS − (−2) − DS ⎟VDS 4 ⎝ 5x10 Ω 2 ⎠ 10 − VDS = 50VDS (4 + VDS ) Same as part (c). VDS = 0.04915V using the quadratic equation. ⎛ 0.04915 ⎞ 10V − VDS ID = 10−3 ⎜0.04915 − (−2) − = 99.5 μA ⎟0.04915 = 99.5 μA Checking : ⎝ 10 5 Ω 2 ⎠ 4.40 See figures in previous problem but use W/L = 20/1. 25x10−6 ⎛ 20 ⎞ 2 I = ⎜ ⎟(−1) = 250 μA but this would require (a) If the transistor were saturated, then D 2 ⎝1⎠ a power supply of greater than 25 V. Thus the transistor must be operating in the triode region.
⎛ 20 ⎞⎛ 10V − VDS V ⎞ = 100x10−6 ⎜ ⎟⎜0 − (−1) − DS ⎟VDS 5 ⎝ 1 ⎠⎝ 10 Ω 2 ⎠ 10 − VDS = 100VDS (2 − VDS ) and VDS = 0.05105V using the quadratic equation. ⎛ 0.05105 ⎞ 10 − 0.0510 ID = 2.00x10−3 ⎜1− V = 99.5 μA ⎟0.05105 = 99.5 μA Checking : ⎝ 2 ⎠ 10 5 Ω (b) In this circuit, the drain and source terminals of the transistor are reversed because of the power supply voltage, and the current direction is also reversed. However, now VDS = VGS and since the transistor is a depletion-mode device, it is still operating in the triode region. ⎛ 20 ⎞⎛ V ⎞ VDS = 10 − (10 5 )(100x10−6 )⎜ ⎟⎜VDS − (−1) − DS ⎟VDS ⎝ 1 ⎠⎝ 2 ⎠ ⎛ V ⎞ VDS = 10 − 200VDS ⎜1+ DS ⎟ and VDS = 0.04858V using the quadratic equation. ⎝ 2 ⎠ ⎛ 0.04858 ⎞ 10 - 0.04858 V = 99.5 μA ID = 2000x10−6 ⎜1+ ⎟0.04858 = 99.5 μA Checking : ⎝ Ω 2 ⎠ 10 5
4.45 Using trial and error with a spreadsheet yielded:
VTO = 0.74V γ = 0.84 V 2φ F = 0.87V RMS Error = 51.9 mV
88
4.46
−14 3.9εo ⎛ cm 2 ⎞ 3.9(8.854 x10 F /cm) (a) K = μ p C = μ p = μp = ⎜200 ⎟ Tox Tox V − sec ⎠ 50x10−9 m(100cm /m) ⎝ F μA K 'p = 13.8x10−6 = 13.8 2 V − sec V μA 50nm μA (b) Scaling the result from Part (a) yields: K n' = 13.8 2 = 34.5 2 V 20nm V μA 50nm μA = 69.0 2 (c) K n' = 13.8 2 V 10nm V μA 50nm μA = 138 2 (d) K n' = 13.8 2 V 5nm V ' p
εox
" ox
4.47
The pinchoff points and threshold voltage can be estimated directly from the graph: e. g. VGS = -3 V curve gives VTP = 2.5 - 3 = - 0.5 V or from the VGS = -5 V curve gives VTP = 4.5 - 5 = 0.5 V. Alternately, choosing two points in saturation, say ID = 1.25 mA for VGS = -3 V and ID = 4.05 mA for VGS = -5 V: ID1 (VGS1 − VTP ) = or ID 2 (VGS 2 − VTP )
1.25 (−3 − VTP ) = 4.05 (−5 − VTP )
Solving for VTP yields : 0.8VTP = −0.4V and VTP = −0.500V . Solving for K p : K p =
2ID
(VGS − VTP )
2
=
2(1.25mA)
(−3 + 0.5)
2
= 0.400
Kp
400
μA
mA W V 2 = 10 | = = μA V2 L K 'p 1 40 2 V
4.48 Using the values from the previous problem PMOS Output Characteristics 0.0045 0.004 0.0035 -2 V -3 V -3.5 V -4 V -4.5 V -5 V
1 = 11.8 Ω ⎛ −6 200 ⎞ 100x10 ⎜ ⎟(5 − 0.75) ⎝ 1 ⎠ ⎛W ⎞ K' ⎛W ⎞ 500 Checking : ⎜ ⎟ = n' ⎜ ⎟ = 2.5(200) = ⎝ L ⎠ p K p ⎝ L ⎠n 1 (b) Ron =
4.53 +18 V R
R4
2
R S VDD B
G
+ -
S B
D G R
1
R
D 3
(a)
(b)
4.54 (a) For VIN = 0, the NMOS device is on with VGS = 5 and VSB = 0, and the PMOS transistor is off with VGS = 0, VO = 0, and VSB = 0. 1 Ron = = 235 Ω −6 (100x10 )(10)(5 − 0.75)
(b) For VIN = 5V, the NMOS device is off with VGS = 0, and the PMOS transistor is on with VGS = -5V, VO = 5V, and VSB = 0. 1 Ron = = 235 Ω −6 (40x10 )(25)(−5 + 0.75) 4.55 Ron ≤
0.1V 0.5A ID A = 0.2Ω K p = = = 0.629 2 0.5A V (VGS − VTP − 0.5VDS )VDS [−10V − (−2V ) − 0.5(−0.1V )](−0.1V )
4.56 VTP = −0.75 − 0.5
( 4 + 0.6 −
)
0.6 = −1.44V
VGS - VTP = −1.5 − (−1.44 ) = −0.065 | VDS = −4V ⇒ Saturation region ID =
2 40x10−6 A ⎛ 25 ⎞ ⎟[−1.5 − (−1.44 )] = 1.80 μA 2⎜ V ⎝1⎠ 2
4.58 The PMOS transistor could be either an enhancement-mode or a depletion-mode device depending upon the specific values of R1, R2 and R4. Thus an enhancement device with VTP < 0 is correct and the symbol is correct. 4.59 If this PMOS transistor is conducting, then its threshold voltage must be greater than zero and it is a depletion-mode device. The symbol is that of an enhancement-mode device and is incorrect. 4.60 +18 V R4
R2
R S
G
VDD
+
D
G R1
R
3
D
(a)
(b)
4.61 RD
R2
75 k Ω
1.5 M Ω
VDD
D
+
G S
-3 V
R1 R
S
1 MΩ
92
39 k Ω
S
10 V
4.62 R
D
75 k Ω R
EQ
600 k Ω V EQ
VDD
D
G
S
+ -5 V 10 V
RS 4V
39 k Ω
93
4.63
n+
22 λ
Metal Polysilicon 12 λ
[(2x20)/(12x22)]= 0.152 or 15.2%
4.64
n+
14 λ
Metal
Polysilicon 18 λ
94
[2x10/(18x14)]= 0.079 or 7.9%
4.65
Metal 12 λ
n+ Polysilicon 12 λ
(2x10/122)= 0.139 or 13.9%
4.66
Metal
12 λ
n+
Polysilicon 14 λ
[2x10/(14x12)] = 0.119 or 11.9%
95
4.67
(a)
" Cox =
εox Tox
=
⎛ ⎝
(3.9)⎜8.854 x10−14 −6
5x10 cm
F⎞ ⎟ cm ⎠
= 6.906x10−8
F cm 2
⎛ F ⎞ " CGC = Cox WL = ⎜6.906x10−8 2 ⎟(20x10−4 cm)(2x10−4 cm)= 27.6 fF ⎝ cm ⎠ F " = 1.73 x 10−7 2 | CGC = 69.1 fF (b) Cox cm F " = 3.45 x 10−7 2 | CGC = 138 fF (c) Cox cm F " = 7.90 x 10−7 2 | CGC = 276 fF (d) Cox cm 4.68 " Cox =
4.77 KP = K 'n = 50U VTO = VTN = 1 V L = 0.5U W = 2.5U LAMBDA = 0 4.78 KP = K 'n = 10U VTO = VTN = 1 V L = 0.6U W = 1.5U LAMBDA = 0 4.79 KP = K 'p = 10U VTO = VTP = −1 V L = 0.5U Using the - 3 - V curve, K P = 2
50μA
[-3 - (-1)]
2
= 25
μA V2
W = 1.25U LAMBDA = 0
4.80 KP = K 'n = 25U VTO = VTN = 1 V L = 0.6U W = 0.6U LAMBDA = 0
98
NMOS i-v Characteristics for Load-Line Problems
800 5V
Drain Current (uA)
600
400
4V
200 3V
2V 0
0
1
2
3
4
5
6
Drain Voltage (V)
99
4.81
For VDS = 0, ID =
4V = 0.588mA. For ID = 0,VDS = 4V . 6.8kΩ
Also, VGS = 4V. From the graph, the transistor is operating below pinchoff in the triode region and the Q-point is Q-point: (350 μA, 1.7V) 800 5V
Drain Current (uA)
600
Q-point (4.82) 400
4V
Q-point (4.81)
200
3V
2V 0
0
1
2
3
4
5
6
Drain Voltage (V)
4.82
For VDS = 0, ID =
5V = 0.602mA. For ID = 0,VDS = 5V . 8.3kΩ
For VGS = 5V, the Q-point is (450 μA, 1.25 V). From the graph in Prob. 4.81, the transistor is operating below pinchoff in the triode region. 4.83 800 5V
Drain Current (uA)
600
Q-point (4.84) 400
4V
Q-point (4.83)
200
3V
2V 0
0
1
2
3
Drain Voltage (V)
100
4
5
6
VDD = 3V | 6 =10 4 ID +V DS | VDS = 0, ID = 0.6mA | ID = 0, VDS = 6V 2 From the graph, Q-pt: (140 μA, 4.6V) in the saturation region. VGS =
4.84
VDD = 4V | 8 =10 4 ID +V DS | VDS = 6, ID = 0.2mA | VDS = 0, ID = 0.8mA 2 See graph for Problem 4.83: Q-pt: (390 μA, 4.1 V) in saturation region. VGS =
70.5VGS2 −139VGS + 62.88 = 0 → VGS = 1.269V and ID = 54.3 μA VDS = 12 − 71x10 3 ID = 8.15 V | VDS > VGS − VTN Saturation is correct. Checking : VGG = 47x10 3 ID + VGS = 3.82V which is correct. Q − point : (54.3 μA, 8.15 V ) 4.90
(a) Setting KP = 500U, VTO = 1, and GAMMA = 0 yields ID = 89.6 μA, VGS = 1.60 V and VDS = 8.77 V 4 (a) Setting KP = 1000U, VTO = 1, and GAMMA = 0 yields ID = 96.3 μA, VGS = 1.44 V and VDS = 8.53 V 4 4.91
(a) Setting KP = 500U, VTO = 1, and GAMMA = 0 yields ID = 124 μA, VGS = 1.71 V and VDS = 10.5 V 4 (a) Setting KP = 1000U, VTO = 1, and GAMMA = 0 yields ID = 132 μA, VGS = 1.51 V and VDS = 10.2 V 4 4.92
(a) Setting KP = 500U, VTO = 1, and GAMMA = 0 yields ID = 50.2 μA, VGS = 1.45 V and VDS = 8.43 V 4 (a) Setting KP = 1000U, VTO = 1, and GAMMA = 0 yields ID = 54.1 μA, VGS = 1.27 V and VDS = 8.16 V 4 4.93 (300 kΩ, 700 kΩ) or (1.2 MΩ, 2.8 MΩ). We normally desire the current in the gate bias network to be much less than ID. We also usually like the parallel combination of R1 and R2 to be as large as possible. 4.94
35x10−6 2 (a) ID = (4 −1−1700ID ) and using the quadratic equation, 2 ID = 134μA. VDS =10 -134 x10−6 (1700 + 38300) = 4.64V 25x10−6 2 (4 − 0.75 −1700ID ) and using the quadratic equation, 2 ID = 116μA. VDS =10 -116x10−6 (1700 + 38300) = 5.36V
(b)
ID =
103
4.95
(a) Example 4.3 Setting KP = 25U and VTO = 1 yields ID = 34.4 μA, VGS = 2.66 V and VDS = 6.08 V 4 Results agree with hand calculations (b) Example 4.4 Setting KP = 25U and VTO = 1 yields ID = 99.2 μA, VGS = 3.82 V and VDS = 6.03 V 4 Results are almost identical to hand calculations 4.96 K n' = 100μA /V 2 | VTN = 0.75V | Choose VDS = VR D = VR S = 4V and VGS − VTN = 1V
RS =
4 4.1 = 40kΩ ⇒ 39kΩ and VR S = 3.9V | RD = = 41kΩ ⇒ 43kΩ 100μA 100μA
VGS − VTN =
2ID 2I W 2 = 1V and K n = D2 = 200μA /V 2 ⇒ = | Kn 1V L 1
R1 ⇒ R1 = 680 kΩ and R2 = 820 kΩ is one convenient possibility. R1 + R2 Another is R1 = 68 kΩ and R2 = 82 kΩ. Both choices have IR 2 0, so the transistor is saturated by connection. +12 V 10
ID =
W = L 1
10 M Ω
330 k Ω
+ G
VDS
+ V GS
-
-
VGS = 12 − 330kΩ(ID + IG ) −10MΩ(IG ) but I G = 0 VGS = 12 − 330kΩ(ID )
IDS I
⎛100 μA ⎞⎛10 ⎞ K n' W 2 2 ⎟(VGS − 0.75) (VGS − VTN ) = ⎜ 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 2 L
VGS must be 0.933 V since 0.564 V is below threshold.
⎛100 μA ⎞ 20 12 − 0.933 2 ID = ⎜ V = 33.5μA (0.933 − 0.75) = 33.5 μA Checking : 2⎟ ⎝ 2 V ⎠ 1 330kΩ and VDS = VGS :
Q-Point: (33.5 μA, 0.933 V)
4.105
(a) Assume saturation :
ID =
⎛100 μA ⎞⎛ 10 ⎞ K n' W 2 2 ⎟(VGS − 0.75) (VGS − VTN ) = ⎜ 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 2 L
VGS = 15 − 330kΩ(ID + IG ) −10MΩ(IG ) but I G = 0 VGS = 15 − 330kΩ(ID ) and VGS = VDS so saturation regioin operation is correct ⎛ 10−3 A ⎞ 2 VGS = 15 − (3.30x10 5 )⎜ V − 0.75) 2 ⎟( GS ⎝ 2 V ⎠ 3.30VGS2 − 4.93VGS + 1.556 = 0 yields VGS = 1.041V, 0.453V ⎛100 μA ⎞⎛ 10 ⎞ 15 −1.041 2 ID = ⎜ V = 42.3μA ⎟(1.041− 0.75) = 42.3μA | Checking : ID = 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 330kΩ Q − Point : (42.3 μA, 1.04 V) (b) Assume saturation ID =
⎛100 μA ⎞⎛ 25 ⎞ K n' W 2 2 ⎟(VGS − 0.75) (VGS − VTN ) = ⎜ 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 2 L
VGS = 15 − 330kΩ(ID + IG ) −10MΩ(IG ) but I G = 0 VGS = 15 − 330kΩ(ID ) and VGS = VDS so saturation region operation is correct. ⎛ 2.50x10−3 A ⎞ 2 V − 0.75) VGS = 15 − (3.30x10 5 )⎜ 2 ⎟( GS V ⎠ 2 ⎝ 8.25VGS2 −12.355VGS + 4.341 = 0 yields VGS = 0.9345V, 0.563V ⎛100 μA ⎞⎛ 25 ⎞ 15 − 0.9345 2 V = 42.6μA ID = ⎜ ⎟(0.9345 − 0.75) = 42.6μA | Checking : ID = 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 330kΩ Q - Point :
108
(42.6 μA, 0.935 V)
4.106
(a)
Asssume saturation
ID =
⎛100 μA ⎞⎛10 ⎞ K n' W 2 2 ⎟(VGS − 0.75) (VGS − VTN ) = ⎜ 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 2 L
VGS = 12 − 470kΩ(ID + IG ) −10MΩ(IG ) but IG = 0 VGS = 12 − 470kΩ(ID ) and VGS = VDS so saturation region operation is correct. ⎛ 10−3 A ⎞ 2 VGS = 12 − (4.70x10 5 )⎜ V − 0.75) 2 ⎟( GS ⎝ 2 V ⎠ 4.70VGS2 − 7.03VGS + 2.404 = 0 yields VGS = 0.9666V, 0.529V ⎛100 μA ⎞⎛ 10 ⎞ 12 − 0.967 2 ID = ⎜ = 23.5μA ⎟(0.9666 − 0.75) = 23.5μA | Checking : ID = 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠ 470kΩ Q - Point : (23.5 μA, 0.967 V) (b) Since the current in RG is zero, the drain current is independent of RG. 4.107 (a) Create an M-file: function f=bias(id) vtn=1+0.5*(sqrt(22e3*id)-sqrt(0.6)); f=id-(25e-6/2)*(6-22e3*id-vtn)^2; fzero('bias',1e-4) yields ans = 8.8043e-05
(b) Modify the M-file: function f=bias(id) vtn=1+0.75*(sqrt(22e3*id)-sqrt(0.6)); f=id-(25e-6/2)*(6-22e3*id-vtn)^2; fzero('bias',1e-4) yields ans = 8.3233e-05 4.108 Using a spreadsheet similar to Table 4.2 yields: (a) 88.04 μA, (b) 83.23 μA. 4.109
100kΩ 12V = 3.75V | Assume saturation 100kΩ + 220kΩ 2ID VTN = 1+ 0.6 24 x10 3 ID + 0.6 − 0.6 | VGS = VTN + 5x10−4 3.75 − VGS ID = | Solving iteratively yields ID = 73.1μA with VTN = 1.460V 24kΩ V = 12V − ID (24kΩ + 12kΩ) = 9.37 V Transistor is saturated. Q - Point : (73.1 μA, 9.37 V) VGG =
3.75 − VGS | Solving iteratively yields ID = 69.7μA with VTN = 1.550V 24kΩ = 12V − ID (24kΩ + 12kΩ) = 9.49 V The transistor is saturated. Q - Point : (69.7 μA, 9.49 V)
ID = VDS
(b) VTN = 1+ 0.6( 24 x10 3 ID + 0.6 −
0.6
)|
VGS = VTN +
2ID 5x10−4
3.75 − VGS | Solving iteratively yields ID = 73.1μA with VTN = 1.460V 24kΩ V = 12V − ID (24kΩ + 24kΩ) = 8.49 V The transistor is saturated. Q - Point : (73.1 μA, 8.49 V) ID =
4.111 (a) γ = 0.6
(b) γ = 0.75 (c ) γ = 0.6
VTN = 1.46 V VTN = 1.55 V VTN = 1.46 V
ID = 73.1 μA ID = 69.7 μA ID = 73.1 μA
VDS = 9.37 V VDS = 9.49 V VDS = 8.49 V
These results all agree with the hand calculations. (They should - they are all solving the same sets of equations.) 4.112 (a) γ = 0
VTN = 1.00 V
ID = 50.2 μA
VDS = 8.43 V
γ = 0.5 VTN = 1.42 V (b) γ = 0 VTN = 1.00 V γ = 0.5 VTN = 1.44 V
ID = 42.2 μA
VDS = 9.01 V
ID = 54.1 μA
VDS = 8.16 V
ID = 45.2 μA
VDS = 8.79 V
The γ = 0 values agree with the hand calculations in the original problem. Including body effect in the simulations reduces the Q-point current by approximately 15%. Although this may sound large, it is within the error that will be introduced by the use of 5% resistors and typical device tolerances. So, we normally omit γ in our hand calculations, and then refine the results using SPICE. 4.113 (a) γ = 0
VTN = 1.00 V
ID = 89.6 μA
VDS = 8.77 V
γ = 0.5 VTN = 1.39 V (b) γ = 0 VTN = 1.00 V γ = 0.5 VTN = 1.41 V
ID = 75.5 μA
VDS = 9.28 V
ID = 96.3 μA
VDS = 8.53 V
ID = 80.8 μA
VDS = 9.09 V
The γ = 0 values agree with the hand calculations in the original problem. Including body effect in the simulations reduces the Q-point current by approximately 15%. Although this may sound 110
large, it is within the error that will be introduced by the use of 5% resistors and typical device tolerances. So, we normally omit γ in our hand calculations, and then refine the results using SPICE. 4.114 γ =0
γ = 0.5
VTN = 1.00 V VTN = 1.35 V
ID = 778 μA ID = 661 μA
VDS = 9.20 V VDS = 9.62 V
The γ = 0 values agree with the hand calculations in the original problem. Including body effect in the simulations reduces the Q-point current by approximately 15%. Although this may sound large, it is within the error that will be introduced by the use of 5% resistors and typical device tolerances. So, we normally omit γ in our hand calculations, and then refine the results using SPICE. 4.115 γ =0
γ = 0.5
VTN = 1.00 V VTN = 1.45 V
ID = 10.5 μA ID = 9.18 μA
VDS = 8.03 V VDS = 8.69 V
The γ = 0 values agree with the hand calculations in the original problem. Including body effect in the simulations reduces the Q-point current by approximately 15%. Although this may sound large, it is within the error that will be introduced by the use of 5% resistors and typical device tolerances. So, we normally omit γ in our hand calculations, and then refine the results using SPICE. 4.116
(a) Both transistors are saturated by connection and the two drain currents must be equal. K K 2 2 ID1 = n1 (VGS1 − VTN1 ) and ID 2 = n 2 (VGS 2 − VTN 2 ) 2 2 But since the transistors are identical, ID1 = ID2 requires VGS1 = VGS2 = VDD/2 = 2.5V. 100x10−6 ⎛ 20 ⎞ 2 ID1 = ID 2 = ⎜ ⎟(2.5 −1) = 2.25 mA ⎝1⎠ 2 (b) For this case, the same arguments hold, and VGS1 = VGS2 = VDD/2 = 5V. 100x10−6 ⎛ 20 ⎞ 2 ID1 = ID 2 = ⎜ ⎟(5 −1) =16.0 mA ⎝1⎠ 2 . (c) For this case, the threshold voltages will be different due to the body-effect in the upper transistor. The drain currents must be the same, but the gate-source voltages will be different: VGS1 = VTN1 + VTN1 =1V
4.117 If we assume saturation, we find ID = 234 μA and VDS = 0.65 V, and the transistor is not saturated. Assuming triode region operation, VGS = 10 − 2x10 4 ID | VDS = 10 − 4 x10 4 ID μA ⎛ 2 ⎞⎛ 10 − 4 x10 4 ID ⎞ 4 ID = 100 2 ⎜ ⎟⎜10 − 2x10 4 ID −1− ⎟(10 − 4 x10 ID ) ⎝ ⎠ 2 V 1 ⎝ ⎠ Collecting terms : 16.5x10 4 ID = 40 → ID = 242 μA
VDS = 10 − 4 x10 4 (2.42x10−4 )= 0.320V | Q - Pt : (242 μA, 0.320V ) Checking the operating region : VGS − VTN = 4.16V > VDS and the triode region assumption is correct. Checking : ID =
10 − 0.32 V = 242μA 40kΩ
4.118 If we assume saturation, we find an inconsistent answer. Assuming triode region operation, VGS = 10 − 2x10 4 ID | VDS = 10 − 3x10 4 ID μA ⎛ 4 ⎞⎛ 10 − 3x10 4 ID ⎞ 4 ID = 100 2 ⎜ ⎟⎜10 − 2x10 4 ID −1− ⎟(10 − 3x10 ID ) 2 V ⎝ 1 ⎠⎝ ⎠ Collecting terms : 1.5x10 8 ID2 −1.725x10 5 ID + 40 = 0 → ID = 322μA
VDS = 10 − 3x10 4 (3.22x10−4 )= 0.340V | Q - Pt : (322 μA, 3.18 V ) Checking the operating region : VGS − VTN = 2.56V > VDS and the triode region assumption is correct. Checking : ID =
112
10 − 0.34 V = 322μA 30kΩ
4.119 For (a) and (b), γ = 0. The transistor parameters are identical so 3VGS = 15V or VGS = 5V. ⎛ 20 ⎞ 1 2 (a) ID = (100x10−6 )⎜ ⎟(5 − 0.75) = 18.1 mA ⎝1⎠ 2 ⎛ 50 ⎞ 1 2 (b) ID = (100x10−6 )⎜ ⎟(5 − 0.75) = 45.2 mA ⎝1⎠ 2 (c) Now we have three different threshold voltages and need an iterative solution. Using MATLAB: function f=Prob112(id) gamma=0.5; vgs1=.75+sqrt(2*id/2e-3); vtn2=0.75+gamma*(sqrt(vgs1+0.6)-sqrt(0.6)); vgs2=vtn2+sqrt(2*id/2e-3); vtn3=0.75+gamma*(sqrt(vgs1+vgs2+0.6)-sqrt(0.6)); vgs3=vtn3+sqrt(2*id/2e-3); f=15-vgs1-vgs2-vgs3; fzero('Prob112',1e-4) --> ans = 0.0130 ID = 13.0 mA 4.120
W 20 = VTN = 0.75 V ID = 18.1 mA VDS = 5.00 V 1 L W 50 = VTN = 0.75 V ID = 45.2 mA VDS = 5.00 V (b) γ = 0 L 1 W 20 = VTN 3 = 1.95 V ID 3 = 13.0 mA VDS 3 = 5.56 V (b) γ = 0.5 L 1 VTN 2 = 1.48 V ID 2 = 13.0 mA VDS 2 = 5.09 V VTN1 = 0.75 V ID1 = 13.0 mA
(a) γ = 0
VDS1 = 4.36 V
Results are identical to calculations in Prob. 4.119 4.121 For VGS = 5 V and VDS = 0.5 V, the transistor will be in the triode region. (5 − 0.5)V = 54.88μA | 54.88x10−6 = 100x10−6⎛ W ⎞⎛5 − 0.75 − 0.5 ⎞0.5 | W = 0.274 = 1 ID = ⎜ ⎟⎜ ⎟ ⎝ L ⎠⎝ 2 ⎠ L 1 3.64 82kΩ 4.122 For VGS = 3.3 V and VDS = 0.25 V, the transistor will be in the triode region. (3.3 − 0.25)V = 16.94 μA | 16.94 x10−6 = 100x10−6⎛ W ⎞⎛ 3.3 − 0.75 − 0.25 ⎞0.25 | W = 0.280 = 1 ID = ⎜ ⎟⎜ ⎟ ⎝ L ⎠⎝ 2 ⎠ L 1 3.57 180kΩ
113
4.123 (a) The transistor is saturated by connection. For this circuit, VGS = VDD + ID R = −15 + 75000ID 4 x10−5 ⎛ 1⎞ 2 ID = ⎜ ⎟(−15 + 75000ID + 0.75) ⇒ 153 μA 2 ⎝ 1⎠ VGS = −15 + 75000ID = −3.525V VDS = VGS = −3.525V | Q - point : (153 μA,−3.53 V )
(b) Here the transistor has VGS = -15 V, a large value, so the transistor is most likely operating in the triode region. ⎛ VDS − (−15) V ⎞ = 4 x10−5 ⎜ −15 − (−0.75) − DS ⎟VDS ⇒ VDS = −0.347 V and ID = 195 μA. ⎝ 75000 2 ⎠ 15 − 0.347 V = 195μA Q - point : (195 μA,-0.347 V ) Checking : ID = 785kΩ Checking the region of operation: VDS = −0.347V > VGS − VTP = −15 + 0.75 = −14.25V ID =
Triode region is correct 4.124 Set W=1U L=1U KP=40U VTO=-0.75 GAMMA=0 Results are almost identical to hand calculations for both parts. 4.125 (a) IDP = IDN , and both transistors are saturated by connection. 10 = -VGSP + VGSN 1 ⎛ 100μA ⎞⎛ 20 ⎞ 1 ⎛ 40μA ⎞⎛ 20 ⎞ 2 2 ⎜ 2 ⎟⎜ ⎟(−10 + VGSN + 0.75) = ⎜ ⎟⎜ ⎟(VGSN − 0.75) 2 2 ⎝ V ⎠⎝ 1 ⎠ 2 ⎝ V ⎠⎝ 1 ⎠
(9.25 − VGSN ) =
2.5 (VGSN − 0.75) → VGSN = 4.04V | VGSP = −5.96V
IDP = IDN = 10.8 mA | VO = VGSN = 4.04V (b) Everything is the same except the currents scale by 80/20: IDP = IDN = 43.2 mA 4.126 For (a) and (b), γ = 0. The transistor parameters are identical so -3VGS = 15V or VGS = -5V.
1 40 2 40x10−6 ) (−5 + 0.75) = 14.4 mA ( 2 1 1 75 2 (b) ID = (40x10−6 ) (−5 + 0.75) = 27.1 mA 2 1 (a) ID =
(c) Now we have three different threshold voltages and need an iterative solution. Using MATLAB: function f=PMOSStack(id) gamma=0.5;
114
vsg1=.75+sqrt(2*id/1.6e-3); vtp2=-0.75-gamma*(sqrt(vsg1+0.6)-sqrt(0.6)); vsg2=-vtp2+sqrt(2*id/1.6e-3); vtp3=-0.75-gamma*(sqrt(vsg1+vsg2+0.6)-sqrt(0.6)); vsg3=-vtp3+sqrt(2*id/1.6e-3); f=15-vsg1-vsg2-vsg3; fzero('PMOSStack',1e-1) --> ans = 0.0104 ID = 10.4 mA. 4.127 (a) W=40U L=1U KP=40U VTO=-0.75 GAMMA=0 (b) W=75U L=1U KP=40U VTO=-0.75 GAMMA=0 (c) W=75U L=1U KP=40U VTO=-0.75 GAMMA=0.5 Results agree with hand calculations. 4.128
4V = 2mA. For ID = 0,VDS = −4V . (VSD = +4V ) 2kΩ 300kΩ VGS = VEQ = −4V = −3V (VSG = +3V ) 300kΩ + 100kΩ From the graph, the transistor is operating below pinchoff in the linear region. For VDS = 0, ID =
4VGS2 + 5.9VGS −1.5 = 0 → VGS = −1.148V and ID = 63.5μA
VDS = −(15 − (100kΩ + 50kΩ)ID ) = −5.47V | Q - point : (59.78 μA,−5.47 V ) (b) For saturation, VDS ≤ VGS − VTP or VSD ≥ VSG + VTP 15 − (100kΩ + R)ID ≥ 7.5 −100kΩID − 0.75 → R ≤ 130 kΩ 4.130 Setting W=20U, L=1U, LEVEL=1, KP=40U, VTO=-0.75 yields results identical to the previous problem. 4.131 (a) Using MATLAB: function f=bias4(id) gamma=0.5; vbs=1e5*id; vgs=-7.5+vbs; vtp=-0.75-gamma*(sqrt(vbs+0.6)-sqrt(0.6)); f=id-(8e-4/2)*(vgs-vtp)^2; fzero('bias4',4e-5) --> ans = 5.5278e-05 --> ID = 55.3 μA VDS = -15 + (100kΩ+R) ID (b) VDS ≤ VGS - VTP | -15 + (100kΩ+R)ID ≤ -1.972 + 1.600 |
R ≤ 164 kΩ
4.132 Setting W=20U, L=1U, LEVEL=1, KP=40U, VTO=-0.75 GAMMA=0.5 yields results identical to the previous problem. 4.133 (a) V
DD
R V +
GS
-
S
VDS
G D
+ I
SD
The arrow identifies the transistor as a PMOS device. Since γ = 0, we do not need to worry about body effect: VTP = VTO. Since VDS = VGS, and VTP < 0, the transistor is saturated.
117
K 'p W 2 ID = (VGS − VTP ) and - VGS = 12 −105 ID 2 L ⎛ 4 x10−5 ⎞⎛ 10 ⎞ 2 -VGS = 12 −10 5 ⎜ ⎟⎜ ⎟(VGS − (−0.75)) ⎝ 2 ⎠⎝ 1 ⎠ 20VGS2 + 29VGS − 0.75 = 0 yields VGS = −1.475V,+0.0255V We require VGS < VTP = -0.75 V for the transistor to be conducting so 2 4 x10−5 ⎛ 10 ⎞ A VGS = −1.475V and ID = ⎜ ⎟ 2 (−1.475 − (−0.75)) = 105 μA 2 ⎝ 1 ⎠V Since VDS = VGS, the Q-point is given by: Q-Point = (105 μA, -1.475 V). (b) Using MATLAB for the second part (Set gamma = 0 for part (a)): function f=bias2(id) gamma=1.0; vgs=-12+1e5*id; vsb=-vgs; vtp=-0.75-gamma*(sqrt(vsb+0.6)-sqrt(0.6)); f=id-5e-5*(vgs-vtp)^2; fzero('bias2',1e-4) --> ans = 9.5996e-05 and Q-Point = (96.0 μA, 2.40 V). 4.134
Solving iteratively yields I D = 35.2 μA with VTP = −1.38 V and VGS = −1.67 V (b) For saturation, VDS ≤ VGS − VTP
−15 + (100kΩ + R)I D ≤ −1.67 + 1.38 → R ≤ 318 kΩ 4.138 (a) Assume an equal voltage (5V) split between R D , RS and VDS. We need VDS ≤ VGS − VTP or - 5 ≤ VGS − VTP . Choose VGS − VTP = −2V. Kn =
7.86V − 2.75V 15 − 5 − 5.1 = 5.11kΩ → 5.1kΩ | RD = = 4.9kΩ → 4.7kΩ 1mA 1mA Note that R1 is connected between the gate and + 15 V, and R 2 is connected between RS =
the gate and ground. (b) For the NMOS case, choose W/L = 5/1. The resistors now have the same values
except R2 is now connected between the gate and +15 V, R1 is connected between the gate and ground, and RD =
15 − 6 − 5.1 = 3.9kΩ 1mA
119
4.139 (a) Assume an equal voltage (3V) split between R D , RS and VDS. We need VDS ≤ VGS − VTP or - 3 ≤ VGS − VTP . Choose VGS − VTP = −1V. Kn =
4.74V −1.75V 9 −3−3 = 5.97kΩ → 6.2kΩ | RD = = 6.0kΩ → 6.2kΩ 0.5mA 0.5mA Note that R1 is connected between the gate and + 9 V, and R 2 is connected between RS =
the gate and ground. R1 = 2 MΩ, R2 = 1.8 MΩ, RS = RD = 6.2kΩ, W / L = 25/1
(b) For the NMOS case, choose W/L
= 40/1. The resistors now have the same values
except R2 is now connected between the gate and + 9 V, and R1 is connected between the gate and ground. 4.140
⎛ 40 μA ⎞⎛ 10 ⎞ 4 VGS = 10 4 I D | Assume saturation : I D = ⎜ ⎟ 10 I D − 4 2 ⎟⎜ ⎝ 2 V ⎠⎝ 1 ⎠
(
)
2
Collecting terms : 108 I D2 − 8.5x10 4 I D + 16 = 0 → I D = 281 μA
(
)
VDS = − 15 −10 4 I D = −12.2V | Q - Pt : (281 μA,−12.2 V )
Checking : VGS − VTP = 2 − 4 = −1.19 V | VDS = −12.2 | Saturation is correct.
4.141
(
VGS = 10 4 I D | VTP = 4 − 0.25 VGS + 0.6 − 0.6
)
| ID =
Solving these equations iteratively yields I D = 260 μA
(
)
2 4x10−4 VGS − VTP ) ( 2
VDS = − 15 −10 4 I D = −12.4V | Q - Pt : (260 μA,−12.4 V )
120
4.142 Note: The answers are very sensitive to round-off error and are best solved iteratively using MATLAB, a spreadsheet, HP solver, etc. Hand calculations using the quadratic equation will generally yield poor results. Saturated by connection with VTP = −1 2 4x10−5 ⎛ 10 ⎞ 5 6 11 2 ID = ⎜ ⎟ 3.3x10 I D −12 − (−1) →121− 7.265x10 I D + 1.089x10 I D = 0 2 ⎝1⎠
[
]
I D = 34.6μA, 32.1μA | VDS = 3.3x105 I D −12 = −0.582V ,−1.407V | Q - point : (32.1 μA,−1.41 V )
since the transistor would not be conducting for VGS = −0.582V.
4.143 Note: The answers are very sensitive to round-off error and are best solved iteratively using MATLAB, a spreadsheet, HP solver, etc. Hand calculations using the quadratic equation will generally yield poor results. Saturated by connection with VTP = −3 ⎛ 4x10−5 ⎞⎛ 30 ⎞ 2 5 6 11 2 ID = ⎜ ⎟⎜ ⎟ 3.3x10 I D −12 − (−3) → 81− 5.941x10 I D + 1.089x10 I D = 0 ⎝ 2 ⎠⎝ 1 ⎠
[
]
I D = 27.07μA | VDS = 3.3x105 I D −12 = −3.067V | Q - point : (27.1 μA,−3.07 V )
4.144 Note: The answers are very sensitive to round-off error and are best solved iteratively using MATLAB, a spreadsheet, HP solver, etc. Hand calculations using the quadratic equation will generally yield poor results. (a) Large VGS − Assume triode region.
⎛ 10 ⎞⎛ V ⎞ | I D = 40x10−6 ⎜ ⎟⎜12 − 0.75 − DS ⎟VDS 2 ⎠ ⎝ 1 ⎠⎝
VDS = 12 − 3.3x105 I D
Q − po int : (36.1 μA, 80.6 mV) | VDS < VGS − VTN so triode region is correct. 2 10x10−6 ⎛ 25 ⎞ 5 Saturated by connection : I = b ⎜ ⎟ 3.3x10 I D −12 + 0.75 () D 2 ⎝1⎠
(
Q − point : (32.4μA,-1.32V)
(c) V
TP
ID =
(
= −0.75 − 0.5 3.3x105 I D + 0.6 − 0.6
40x10−6 ⎛ 25 ⎞ 5 ⎜ ⎟ 3.3x10 I D −12 − VTP 2 ⎝1⎠
(
)
2
)
) (
| VDS = − 12 − 3.3x105 I D
)
Q − point : (28.8 μA,-2.49 V)
121
4.145
(a) Kn = μn ID =
(b) K
' n
Tox
(a) C
GC
⎥⎝ 2μm ⎠ ⎦
V2
2 864μA ⎛ 4 1 ⎞ | I = ⎜ − ⎟ = 0.972 mA 2 ⎝ 2 2⎠
V | V = 2 '
' D
(
⎡ 3.9 8.854x10−14 F / cm ⎢ = C WL = ⎢ 20x10−7 cm ⎣
(b) α = 2
" OX
' | CGC =
CGC
1 gm 2π CGC
| gm =
)⎥⎤ 20x10 ( ⎥
−4
⎦
)(
)
cm 10−4 cm = 34.5 fF
= 17.3 fF
α
4.147
fT =
)⎥⎤⎛⎜ 20μm ⎞⎟ = 432 μA
2 432μA 4 −1) = 1.94 mA ( 2
= 2Kn
4.146
(
−14 ⎡ cm2 ⎢ 3.9 8.854x10 F / cm = 500 V −s⎢ L 40x10−7 cm ⎣
εox W
∂iD " W " = KP (VGS − VTP ) = μ pCOX | CGC = COX WL ∂vGS L
1 μp (VGS − VTP ), but (VGS − VTP )< 0 for PMOS transistor. 2π L2 1 μp Since f T should be positive, f T = (VGS − VTP ) 2π L2 fT =
5.5 (a) For this circuit, VBE = 0 V, VBC = -5 V and I = IC. Substituting these values into the collector current expression in Eq. (5.13): ⎡ ⎛ −5 ⎞⎤ I S ⎡ ⎛ −5 ⎞ ⎤ IC = I S ⎢exp(0)− exp⎜ ⎟⎥ − ⎢exp⎜ ⎟ −1⎥ ⎝ .025 ⎠⎦ β R ⎣ ⎝ .025 ⎠ ⎦ ⎣ ⎛ ⎛ 1⎞ 1⎞ I = IC = I S ⎜1+ ⎟ = 10−15 A⎜1+ ⎟ = 2 fA. ⎝ 1⎠ ⎝ βR ⎠
(b) For this circuit, the constraints are VBC = -5 V and IE = 0. Substituting these values into the emitter current expression in Eq. (5.13): ⎡ ⎛V ⎞ ⎛ V ⎞⎤ I ⎡ ⎛ V ⎞ ⎤ I E = I S ⎢exp⎜ BE ⎟ − exp⎜ BC ⎟⎥ + S ⎢exp⎜ BE ⎟ −1⎥ = 0 which gives ⎝ VT ⎠⎦ β F ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎛V ⎞ ⎛V ⎞ βF 1 + exp⎜ BC ⎟. Substituting this result into IC : exp⎜ BE ⎟ = ⎝ VT ⎠ 1+ β F 1+ β F ⎝ VT ⎠ ⎛ V ⎞⎤ I ⎡ ⎛ V ⎞ ⎤ I ⎡ ICBO = S ⎢1− exp⎜ BC ⎟⎥ − S ⎢exp⎜ BC ⎟ −1⎥. 1+ β F ⎣ ⎝ VT ⎠⎦ β R ⎣ ⎝ VT ⎠ ⎦ ⎡ 1 ⎡ 1 1⎤ 1⎤ + ⎥ = 10−15 A⎢ + ⎥ = 1.01 fA, and For VBC = -5V , ICBO = I S ⎢ ⎣101 1⎦ ⎣1+ β F β R ⎦ ⎛ 1 ⎞ ⎛ 1 ⎞ VBE = VT ln⎜ ⎟ = 0.025V ln⎜ ⎟ = −0.115 V ≠ 0! ⎝101⎠ ⎝1+ β F ⎠ 5.6
124
IB
+ 150 μA
B
VBC -
C
IC
(a) - (c) (b) npn transistor
E
+ V BE IE
(d) VBE = VBC
I S ⎡ ⎛ VBE ⎞ ⎤ ⎢exp⎜ ⎟ −1⎥ β R ⎣ ⎝ VT ⎠ ⎦ I ⎡ ⎛V ⎞ ⎤ I E = + S ⎢exp⎜ BE ⎟ −1⎥ β F ⎣ ⎝ VT ⎠ ⎦ ⎛ 1 1 ⎞ ⎡ ⎛V ⎞ ⎤ IB = IS ⎜ + ⎟ ⎢exp⎜ BE ⎟ −1⎥ ⎝ β F β R ⎠ ⎣ ⎝ VT ⎠ ⎦
(e) I
IE = IB
C
=−
1 1+
and
βF βR
IE β =− R IC βF
βF I = − 400I E and I B = I E − IC = 401 I E βR E For the circuit I B = 150μA 150μA Therefore I E = = 0.374 μA, and IC = −149.6 μA.
⎛ 1 ⎞⎡ ⎛ VBE ⎞ ⎤ IE | IC = β F I B For VBC = 0, I E = I S ⎜1+ ⎟⎢exp⎜ ⎟ −1⎥ | I B = βF + 1 ⎝ β F ⎠⎣ ⎝ VT ⎠ ⎦ 175μA 100 = 1.73 μA | IC = 175μA = 173 μA 101 101 ⎛ β ⎛100 175μA ⎞ IE ⎞ = VT ln⎜ F + 1⎟ = 0.025V ln⎜ + 1⎟ = 0.630 V ⎠ ⎝ 101 2 fA ⎠ ⎝ βF + 1 IS
I E = 175 μA | I B =
175 μA
VBE
125
5.8 - E IE
VBE IB
npn transistor
+ B + V BC
C -
IC
175 μA
⎛ 1 ⎞⎡ ⎛ V ⎞ ⎤ I For VBE = 0, IC = −I S ⎜1+ ⎟⎢exp⎜ BC ⎟ −1⎥ | I B = − C | I E = −β R I B βR + 1 ⎝ β R ⎠⎣ ⎝ VT ⎠ ⎦ ⎛ −175μA ⎞ 0.25 IC = −175 μA | I B = −⎜ 175μA = −35 μA ⎟ = 140 μA | I E = − 1.25 ⎝ 1.25 ⎠ ⎛ β ⎞ ⎛ 0.25 175μA ⎞ I + 1⎟ = 0.590 V VBC = VT ln⎜− R C + 1⎟ = 0.025V ln⎜ ⎝ 1.25 2 fA ⎠ ⎝ βR + 1 IS ⎠
5.9 Using vBC = 0 in Eq. 5.13 and recognizing that i = iC + iB = iE : ⎛ 1 ⎞⎡ ⎛ vBE ⎞ ⎤ i = iE = I S ⎜1 + ⎟⎢exp⎜ ⎟ − 1⎥ , and the reverse saturation current ⎝ β F ⎠⎣ ⎝ VT ⎠ ⎦ ⎛ ⎛ 1 ⎞ 1 ⎞ of the diode connected transistor is I S' = I S ⎜1 + ⎟ = (2 fA)⎜1 + ⎟ = 2.02 fA ⎝ 100 ⎠ ⎝ βF ⎠ 5.10 Using vBE = 0 in Eq. 5.13 and recognizing that i = −iC : ⎛ 1 ⎞⎡ ⎛ v ⎞ ⎤ i = −iC = −I S ⎜1 + ⎟⎢exp⎜ BC ⎟ − 1⎥ , and the reverse saturation current ⎝ β R ⎠⎣ ⎝ VT ⎠ ⎦ ⎛ ⎛ 1⎞ 1⎞ of the diode connected transistor is I S' = I S ⎜1 + ⎟ = (5 fA)⎜1 + ⎟ = 6.67 fA ⎝ 3⎠ ⎝ βR ⎠ 5.11
⎡ ⎛v ⎞ ⎡ ⎛ 0.75 ⎞ ⎛ v ⎞⎤ ⎛ −3 ⎞⎤ = I S ⎢exp⎜ BE ⎟ − exp⎜ BC ⎟⎥ = 5x10−16 A⎢exp⎜ ⎟ − exp⎜ ⎟⎥ = 5.34 mA ⎝ 0.025 ⎠⎦ ⎝ VT ⎠⎦ ⎣ ⎝ 0.025 ⎠ ⎣ ⎝ VT ⎠ (b) The current is symmetric: For VBC = 0.75 V and VBE = -3 V, iT = -5.34 mA.
(a) i
T
5.12
⎡ ⎛v ⎞ ⎡ ⎛ 0.70 ⎞ ⎛ vBC ⎞⎤ ⎛ −3 ⎞⎤ −15 BE a i = I exp A exp = 10 − exp − exp ⎢ ⎥ ⎢ ⎜ ⎟ ⎜ ⎟⎥ = 1.45 mA ( ) T S ⎜⎝ V ⎟⎠ ⎜⎝ V ⎟⎠ ⎝ 0.025 ⎠⎦ ⎣ ⎝ 0.025 ⎠ ⎣ T T ⎦ (b) The current is symmetric: For VBC = 0.70 V and VBE = -3 V, iT = -1.45 mA.
5.13 Base Contact = F p-type Emitter = D 5.14
126
Collector Contact = G p-type Collector = A
Emitter Contact = E Active Region = C
(a) pnp transistor i
+ v iB
EB
E
E
B -
C v
100 μA
CB
+
iC
(b)-(c) (d) Using Eq. (5.17) with vEB = 0 and dropping the "-1" terms: ⎛ ⎛v ⎞ ⎛v ⎞ 1 ⎞ ⎛v ⎞ I iC = −I S ⎜1+ ⎟ exp⎜ CB ⎟ iE = −I S exp⎜ CB ⎟ iB = S exp⎜ CB ⎟ βR ⎝ β R ⎠ ⎝ VT ⎠ ⎝ VT ⎠ ⎝ VT ⎠ IE βR 1 IE = = = αR = −β R 1 IC βR + 1 IB 1+
βR IC = −100μA, I E = α R IC = 0.25IC = −25.0μA αR I 0.25 1 IB = − E β R = = = I B = +75μA βR 1− α R 1− 0.25 3 α 0.985 βF = F = = 65.7 1− α F 1− 0.985
⎛V ⎞ ⎛ I ⎞ VEB = 0 and I E = −I S exp⎜ CB ⎟ VCB = VT ln⎜ − E ⎟ ⎝ VT ⎠ ⎝ Is ⎠ ⎛ −25x10−6 A ⎞ VCB = 0.025V ln⎜ − ⎟ = 0.599 V 10−15 A ⎠ ⎝
127
5.15 (a) pnp VCB
IC
+
C
-
IB
B V
+
V EB
E +
IE
(b)-(c) (d) Using Eq. (5.17) with vCB = 0 and droping the "-1" terms: ⎛ ⎛v ⎞ 1 ⎞ ⎛ vEB ⎞ iE = I S ⎜1 + iC = −I S exp⎜ EB ⎟ ⎟ exp⎜ ⎟ ⎝ β F ⎠ ⎝ VT ⎠ ⎝ VT ⎠ IC 300μA = = 2.29 fA IS = ⎛ VEB ⎞ ⎛ 0.640 ⎞ exp⎜ ⎟ exp⎜ ⎟ ⎝ 0.025V ⎠ ⎝ VT ⎠
βF =
iB =
⎛v ⎞ exp⎜ EB ⎟ βF ⎝ VT ⎠ IS
αR IC 300μA 0.2 = = 75 | β R = = = 0.25 4μA IB 1− α R 1− 0.2
5.16 Using VCB = 0 in Eq. 5.17 and recognizing that i = iE : ⎛ 1 ⎞⎡ ⎛ vEB ⎞ ⎤ i = iE = I S ⎜1 + ⎟⎢exp⎜ ⎟ − 1⎥ , and the reverse saturation current ⎝ β F ⎠⎣ ⎝ VT ⎠ ⎦ ⎛ ⎛ 1 ⎞ 1 ⎞ of the diode connected transistor is I S' = I S ⎜1 + ⎟ = (2 fA)⎜1 + ⎟ = 2.02 fA ⎝ 100 ⎠ ⎝ βF ⎠ 5.17 v
-
i B
B - v
CB
+
35 μA i
C
C
E
EB
+ iE
(a)-(c) (b) pnp transistor(d) ⎛ 1 I ⎡ ⎛v ⎞ ⎤ I ⎡ ⎛v ⎞ ⎤ 1 ⎞⎡ ⎛ v ⎞ ⎤ + ⎟⎢exp⎜ EB ⎟ −1⎥ vEB = vCB iC = − S ⎢exp⎜ EB ⎟ −1⎥ iE = + S ⎢exp⎜ EB ⎟ −1⎥ iB = + I S ⎜ β R ⎣ ⎝ VT ⎠ ⎦ β F ⎣ ⎝ VT ⎠ ⎦ ⎝ β F β R ⎠⎣ ⎝ VT ⎠ ⎦ 1 IE βR 4 IE β 4 βF = = = = 0.0506 = − R = − = −0.0533 1 1 IB β F + β R 79 IB βF 75 +
βF
128
βR
4 75 I B = 1.77 μA IC = − I E = −33.2 μA 79 4 ⎛ 4 −33.2x10−6 A ⎛ β R IC ⎞ VCB = VEB = 0.025V ln⎜1− = VT ln⎜1− ⎟ ⎜ Is ⎠ 2x10−15 A ⎝ ⎝
I B = 35 μA
VEB
IE =
(
)⎟⎞ = 0.623 V ⎟ ⎠
5.18 C IC VCB + IB
B V EB
E +
IE
pnp transistor ⎛ 1 ⎞ ⎡ ⎛ VEB ⎞ ⎤ For VCB = 0, I E = I S ⎜1+ ⎟ ⎢exp⎜ ⎟ −1⎥ ⎝ β F ⎠ ⎣ ⎝ VT ⎠ ⎦
| IB =
IE | IC = β F I B βF + 1
300μA = 2.97 μA | IC = 100(2.97μA)= 297 μA 101 ⎤ ⎡⎛ β ⎞ I ⎡⎛ 100 ⎞ 300μA ⎤ = VT ln⎢⎜ F ⎟ E + 1⎥ = 0.025V ln⎢⎜ + 1⎥( )= 0.626 V ⎟ ⎦ ⎣⎝ 101⎠ 4 fA ⎣⎝ β F + 1⎠ I S ⎦
I E = 300 μA | I B =
I
VEB 5.19 VEB IB
+ E IE
B V CB I
C +
IC
pnp transistor ⎛ 1 ⎞⎡ ⎛ V ⎞ ⎤ I | I E = −β R I B For VEC = 0, IC = −I S ⎜1+ ⎟⎢exp⎜ CB ⎟ −1⎥ | I B = − C βR + 1 ⎝ β R ⎠⎣ ⎝ VT ⎠ ⎦ ⎛ −300μA ⎞ IC = −300 μA | I B = −⎜ ⎟ = 150 μA | I E = −1(150μA)= −150 μA ⎝ 2 ⎠ ⎡ ⎛ β ⎞I ⎤ ⎡ 1 ⎛ −300μA ⎞ ⎤ VCB = VT ln⎢−⎜ R ⎟ C + 1⎥ = 0.025V ln⎢− ⎜ ⎟ + 1⎥ = 0.603 V ⎣ 2 ⎝ 5 fA ⎠ ⎦ ⎣ ⎝ β R + 1⎠ I S ⎦
5.20
⎡ ⎛v ⎞ ⎡ ⎛ 0.70 ⎞ ⎛ v ⎞⎤ ⎛ −3 ⎞⎤ = I S ⎢exp⎜ EB ⎟ − exp⎜ CB ⎟⎥ = 5x10−16 A⎢exp⎜ ⎟ − exp⎜ ⎟⎥ = 723 μA ⎝ 0.025 ⎠⎦ ⎝ VT ⎠⎦ ⎣ ⎝ 0.025 ⎠ ⎣ ⎝ VT ⎠ (b) The current is symmetric: For VCB = 0.75 V and VEB = -3 V, iT = -723 μA.
(a) i
T
129
5.21
⎡ ⎛v ⎞ ⎤ ⎡ ⎛ 0.73V ⎞ ⎤ i = I a ⎢ ( ) F S exp⎜⎝ VBE ⎟⎠ −1⎥ = 4x10−15 A⎢exp⎜⎝ 0.025V ⎟⎠ −1⎥ = 19.2 mA ⎣ ⎦ ⎣ ⎦ T ⎡ ⎛v ⎞ ⎤ ⎡ ⎛ −3V ⎞ ⎤ iR = I S ⎢exp⎜ BC ⎟ −1⎥ = 4x10−15 A⎢exp⎜ ⎟ −1⎥ = −4.00 fA ⎣ ⎝ 0.025V ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ 19.2mA i −4.00 fA = 240 μA | R = = −2.00 μA βF βR 80 2 ⎡ ⎛v ⎞ ⎤ ⎡ ⎛ −3V ⎞ ⎤ (b) iF = I S ⎢exp⎜⎝ VBE ⎟⎠ −1⎥ = 4x10−15 A⎢⎣exp⎜⎝ 0.025V ⎟⎠ −1⎥⎦ = −4.00 fA ⎦ ⎣ T ⎡ ⎛v ⎞ ⎤ ⎡ ⎛ 0.73V ⎞ ⎤ iR = I S ⎢exp⎜ BC ⎟ −1⎥ = 4x10−15 A⎢exp⎜ ⎟ −1⎥ = 19.2 mA ⎣ ⎝ 0.025V ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ iT = iF − iR = 19.2 mA |
iF
iT = iF − iR = −19,2 mA |
=
iF
βF
−4.00 fA i 19.2mA = −0.05 μA | R = = 9.60 mA βR 80 2
=
5.22
⎡ ⎛v ⎞ ⎤ ⎡ ⎛ 0.68V ⎞ ⎤ = I S ⎢exp⎜ EB ⎟ −1⎥ = 6x10−15 A⎢exp⎜ ⎟ −1⎥ = 3.90 mA ⎣ ⎝ 0.025V ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎤ ⎡ ⎛ −3V ⎞ ⎤ iR = I S ⎢exp⎜ CB ⎟ −1⎥ = 6x10−15 A⎢exp⎜ ⎟ −1⎥ = −6.00 fA ⎣ ⎝ 0.025V ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦
(a) i
F
3.90mA i −6.00 fA = 65.0 μA | R = = −2.00 μA βF βR 60 3 ⎡ ⎛v ⎞ ⎤ ⎡ ⎛ −3V ⎞ ⎤ (b) iF = I S ⎢exp⎜⎝ VEB ⎟⎠ −1⎥ = 6x10−15 A⎢⎣exp⎜⎝ 0.025V ⎟⎠ −1⎥⎦ = −6.00 fA ⎣ ⎦ T ⎡ ⎛v ⎞ ⎤ ⎡ ⎛ 0.68V ⎞ ⎤ iR = I S ⎢exp⎜ CB ⎟ −1⎥ = 6x10−15 A⎢exp⎜ ⎟ −1⎥ = 3.90 mA ⎣ ⎝ 0.025V ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ iT = iF − iR = 3.90 mA |
iT = iF − iR = −3.90 mA |
130
iF
iF
=
βF
=
−6.00 fA i 3.90mA = −0.100 fA | R = = 1.30 mA 60 3 βR
5.23
⎡ ⎛v ⎞ ⎡ ⎛v ⎞ ⎛ v ⎞⎤ I ⎡ ⎛ v ⎞ ⎤ ⎛v ⎞ ⎤ I ⎡ ⎛v ⎞ ⎤ iE = I S ⎢exp⎜ BE ⎟ − exp⎜ BC ⎟⎥ + S ⎢exp⎜ BE ⎟ −1⎥ = I S ⎢exp⎜ BE ⎟ −1− exp⎜ BC ⎟ + 1⎥ + S ⎢exp⎜ BE ⎟ −1⎥ ⎝ VT ⎠⎦ β F ⎣ ⎝ VT ⎠ ⎦ ⎝ VT ⎠ ⎦ β F ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎣ ⎝ VT ⎠ ⎡ ⎛v ⎞ ⎤ I ⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ ⎛ ⎛ v BC ⎞ ⎤ 1 ⎞⎡ ⎛ vBE ⎞ BC S BE BC iE = I S ⎜1+ exp exp exp −1− exp + 1 − I −1 = −1 − I ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎟ −1⎥ S S ⎢exp⎜ ⎝ β F ⎠⎣ ⎝ VT ⎠ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ α F ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎡ ⎛v ⎞ ⎛ v ⎞⎤ I ⎡ ⎛ v ⎞ ⎤ ⎛v ⎞ ⎤ I ⎡ ⎛v ⎞ ⎤ iC = I S ⎢exp⎜ BE ⎟ − exp⎜ BC ⎟⎥ − S ⎢exp⎜ BC ⎟ −1⎥ = I S ⎢exp⎜ BE ⎟ −1− exp⎜ BC ⎟ + 1⎥ − S ⎢exp⎜ BC ⎟ −1⎥ ⎝ VT ⎠⎦ β R ⎣ ⎝ VT ⎠ ⎦ ⎝ VT ⎠ ⎦ β R ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎣ ⎝ VT ⎠ ⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ I ⎡ ⎛v ⎞ ⎤ ⎛ 1 ⎞⎡ ⎛ v ⎞ ⎤ iC = I S ⎢exp⎜ BE ⎟ −1⎥ − I S ⎜1+ ⎟⎢exp⎜ BC ⎟ −1⎥ = I S ⎢exp⎜ BE ⎟ −1⎥ − S ⎢exp⎜ BC ⎟ −1⎥ ⎝ β R ⎠⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ α R ⎣ ⎝ VT ⎠ ⎦
Defining I ES =
IS
αF
and ICS =
IS
αR
, then we see I S = α F I ES = α R ICS and
⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ iE = I ES ⎢exp⎜ BE ⎟ −1⎥ − α R I S ⎢exp⎜ BC ⎟ −1⎥ ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ iC = α F I ES ⎢exp⎜ BE ⎟ −1⎥ − ICS ⎢exp⎜ BC ⎟ −1⎥ ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ iB = iE − iC = (1− α F )I ES ⎢exp⎜ BE ⎟ −1⎥ + (1− α R )I S ⎢exp⎜ BC ⎟ −1⎥ ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ 5.24
αF =
βF
βR 100 0.5 I 2 fA = 0.990 | α R = = = 0.333 | I ES = S = = 2.02 fA β F + 1 101 β R + 1 1.5 α F 0.990
ICS =
IS
αR
=
=
2 fA = 6.00 fA | α F I ES = α R ICS = I S 0.333
131
5.25
⎡ ⎛v ⎞ ⎡ ⎛v ⎞ ⎤ ⎛v ⎞ ⎤ I ⎡ ⎛v ⎞ ⎤ ⎛ 1 ⎞⎡ ⎛ v EB ⎞ ⎤ CB iE = I S ⎢exp⎜ EB ⎟ −1− exp⎜ CB ⎟ + 1⎥ + S ⎢exp⎜ EB ⎟ −1⎥ = I S ⎜1+ ⎟⎢exp⎜ ⎟ −1⎥ − I S ⎢exp⎜ ⎟ −1⎥ ⎝ VT ⎠ ⎦ β F ⎣ ⎝ VT ⎠ ⎦ ⎝ β F ⎠⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎡ ⎛v ⎞ ⎤ ⎛v ⎞ ⎤ I ⎡ ⎛v ⎞ ⎤ ⎛ 1 ⎞⎡ ⎛ v ⎞ ⎤ iC = I S ⎢exp⎜ EB ⎟ −1− exp⎜ CB ⎟ + 1⎥ − S ⎢exp⎜ CB ⎟ −1⎥ = I S ⎢exp⎜ EB ⎟ −1⎥ − I S ⎜1+ ⎟⎢exp⎜ CB ⎟ −1⎥ ⎝ VT ⎠ ⎦ β R ⎣ ⎝ VT ⎠ ⎦ ⎝ β R ⎠⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ iE = I ES ⎢exp⎜ EB ⎟ −1⎥ − α R ICS ⎢exp⎜ CB ⎟ −1⎥ ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ iC = α F I ES ⎢exp⎜ EB ⎟ −1⎥ − ICS ⎢exp⎜ CB ⎟ −1⎥ ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ⎡ ⎛v ⎞ ⎤ ⎡ ⎛v ⎞ ⎤ iB = iE − iC = (1− α F )I ES ⎢exp⎜ EB ⎟ −1⎥ + (1− α R )ICS ⎢exp⎜ CB ⎟ −1⎥ ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦
5.26 At IC = 5 mA and VCE = 5 V , I B = 60μA : β F =
IC 5mA = = 83.3 I B 60μA
At IC = 7 mA and VCE = 7.5 V , I B = 80μA : β F =
IC 7mA = = 87.5 I B 80μA
At IC = 10 mA and VCE = 14 V , I B = 100μA : β F =
IC 10mA = = 100 I B 100μA
5.27 See Problem 5.28 5.28 20mA
10mA
0A
-4mA 0V
2V
4V
6V
-I(VCC) V_VCC
132
8V
10V
5.29 3.0mA
2.0mA
1.0mA
0A
-1.0mA -2V
0V
2V
4V
6V
8V
10V
-I(VCB) V_VCB
5.30 See Problem 5.31 5.31 20mA
10mA
0A
-4mA 0V
2V
4V
6V
8V
10V
-I(VEC) V_VEC
133
5.32 3.0mA
2.0mA
0A
-1.0mA -2V
0V
2V
4V
6V
8V
10V
-I(VBC) V_VBC
5.33 The change in vBE for a decade change in iC is ΔVBE = VT ln (10) = 2.30VT .
⎛1.38x10-23 ⎞ kT The reciprocal of the slope is 2.30VT = 2.30 = 2.30⎜ ⎟T (V/dec) -19 q ⎝1.60x10 ⎠ (a) 39.6 mV/dec (b) 49.5 mV/dec (c) 59.4 mV/dec (d) 69.3 mV/dec 5.34 (a) The break down voltage is equal to that of the emitter-base junction: VZ = 6 V. (b) The break down voltage is determined by the base-collector junction: VZ = 50 V. (c) The break down voltage is set by the emitter-base junction: VZ = 6 V. 5.35 (a) The base-emitter junction breaks down with VEB = 6.3 V. 5 − 6.3 − (−5) V = 2.31 mA IR = Ω 1600 (b) The base-emitter junction is forward biased; VBE = 0.7 V 5 − 0.7 − (−5) V IR = = 388 μA 24000 Ω (c) VBE = 0, and the collector-base junction is reversed biased with VBC ≈ -10V which is less than the breakdown voltage of 75 V. The transistor is operating in cutoff. ⎛ I 1⎞ Using Eq. (5.13), I R = IC = I S (1− 0)− S (0 −1)= I S ⎜1+ ⎟ ≈ 0 βR ⎝ βR ⎠ 5.36 VCE = VCB + VBE = VCB + 0.7 ≤ 65.7 V
134
5.37 (a) IB is forced to be negative by the current source, and the largest negative base current according to the Transport model is ⎛ 1 ⎛1 1⎞ 1 ⎞ IB = −IS ⎜ + ⎟ = −10−15 A⎜ + ⎟ = −2.02 fA ⎝ 50 0.5 ⎠ ⎝ βF βR ⎠ .
(b) IB is forced to be -1 mA by the current source. One or both of the junctions must enter the breakdown region in order to supply this current. For the case of a normal BJT, the base-emitter junction will break down and supply the current since it has the lower reverse breakdown voltage. 5.38
Base-Emitter Voltage
Base-Collector Voltage 0.7 V
-5.0 V
-5.0 V
Reverse Active
Cutoff
0.7 V
Saturation
Forward Active
5.39 (a) vBE > 0, vBC = 0, forward-active region; vBE = 0, vBC > 0, reverse-active region; vBE > 0, vBC = 0, forward-active region (b) vEB < 0, vCB < 0, cutoff region (c) vEB > 0, vCB < 0, forward-active region (d) vBE > 0, vBC < 0, forward-active region; vBE > 0, vBC > 0, saturation region 5.40 (a) vBE = 0, vBC < 0 cutoff region (b) vBC < 0, IE = 0, cutoff region 5.41 (a) vBE > 0, vBC > 0 saturation region (b) vBE > 0, vBC = 0, forward-active region (c) vBE = 0, vBC > 0, reverse-active region
135
5.42
Emitter-Base Voltage
Collector-Base Voltage 0.7 V
-0.65 V
0.7 V
Saturation
Forward Active
-0.65 V
Reverse Active
Cutoff
5.43 (a) vBE > 0, vBC = 0, forward-active region (b) vBE = 0, vBC > 0, reverse-active region 5.44 (a) vEB = 0, vCB > 0, reverse-active region (b) vEB > 0, vCB = 0, forward-active region 5.45 (a) vEB > 0, vCB > 0, saturation region (b) vEB > 0, vCB = 0, forward-active region (c) vEB = 0, vCB > 0, reverse-active region 5.46 (a ) pnp transistor with VEB = −3V and VCB = −3V → Cutoff | Using Eq. (5.17) : 10−15 A I 10−15 A = 0.5x10-15 = 0.5 fA | I E = − S = = 13.3x10-18 = 13.3 aA 2 75 βR βF ⎛ 1 ⎛ 1 1⎞ 1⎞ + ⎟ = 10−15 A⎜ + ⎟ = 0.263x10−15 = 0.263 fA I B = −I S ⎜ ⎝ 75 4 ⎠ ⎝ βF βR ⎠
IC = +
IS
=
(b) npn transistor with V
BE
= −5V and VBC = −5V → Cutoff | The currents are the same as
These currents are all very small - for most practical purposes it still appears to be cutoff. Since VBE > 0 and VBC < 0, the transistor is actually operating in the forward-active region. Note that I C = β FI B . 5.48 An npn transistor with VBE = 0.7V and VBC = −0.7V → Forward - active region
Using Eq. (5.45) : I E = (β F + 1)I B | β F =
IE 10mA −1 = −1 = 65.7 0.15mA IB
⎛ 1 ⎞ ⎛V ⎞ 0.01A = 6.81x10−15 A = 6.81 fA I E = I S ⎜1+ ⎟ exp⎜ BE ⎟ | I S = ⎛ ⎞ ⎛ ⎞ 1 0.7 ⎝ β F ⎠ ⎝ VT ⎠ ⎜1+ ⎟ exp⎜ ⎟ ⎝ 65.7 ⎠ ⎝ 0.025⎠ 5.49 A pnp transistor with VEB = 0.7V and VCB = −0.7V ⇒ Forward - active region ⎛V ⎞ I 2.5mA 2.5mA Using Eq. (5.44) : β F = C = = 62.5 | IC = I S exp⎜ EB ⎟ | I S = = 1.73 fA ⎛ 0.7V ⎞ I B 0.04mA ⎝ VT ⎠ exp⎜ ⎟ ⎝ 0.025V ⎠ 5.50
IE =
−0.7V − (−3.3V ) 47kΩ
= 55.3μA | I B =
IE 55.3μA = = 0.683μA 81 βF + 1
IC = β F I B = 80(0.683μA)= 54.6μA | Check : I B + IC = I E is ok 5.51
(a) f β =
fT
βF
=
500 MHz = 6.67 MHz 759
(b) The graph represents the Bode magnitude plot. Thus β (s) =
βF 1+
s
ωβ
=
βFωβ ωT = s + ωβ s + ωβ
ωT βF β (s) s + ωβ βFωβ ωT αF βF + 1 α (s)= = = = = ≈ ωT s s s + ωT + ω β s + (β F + 1)ω β β (s)+ 1 +1 1+ 1+ s + ωβ ωT (β F + 1)ω β α ( jω ) =
αF ⎛ ω ⎞2 1+ ⎜ ⎟ ⎝ ωT ⎠
137
5.52 vEB > 0
vCB < −4VT ⎛V ⎞ I ⎛V ⎞ iC = I S exp⎜ EB ⎟ + S ≈ I S exp⎜ EB ⎟ ⎝ VT ⎠ β R ⎝ VT ⎠ ⎛V ⎞ I ⎛V ⎞ I ⎛V ⎞ iE = I S exp⎜ EB ⎟ + S exp⎜ EB ⎟ = S exp⎜ EB ⎟ ⎝ VT ⎠ β F ⎝ VT ⎠ α F ⎝ VT ⎠ ⎛V ⎞ I ⎛V ⎞ I I iB = S exp⎜ EB ⎟ − S ≈ S exp⎜ EB ⎟ βF ⎝ VT ⎠ β R β F ⎝ VT ⎠ iC = β F iB | iC = α F iE
iB
iC C
B
+
i = β i
vEB
C
F B
0.7 V i
E
E
5.53 An npn transistor with VBE = −0.7V and VBC = +0.7V → Reverse - active region
Using Eq. (5.51) : IC = −(β R + 1)I B | β R = − ⎛V ⎞ I E = −I S exp⎜ BC ⎟ | I E = −35μA | I S = − ⎝ VT ⎠
IC −75μA −1 = − −1 = 0.875 40μA IB
−35μA = 2.42x10−17 A = 0.0242 fA = 24.2 aA ⎛ 0.7 ⎞ exp⎜ ⎟ ⎝ 0.025⎠
5.54 A pnp transistor with VEB = −0.7 V and VCB = +0.7 V → Reverse − active region ⎛V ⎞ I ⎛V ⎞ ⎛V ⎞ I iC = −I S exp⎜ CB ⎟ − S exp⎜ CB ⎟ = − S exp⎜ CB ⎟ αR ⎝ VT ⎠ β R ⎝ VT ⎠ ⎝ VT ⎠ ⎛V ⎞ I ⎛V ⎞ iE = −I S exp⎜ CB ⎟ − S ≅ −I S exp⎜ CB ⎟ ⎝ VT ⎠ β F ⎝ VT ⎠ ⎛V ⎞ I ⎛V ⎞ I I iB = − S + S exp⎜ CB ⎟ ≅ S exp⎜ CB ⎟ βF βR ⎝ VT ⎠ β R ⎝ VT ⎠
⎡ ⎤ β 1+ FOR ⎥ ⎢ ⎛ 1 ⎞ (β R + 1)⎥ βR I 1mA 2 | αR = β FOR = C = = 1 | VCESAT = VT ln⎢⎜ ⎟ = ⎢⎝ α R ⎠ ⎛β ⎞ ⎥ I B 1mA βR + 1 3 1− ⎜ FOR ⎟ ⎥ ⎢ ⎝ βF ⎠ ⎦ ⎣ ⎡ 1 ⎤ ⎢ 1+ ⎥ ⎛ 3 ⎞ (2 + 1)⎥ ⎢ = 17.8 mV VCESAT = 0.025ln ⎜ ⎟ ⎢⎝ 2 ⎠ ⎛1⎞⎥ 1− ⎜ ⎟ ⎥ ⎢ ⎝ 50 ⎠ ⎦ ⎣ ⎡ ⎤ ⎢ ⎥ ⎡ 1mA + (1− 0.667)1mA ⎤ I B + (1− α R )IC ⎥ ⎢ ⎥ = 0.724 V = 0.025V )ln⎢ −15 VBE = VT ln ⎞⎥ ( ⎢ ⎛ 1 ⎢⎣10 A(0.02 + 1− .0.667)⎥⎦ + 1− α R ⎟ ⎥ ⎢ IS ⎜ ⎠⎦ ⎣ ⎝ βF
5.57
⎛v ⎞ I ⎛v ⎞ ⎛v ⎞ I ⎛v ⎞ I iC = I S exp⎜ EB ⎟ − S exp⎜ CB ⎟ | iB = S exp⎜ EB ⎟ + S exp⎜ CB ⎟ | Simultaneous βF ⎝ VT ⎠ α R ⎝ VT ⎠ ⎝ VT ⎠ β R ⎝ VT ⎠ i iB − C iB + (1− α R )iC βF solution yields : vEB = VT ln | vCB = VT ln ⎤ ⎤ ⎡1 ⎡ 1 ⎤⎡ 1 I S ⎢ + (1− α R )⎥ I S ⎢ ⎥⎢ + (1− α R )⎥ ⎦ ⎦ ⎣β F ⎣α R ⎦⎣β F ⎡ ⎤ iC 1+ ⎢ ⎥ ⎛ 1 ⎞ (β R + 1) iB ⎥ i ⎢ vECSAT = vEB − vCB = VT ln ⎜ ⎟ for i B > C ⎢⎝ α R ⎠ ⎥ i βF 1− C ⎢ ⎥ β F iB ⎦ ⎣
5.58 (a) Substituting iC = 0 in Eq. 5.30 gives
⎛ 1 ⎞ ⎛ 1 ⎞ VCESAT = VT ln⎜ ⎟ = (0.025V )ln⎜ ⎟ = 0.0173 V = 17.3 mV ⎝ 0.5⎠ ⎝αR ⎠ (b) By symmetry ⎛ 1 ⎞ VECSAT = VT ln⎜ ⎟ ⎝αF ⎠ or by using iE = 0 and iC = -iB,
139
VCESAT
βR 1 1− ⎛ 1 ⎞ β +1 ⎛ 1 ⎞ β +1 ⎛ 1 ⎞α R = VT ln⎜ ⎟ = VT ln⎜ ⎟ R = VT ln⎜ ⎟ R ⎝ α R ⎠ 1+ 1 ⎝ α R ⎠ βF + 1 ⎝αR ⎠ 1 βF
⎡ β FOR ⎤ 1+ ⎢⎛ ⎥ 1 ⎞ (0.9 + 1) ⎥ I 20A (b) 0.04 = 0.025ln⎢⎜ = 10.1A → β FOR = 1.97 | I B = C = ⎟ ⎞ ⎛ β FOR 1.97 ⎢⎝ 0.4737 ⎠ 1− β FOR ⎥ ⎟ ⎜ ⎢⎣ ⎝ 15 ⎠ ⎥⎦
140
5.61 With VBE = 0.7 and VBC = 0.5, the transistor is technically in the saturation region, but calculating the currents using the transport model in Eq. (5.13) yields
At 0.5 V, the collector-base junction is not heavily forward biased compared to the base-emitter junction, and IC = 38.5IB ≅ β F IB . The transistor still acts as if it is operating in the forwardactive region. 5.62 (a) The current source will forward bias the base - emitter junction (VBE ≅ 0.7V ) and
the collector - base junction will then be reverse biased (VBC ≅ −2.3V ). Therefore, the npn transistor is in the forward - active region. ⎛ 50 175x10−6 A ⎞ ⎛ VBE ⎞ ⎟ = 0.803 V IC = β F I B = I S exp⎜ ⎟ | VBE = 0.025ln⎜ −16 ⎜ ⎟ V 10 A ⎝ T ⎠ ⎝ ⎠ (b) Since I B = 175μA and IC = 0, IC < β F I B , and the transistor is saturated.
⎡ ⎛v ⎞ ⎛ v ⎞⎤ I ⎡ ⎛ v ⎞ ⎤ iC = I S ⎢exp⎜ BE ⎟ − exp⎜ BC ⎟⎥ + S ⎢exp⎜ BC ⎟ −1⎥ ⎝ VT ⎠⎦ β R ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎡ ⎛v ⎞ ⎛ v ⎞⎤ I ⎡ ⎛ v ⎞ ⎤ iE = I S ⎢exp⎜ BE ⎟ − exp⎜ BC ⎟⎥ + S ⎢exp⎜ BE ⎟ −1⎥ ⎝ VT ⎠⎦ β F ⎣ ⎝ VT ⎠ ⎦ ⎣ ⎝ VT ⎠ vBE > 4VT and vBC < −4VT ⎡ ⎛ v ⎞⎤ ⎛ 1 ⎞⎡ ⎛ vBE ⎞⎤ I S ⎡ ⎛ v BE ⎞⎤ iC ≅ I S ⎢exp⎜ BE ⎟⎥ and iE = I S ⎜1+ ⎢exp⎜ ⎟⎢exp⎜ ⎟⎥ = ⎟⎥ → iC ≅ α F iE ⎝ β F ⎠⎣ ⎝ VT ⎠⎦ α F ⎣ ⎝ VT ⎠⎦ ⎣ ⎝ VT ⎠⎦ ⎛i ⎞ ⎛α i ⎞ vBE ≅ VT ln⎜ C ⎟ = VT ln⎜ F E ⎟ ⎝ IS ⎠ ⎝ IS ⎠
5.64
I SD =
IS
αF
=
1 fA = 1.02 fA 0.98
5.65 Both transistors are in the forward - active region. For simplicity, assume VA = ∞. I = IC1 + I B1 + I B 2 | Since the transistors are identical and have the same VBE ,
IC 2 = IC 1 and I B1 = I B 2 | I = IC1 + 2I B1 = (β F + 2)I B1 | IC 2 = β F I B 2 = β F I B1 IC 2 =
βF
βF + 2
I=
25 25μA | IC 2 = 23.2 μA | See the Current Mirror in Chapter 15. 25 + 2
5.66
CD =
IC 50x10−12 τF = IC = 2x10−9 IC (F) (a) 4 fF (b) 0.4 pF (c) 40 pF VT 0.025
5.67
Using Fig. 2.8 with N =
1018 cm2 cm2 , μ = 260 and μ = 100 n p v-s v-s cm3
W2 WB2 (a) npn : τ F = B = = 2Dn 2VT μn
W2 WB2 = (b) pnp : τ F = B = 2D p 2VT μ p
142
(1x10
−4
cm
)
2
⎛ cm2 ⎞ 2(0.025V )⎜260 ⎟ v - s⎠ ⎝
(1x10
−4
cm
)
= 0.769 ns
2
⎛ cm2 ⎞ 2(0.025V )⎜100 ⎟ v - s⎠ ⎝
= 2.00 ns
5.68
For f >> f β , f T = β ⋅ f = 10(75MHz)= 750 MHz | f β =
fT
βF
=
750 MHz = 3.75 MHz 200
5.69
f T 900 MHz f 900 MHz = = 180 | For f >> 5 MHz, β (f ) = T = = 18 5MHz 50 MHz fβ f
βF = 5.70
6x1018 cm2 cm2 cm2 → μ = 130 using Fig. 2.8. D = μ V = 130 0.025V = 3.25 ( ) n n n T v−s v−s s cm3 2 ⎞⎛ 20 ⎞ ⎛ cm 10 1.60x10−19 C 25x10−8 cm 2 ⎜3.25 ⎟⎜ ⎟ 2 s ⎠⎝ cm6 ⎠ qADn ni ⎝ IS = = = 5.42x10−20 A 18 N AWB 6x10 0.4x10−4 cm cm3 NA =
(
)
(
)
5.71
WB = 2Dnτ F | τ F ≤ 18
1 1 = = 31.8 ps 2πf 2π 5x109
(
)
2
5x10 cm → μn = 135 using Fig. 2.8. 3 v−s cm cm 2 cm2 0.025V = 3.38 Dn = μnVT = 135 ( ) v−s s ⎛ cm2 ⎞ −12 WB ≤ 2⎜ 3.38 ⎟31.8x10 s = 0.147 μm s ⎠ ⎝ NA =
5.72
⎛ V ⎞ ⎛ ⎛ 10 ⎞ 265μA 5 ⎞ 240μA and β FO ⎜1+ ⎟ = IC = β F I B = β FO ⎜1+ CE ⎟ I B | β FO ⎜1+ ⎟ = 3μA 3μA ⎝ VA ⎠ ⎝ VA ⎠ ⎝ VA ⎠ ⎛ 10 ⎞ ⎜1+ ⎟ 80 ⎝ VA ⎠ 265μA = ⇒ VA = 43.1 V | β FO = = 71.7 ⎛ ⎛ 5 ⎞ 5 ⎞ 240μA ⎜1+ ⎟ ⎜1+ ⎟ ⎝ 43.1⎠ ⎝ VA ⎠
5.73
143
⎡ ⎛ V ⎞ ⎤⎛ V ⎞ ⎡ ⎛ 0.72V ⎞ ⎤⎛ 10V ⎞ ( a ) IC = I S ⎢exp⎜ BE ⎟ −1⎥⎜1+ CE ⎟ = 10−16 A⎢exp⎜ ⎟ −1⎥⎜1+ ⎟ = 371 μA ⎣ ⎝ 0.025V ⎠ ⎦⎝ 65V ⎠ ⎣ ⎝ VT ⎠ ⎦⎝ VA ⎠ ⎡ ⎛V ⎞ ⎤ ⎡ ⎛ 0.72V ⎞ ⎤ ( b ) IC = I S ⎢exp⎜ BE ⎟ −1⎥ = 10−16 A⎢exp⎜ ⎟ −1⎥ = 322 μA ⎣ ⎝ 0.025V ⎠ ⎦ ⎣ ⎝ VT ⎠ ⎦ ( c ) 1.15 :1 (a) is 15% larger than (b) due to the Early effect.
5.74
⎛ V ⎞ IC = β F I B = β FO ⎜1+ CE ⎟ I B | We need two Q - points from the output characteristics. ⎝ VA ⎠
For example : (10 mA, 14 V) and
(5 mA, 5 V)
⎛ 14 ⎞ ⎛ 5⎞ 10mA = β FO ⎜1+ ⎟0.1mA and 5mA = β FO ⎜1+ ⎟0.06mA yields ⎝ VA ⎠ ⎝ VA ⎠ ⎛ 14 ⎞ ⎛ 5⎞ 100 = β FO ⎜1+ ⎟ and 83.3 = β FO ⎜1+ ⎟. Solving these two equations yields ⎝ VA ⎠ ⎝ VA ⎠ β FO = 72.9 and VA = 37.6 V. 5.75
⎡ ⎛ V ⎞ ⎤ ⎡ ⎛ V +V ⎞ ⎤ I ⎛V ⎞ BE Fig. 5.16(a) : I E = IC + I B = ⎢β FO ⎜1+ CE ⎟ + 1⎥ I B ≅ ⎢β FO ⎜1+ CB ⎟ + 1⎥ s exp⎜ BE ⎟ VA ⎠ ⎦ β FO ⎝ VT ⎠ ⎣ ⎝ VA ⎠ ⎦ ⎣ ⎝ ⎛ V ⎞ ⎡ 5 + VBE 1 ⎤ + ⎥ 5 x10−15 exp⎜ BE ⎟ = 100μA → VBE = 0.589V by iteration ⎢1+ 19 ⎦ 50 ⎣ ⎝ 0.025 ⎠ ⎛ 5.589 ⎞ 100μA = 4.52 μA | IC = 19⎜1+ IB = ⎟ I B = 95.48 μA ⎡ ⎛ 5.589 ⎞ ⎤ 50 ⎠ ⎝ ⎢19⎜1+ ⎟ + 1⎥ 50 ⎠ ⎦ ⎣ ⎝ ⎛V ⎞ 100μA For VA = ∞, I E = I s exp⎜ BE ⎟ | VBE = 0.025ln = 0.593 V 5 fA ⎝ VT ⎠
(
)
⎛V ⎞ 19(100μA) exp⎜ BE ⎟ → VBE = 0.025ln = 0.667 V β FO 5 fA ⎝ VT ⎠ ⎛ V ⎞ ⎛ 5⎞ IC = β FO ⎜1+ CE ⎟ I B = 19⎜1+ ⎟100μA = 2.09 mA | I E = IC + I B = 2.19 mA ⎝ 50 ⎠ ⎝ VA ⎠
Fig. 5.16(b) : I B =
Is
VBE is independent of VA in the equation above.
5.76
144
⎛ V ⎞ ⎛ 9 + 0.7 ⎞ IC = β F I B | I E = (β F + 1)I B | β F = β FO ⎜1+ CE ⎟ = 50⎜1+ ⎟ = 59.7 50 ⎠ ⎝ ⎝ VA ⎠ IE =
(9 − 0.7)V = 1.01 mA | 8200Ω
5.77
I gm = C VT
IE 1.01mA = = 16.7 μA | IC = 59.7 I B = 0.996 mA βF + 1 60.7
(
)
−23 kT 1.38x10 J / K (300K ) | VT = = = 25.9 mV q 1.60x10−19 C
m =
10−5 A 10−4 A = 0.387 mS (b) g m = = 3.87 mS VT VT
m =
10−3 A 10−2 A = 38.7 mS (d ) g m = = 0.387 S VT VT
(a) g (c) g
IB =
(e) The values of g
m
are the same for the pnp.
5.78
IC 10x10−12 CD = τ F = IC = 3.88x10−10 IC (F) (a) 0.388 fF (b) 0.388 pF (c) 3.88 pF VT 0.0258 5.79 The following are from the Cadence website and the file psrefman.pdf:
IS = 10fA, BF = 100, BR = 1, VAF = ∞, VAR = ∞, TF = 0, TR = 0, NF = 1, NE = 1.5, RB = 0, RC = 0, RE = 0, ISE = 0, ISC = 0, ISS = 0, IKF = ∞, IKR = ∞, CJE = 0, CJC = 0. These default values apply to both npn and pnp transistors. 5.80
⎡ ⎛ i ⎞⎤ ⎛ 1mA ⎞ 1+ ⎢1+ 4⎜ F ⎟⎥ 1+ 1+ 4⎜ ⎟ ⎝ IKF ⎠⎦ ⎝10mA ⎠ ⎣ = = 1.09 → 8.3% reduction (a) KBQ = 2 2 ⎛ 10mA ⎞ 1+ 1+ 4⎜ ⎟ ⎝ 10mA ⎠ i = 1.62 | iC = F = 0.62iF → 38% reduction (a) KBQ = 2 1.62 ⎛ 50mA ⎞ 1+ 1+ 4⎜ ⎟ ⎝ 10mA ⎠ i = 2.79 | iC = F = 0.36iF → 64% reduction (a) KBQ = 2 2.79 NK
5.81
145
12.000 10.000 8.000 6.000
Series1
4.000 2.000 0.000 0.1
1
10
100
1000
Collector Current
5.82
36kΩ 10V = 3.462V | REQ = 36kΩ 68kΩ = 23.54kΩ 36kΩ + 68kΩ 3.462 − 0.7 V IB = = 1.618μA | IC = 50I B = 80.9 μA | I E = 51I B = 82.5 μA 23.54 + (50 + 1)33 kΩ
(a) VEQ =
VCE = 10 − 43000IC − 33000I E = 3.797V | Q - point : (80.9 μA,3.80 V)
7.2kΩ 10V = 3.462V | REQ = 7.2kΩ 13.6kΩ = 4.708kΩ 7.2kΩ + 13.6kΩ 3.462 − 0.7 V IB = = 8.092μA | IC = 50I B = 404.6μA | I E = 51I B = 412.7 μA 4.708 + (50 + 1)6.6 kΩ
(b) VEQ =
VCE = 10 − 8600IC − 6600I E = 3.7976V | Q - point : (405 μA,3.80 V)
68kΩ 10V = 6.538V | REQ = 36kΩ 68kΩ = 23.54kΩ 36kΩ + 68kΩ 10 − 0.7 − 6.538 V = 1.618μA | IC = 50I B = 80.9 μA | I E = 51I B = 82.5 μA IB = 23.54 + (50 + 1)33 kΩ
(c) VEQ =
VEC = 10 − 33000IC − 43000I E = 3.797V | Q - point : (80.9 μA,3.80 V)
13.6kΩ 10V = 6.538V | REQ = 7.2kΩ 13.6kΩ = 4.708kΩ 7.2kΩ + 13.6kΩ 10 − 0.7 − 6.538 V = 8.092μA | IC = 50I B = 404.6μA | I E = 51I B = 412.7 μA IB = 4.708 + (50 + 1)6.6 kΩ
(b) VEQ =
VEC = 10 − 6600IC − 8600I E = 3.7976V | Q - point : (405 μA,3.80 V)
5.83
146
36kΩ 10V = 3.462V | REQ = 36kΩ 68kΩ = 23.54kΩ 36kΩ + 68kΩ V 3.462 − 0.7 = 1.629μA | IC = 75I B = 122.2μA | I E = 76I B = 123.8μA IB = 23.54 + (75 + 1)22 kΩ
(a) VEQ =
VCE = 10 − 43000IC − 22000I E = 2.022V | Q - point : (122μA,2.02V)
68kΩ 10V = 6.538V | REQ = 36kΩ 68kΩ = 23.54kΩ 36kΩ + 68kΩ 10 − 0.7 − 6.538 V = 1.629μA | IC = 75I B = 122.2μA | I E = 76I B = 123.8μA IB = 23.54 + (75 + 1)22 kΩ
VEC = 10 − 420IC − 330I E | From characteristics at VEC = 5V : β F ≅ VEC = 10 − 420IC − 3300
5mA = 83 60μA
84 IC = 10 − 754IC 83
Load line points : IC = 0, VEC = 10V and VEC = 0, IC = 13.3mA − off the graph VEC = 5V , IC = 6.63mA | I B =
10 − 0.7 − 6.538 = 92μA 2354 + (83 + 1)330
From Graph : Q - point : (7.5 mA, 4.3 V)
151
5.93 Writing a loop equation starting at the 9 V supply gives: 9 = 1500(IC + IB ) + 10000IB + VBE
Assuming forward-active region operation, VBE = 0.7 V and IC = βFIB. 9 = 1500(β F I B + I B )+ 10000I B + 0.7
β F (9 − 0.7) 9 − 0.7 and IC = β F I B = 1500(β F + 1)+ 1000 1500(β F + 1)+ 1000
IB =
(a ) I
C
(b) I (c) I
=
C
=
C
=
(d ) I
C
30(9 − 0.7)V
1.5kW(30 + 1)+ 10kW 100(9 − 0.7)V
1.5kΩ(100 + 1)+ 10kΩ 250(9 − 0.7)V
1.5kΩ(250 + 1)+ 10kΩ
=
(9 − 0.7)V = 5.53 mA 1500Ω
= 4.41 mA | VCE = 9 −1500I E = 2.17V | Q - pt : (4.41mA,2.17V) = 5.14 mA | VCE = 9 −1500I E = 1.21V | Q - pt : (5.14mA,1.21V) = 5.37 mA | VCE = 9 −1500I E = 0.913V | Q - pt : (5.37mA,0.913V) | VCE = 9 −1500I E = 0.705V | Q - pt : (5.53mA,0.705V)
5.94
⎛ I ⎞ V − 0.7 VCE = 9 − (IC + I B )1500 | VCE = 9 − ⎜ IC + C ⎟1500 | I B = CE 4 βF ⎠ 10 ⎝ 5mA From Fig. P5.26 at 5V : β F = = 83.3 | VCE = 9 −1518IC 60μA IC = 0, VCE = 9V | VCE = 0, IC = 5.93mA VCE = 0.9V , I B = 20μA | VCE = 1.3V , I B = 60μA | VCE = 1.7V , I B = 100μA From graph : Q - point = (5.0 mA, 1.3 V) 10mA IB = 100 I = 100 B
μA
μA
VCE = 1.7 V I = 80 μA B
Collector Current
IB = 80 μA VCE = 1.5 V
IB = 60 μA
Q-Point 5mA IB = 60 μA VCE = 1.3 V
IB = 40 μA
IB = 40 μA V CE = 1.1 V IB = 20 μA
I = 20 μA B V CE = 0.9 V 0A 0V
5V
V
CE
152
10V
15V
5.95
(a) VEC = 10 − (IC + I B )RC = 10 − I E RC | I E = RC =
For RC = 30kΩ : VCE = 1.5 − 30kΩ(IC + I B )RC = 1.5 − 30kΩ(126)I B | I B =
VCE − 0.65 620kΩ
V − 0.65 VCE = 1.5 − 30kΩ(126) CE → VCE = 0.770V 620kΩ 0.770 − 0.65 IC = 125I B = 125 = 24.2μA | Q - po int : (24.2 μA, 0.770 V ) 620kΩ
5.97
12 = RC (IC + I B )+ VZ + VBE = 500(I E )+ 7.7 | I E = IB =
12 − 7.7 = 8.60mA 500
IE 8.60mA = = 85.2μA | IC = β F I B = 8.52mA | VCE = 7.70V 101 βF + 1
Q - point = (8.52 mA, 7.70 V) 5.95
15− 6 = 6.114V | REQ = 100Ω 7800Ω = 98.73Ω 7800+ 100 20mA VO 20mA 6.14 − 98.7I B − VBE 101.1− VBE + = + → I C = 50I B = 50 IB = 51 51 51(4700Ω) 51(4700Ω) 2.398x105
VEQ = 6+ 100
VBE = 0.025ln
IC 10−16 153
Using MATLAB: fzero('IC107',.02) ---> ans =0.0207 function f=IC107(ic) vbe=0.025*log(ic/1e-16); f=ic-50*(101.1-vbe)/2.398e5; VO = 6.14 − 98.7
20.7mA 20.7mA − .025ln = 5.276 V 51 10−16
5.99 *Problem 5.98 VCC 1 0 DC 15 R1 1 2 7.8K RZ 2 4 100 VZ 4 0 DC 6 Q1 1 2 3 NPN RE 3 0 4.7K IL 3 0 20MA .MODEL NPN NPN IS=1E-16 BF=50 BR=0.25 .OP .END Output voltages will differ slightly due to different value of VT. 5.100
vO = 7 −100iB − vBE = 7 −100iB − VT ln vO = 7 −100iB − VT ln iL − VT ln
iC α i = 7 −100iB − VT ln F L IS IS
αF
IS ⎛ dv di V ⎞ 100Ω 0.025V Ro = − O = −⎜ −100Ω B − T ⎟ = + = 3.21Ω 51 0.02 A diL diL iL ⎠ ⎝
5.101 Since the voltage across the op - amp input must be zero, vO = VZ = 10 V.
Since the input current to the op amp is zero, I E = I +15 = I Z + IC = I Z + α F I E =
154
VO = 100 mA 100
15V −10V 60 + 100mA = 98.5 mA 47kΩ 61
5.102
47Ω = VZ 47Ω + 47Ω and vO = 10 V. Since the input current to the op amp is zero, I 10V ⎛ 41⎞ 15V − 5V + 109mA = 109 mA IE = C = ⎜ ⎟ = 109 mA I +15 = I Z + I E = α F 94Ω ⎝ 40 ⎠ 82kΩ Since the voltage across the op - amp input must be zero, vO
VCEmin = 12.6 − ICmax 1.05(22kΩ) − I Emax 15.2kΩ VCEmin = 12.6 − 5.68 − 3.77V = 3.15V | Q - po int : (246 μA, 3.15 V ) 500 Cases IC (A) VCE (V)
Average Std. Dev. Min Max 156
2.02E-04 1.14E-05 1.71E-04 2.35E-04
4.26 0.32 3.43 5.21
The averages are close to the hand calculations that go with Fig. 5.35. The minimum and maximum values fall within the worst-case analysis as we expect. 5.106 Using the Spreadsheet approach with zero tolerance on the current gain, Eq. set (5.66) becomes:
Note that the current gain tolerance has little effect on the results. 5.107 (a) Approximately 22 cases fall outside the interval [170μA,250μA]: 100% (b) Approximately 125 cases fall inside the interval [3.2V,4.8V]: 100%
22 = 4.4% fail 500
125 = 25% fail 500
5.108 Using the Spreadsheet approach with 50% tolerance on the current gain, a tolerance TP on VCC, and a tolerance TR on resistor values, Eq. set (5.66) becomes: 1.
5. RC = 22000 * (1+ 2 TR (RAND() − 0.5)) | 6. β F = 100 * (1+ 1* (RAND() − 0.5)) 10,000 case Monte Carlo runs indicate that the specifications cannot be achieved even with ideal resistors. For TP = 5% and TR = 0%, 18 % of the circuits fail. With TP = 2% and TR = 0%, 1.5% percent fail. The specifications can be met with TP = 1% and TR = 1%.
VCEmin = 12.6 − ICmax 1.2(22kΩ) − I Emax 12.8kΩ VCEmin = 12.6 − 9.57 − 4.67V = −1.64V! Saturated! The forward - active region assumption is violated. See the next problem. Based upon a Monte Carlo analysis, only about 1% of the circuits actually have this problem, although VCE will be relatively small in many circuits.
158
5.110 Using the Spreadsheet approach: 1. VCC = 12 * (1+ .1* (RAND() − 0.5))
| 2.
3.
R2 = 36000 * (1+ 0.4 * (RAND() − 0.5)) | 4.
5.
RC = 22000 * (1+ 0.4 * (RAND() − 0.5))
7.
VA = 75 * (1+ 0.66 * (RAND() − 0.5))
R1 = 18000 * (1+ 0.4 * (RAND() − 0.5))
| 6.
RE = 16000 * (1+ 0.4 * (RAND() − 0.5))
β F = 100 * (1+ 1* (RAND() − 0.5))
In order to avoid an iterative solution at each step, assume that VCE does not influence the base current. Then, IB =
VEQ − 0.7 and VCE REQ + (β FO + 1)RE
⎛ R ⎞ VCC − β FO IB ⎜ RC + E ⎟ ⎛ V ⎞ αF ⎠ ⎝ = | IC = β FO IB ⎜1+ CE ⎟ ⎛ β R ⎞ ⎝ VA ⎠ 1+ FO IB ⎜ RC + E ⎟ VA ⎝ αF ⎠
500 Cases
VCE (V)
IC (A)
Average Std. Dev. Min** Max
3.81E+00 1.26E+00 -2.07E-01 6.94E+00
2.049E-04 3.785E-05 1.264E-04 3.229E-04
**Note: In this particular simulation, there were 4 cases in which the transistor was saturated.
6.3 ⎛ 2.5 − 0 ⎞ 5 (a ) VH = 2.5 V | VL = 0 V | PVH = I R = 0 mW | PVL = ⎜ ⎟ 10 = 62.5 μW 5 ⎝ 10 ⎠ 2
2
⎛ 3.3 − 0 ⎞ 5 (b) VH = 3.3 V | VL = 0 V | PVH = I R = 0 mW | PVL = ⎜ ⎟ 10 = 109 μW 5 ⎝ 10 ⎠ 2
2
6.4 vO VH (3.3 V)
vI V (0V) L
1.1 V (V REF)
3.3V V+
6.5 v
O
V H (3.3 V)
vI
V L (0V) 1.1 V (V REF)
3.3V V+
()
Z= A =A
6-1
6.6 V REF vI
AV
6.7 V H = 3 V | VL = 0 V | VIH = 2 V | VIL = 1 V | AV =
dvO −3V = = −3 dv I 1V
6.8 V (3 V) H
v
O
Slope = +9 1.5 V
v V (0V)
I
6.9 VOH = 5 V
1.5 V
1.67 V
1.33 V
L
3V V
+
VIH = VREF = 2 V
NM H = 5 − 2 = 3 V VOL = 0 V
VIL = VREF = 2 V
NM L = 2 − 0 = 2 V 6.10 We would like to achieve the highest possible noise margins for both states and have them be symmetrical. Therefore VREF = 3.3/2=1.65 V. 6.11 V H = 3.3 V | VL = 0 V | VIH = 1.8 V | VOL ≅ 0.25 V | VIL = 1.5 V | VIH ≅ 3.0 V NM H = 3.0 −1.8 = 1.2 V | NM L = 1.5 − 0.25 = 1.25 V 6.12 VH = 2.5 V | VL = 0.20 V
6-2
6.13 V H = −0.80 V | VL = −1.35 V 6.14 VIH = VOH − NM H = −0.8 − 0.5 = −1.3 V | VIL = NM L + VOL = 0.5 + (−2) = −1.5 V 6.15 -13 -4 -9 τP = PDP/P = 10 J/10 W = 10 s = 1 ns 6.16
4 x10-6W / gate 1W = μ = 1.60 μA / gate 4 W / gate ( b ) I = 2.5V 2.5 x105 gates (c) PDP = 2ns (4 μW ) = 8 fJ (a ) Pavg =
(b) V10% = VL + 0.1ΔV = 0.20 + 0.23 = 0.43V → t10% ≅ 23 ns for vO V90% = VL + 0.9ΔV = 0.20 + 2.07 = 2.27V → t90% ≅ 33 ns for vO → t r = 33 − 23 = 10 ns For fall time : t10% ≅ 2.5 ns for vO t90% ≅ 0.8 ns for vO → t f = 1.7 ns For v I , t10% ≅ 0 ns t90% ≅ 1 ns t r = 1 ns | t f ≅ 1 ns
(b) V10% = VL + 0.1ΔV = −1.36 + 0.1(0.58) = −1.30V → t10% ≅ 32.5 ns for vO
V90% = VL + 0.9ΔV = −1.36 + 0.9(0.58) = −0.84V → t90% ≅ 42 ns for vO tr = 42 − 32.5 = 9.5 ns For fall time : t10% ≅ 11.5 ns for vO t90% ≅ 2 ns for vO → t f = 9.5 ns For vI , t10% ≅ 0 ns t90% ≅ 1 ns tr = 1 ns | t f ≅ 1 ns
3.3V = 132mA = 0.132 A 10− 9 s For all 64 lines, I = 64(0.132 A) = 8.45 A!
i = 40 x10−12 F 1 ns
t
0
6.31 i(t) 1.32 A
For each line : i = C
3.3V = 1.32 A 10−10 s For all 64 lines, I = 64(1.32 A) = 84.5 A!
i = 40 x10−12 F
0.1 ns t 0
dv dt
6.32
F ⎞⎛ 7.5mm 0.1cm ⎞ ⎛ 3.9⎜ 8.854 x10 −14 ⎟(1.5μm ) ⎟⎜ ⎛ ε ox A ⎞ 3.9ε o LW cm ⎠⎝ 2 mm ⎠ ⎝ ⎟⎟ = 3 = 0.583 pF C = 3⎜⎜ =3 1μm tox ⎝ tox ⎠ 6.33 CΔV KCox" WLΔV | Let W* = αW and L* = αL ΔT = = 1 I ⎛W ⎞ μ nCox" ⎜ ⎟(VGS − VTN )2 2 ⎝L⎠ C *ΔV * K (αW )(αL )(αΔV ) ΔT = = = α ΔT * 1 ⎛ αW ⎞ I 2 μn ⎜ ⎟(αVGS − αVTN ) 2 ⎝ αL ⎠ *
V ε ⎛W ⎞ 2 ⎟(VGS − VTN ) = μ n ox ⎜ 2 Tox ⎝ L ⎠ αV ε ⎛ αW ⎞ 2 2 P* = μn ox ⎜ ⎟(αVGS − αVTN ) = α P 2 αTox ⎝ αL ⎠ P = VI =
V ⎛W μ nCox" ⎜ 2 ⎝L
PDP* = P*ΔT * = (αΔT )α 2 P = α 3 PΔT = α 3 PDP
Power density =
6-8
P P P* α 2P P = | *= = A WL A αW (αL ) A
⎞ 2 ⎟(VGS − VTN ) ⎠
6.34
1 1 ε ⎛W ⎞ ⎛W ⎞ μnCox" ⎜ ⎟(VGS − VTN )2 = μ n ox ⎜ ⎟(VGS − VTN )2 2 2 Tox ⎝ L ⎠ ⎝L⎠ ⎛W ⎞ ⎜ ⎟ ε 1 2 I D* = μn ox ⎜ 2 ⎟(VGS − VTN ) = 2 I D T L 2 ox ⎜ ⎜ ⎟⎟ 2 ⎝ 2 ⎠ (b) P* = V (2 I ) = 2VI = 2 P - The power has increased by a factor of two. ε ε W L CG (c) CG = Cox" WL = ox WL | CG* = ox = Tox 2 2 Tox 2 2 The capacitance has decreased by a factor of two. (a) I D =
⎛ W ⎞⎛ L ⎞ K ⎜ ⎟⎜ ⎟(ΔV ) ΔT C ΔV ⎝ 2 ⎠⎝ 2 ⎠ = (d ) ΔT * = = * 4 I ⎛W ⎞ 1 ⎜ 2 ⎟ 2 μ n ⎜ ⎟(VGS − VTN ) 2 ⎜ L ⎟ ⎜ ⎟ ⎝ 2 ⎠ *
⎛W ⎞ ⎛ ⎛W ⎞ ⎛ ⎛W ⎞ V ⎞ 0.15 ⎞ 4.02 I DS = Kn' ⎜ ⎟ ⎜VH − VTNS − L ⎟VL | 25x10−6 = 100x10−6 ⎜ ⎟ ⎜1.09 − 0.6 − ⎟0.15 → ⎜ ⎟ = 2 ⎠ 1 2⎠ ⎝ L ⎠S ⎝ ⎝ L ⎠S ⎝ ⎝ L ⎠S
( 0.15 + 0.6 −
For vO = VL = 0.15V , VTN = 0.6 + 0.6
)
0.6 = 0.655V
⎛W ⎞ 2 2 Kn' ⎛W ⎞ 100x10−6 ⎛W ⎞ 1 −6 V − V | 25x10 = ⎜ ⎟ ( GSL TNL ) ⎜ ⎟ (2 − 0.15 − 0.655) → ⎜ ⎟ = 2 ⎝ L ⎠L 2 ⎝ L ⎠L ⎝ L ⎠ L 2.86 (c) Using LEVEL=1 KP=100U VTO=0.6 GAMMA=0, the values of ID and VL agree with our hand calculations. The results also agree for GAMMA=0.6. I DL =
6.59
⎛W ⎞ ⎛ 2 VDSL ⎞ Kn' ⎛W ⎞ I DS = I DL | K ⎜ ⎟ ⎜VGSS − VTNS − ⎟VDSL = ⎜ ⎟ (VGSL − VTNL ) 2 ⎠ 2 ⎝ L ⎠L ⎝ L ⎠S ⎝ ⎛ 4.71⎞⎛ 2 Kn' ⎛ 1 ⎞ VO ⎞ Kn' ⎜ ⎜ ⎟⎜2.5 − 0.6 − ⎟VO = ⎟(2.5 − VO − VTNL ) 2⎠ 2 ⎝ 1.68 ⎠ ⎝ 1 ⎠⎝ ' n
(
VTNL = 0.6 + 0.5 VO + 0.6 − 0.6
)
An iterative solution yields VO = 0.1061 V
6.60
⎛W ⎞ ⎛ 2 V ⎞ K ' ⎛W ⎞ I DS = I DL | Kn' ⎜ ⎟ ⎜VH − VTNS − L ⎟VL = n ⎜ ⎟ (2.5 − VL − VTNL ) 2⎠ 2 ⎝ L ⎠L ⎝ L ⎠S ⎝
which is independent of K'n . Ratioed logic maintains VL and VH independent of K'n . So VH = 1.55V and VL = 0.20V. However, I DS = I DL ∝ Kn' : 80 μA V 2 = 64.0 μA P = 2.5V (64μA)= 0.160 mW 100 μA V 2 μA ⎛ 4.71⎞⎛ 0.2 ⎞ Checking : I DS = 80 2 ⎜ ⎟⎜1.55 − 0.6 − ⎟0.2 = 64.1μA 2 ⎠ V ⎝ 1 ⎠⎝
So, I D = 80μA
6-19
6.61
⎛W ⎞ ⎛ 2 V ⎞ K ' ⎛W ⎞ I DS = I DL | Kn' ⎜ ⎟ ⎜VH − VTNS − L ⎟VL = n ⎜ ⎟ (2.5 − VL − VTNL ) 2⎠ 2 ⎝ L ⎠L ⎝ L ⎠S ⎝
which is independent of K'n . Ratioed logic maintains VL and VH independent of K'n . So VH = 1.55V and VL = 0.20V. However, I DS = I DL ∝ Kn' : 120 μA V 2 = 96.0 μA P = 2.5V (96μA)= 0.240 mW 100 μA V 2 0.2 ⎞ μA ⎛ 4.71⎞⎛ Checking : I DS = 120 2 ⎜ ⎟⎜1.55 − 0.6 − ⎟0.2 = 96.1μA 2 ⎠ V ⎝ 1 ⎠⎝
So, I D = 80μA
6.62 Noise Margins vs. KR 2.5
2
1.5 NMH NML 1
0.5
0 0
2
4
6
8
10
12
-0.5 KR
6.63
(a) VH = VDD – VTNL does not depend upon λ. However, VL is dependent upon λ. (b) SPICE yields VL = 0.20 V, 0.207 V, 0.217 V, and 0.232 V for λ = 0, 0.02/V, 0.05/V, and 0.1/V respectively. The current also increases: IDD = 80.1, 82.8, 86.9 and 93.3 μA, respectively. 6.64 VTNL = 0.6 + 0.5 0.20 + 0.6 − 0.6 = 0.660V
(
)
VGSL − VTNL = 4 − 0.2 − 0.66 = 3.14V | VDSL = 2.5 − 0.2 = 2.30V → Triode region ⎛W ⎞ 2.3⎞ 1 μA ⎛ W ⎞ ⎛ 80μA = 100 2 ⎜ ⎟ ⎜ 4 − 0.2 − 0.66 − ⎟2.3 → ⎜ ⎟ = 2 ⎠ V ⎝ L ⎠L⎝ ⎝ L ⎠ L 5.72 ⎛W ⎞ 2.22 0.2 ⎞ μA ⎛ W ⎞ ⎛ 80μA = 100 2 ⎜ ⎟ ⎜ 2.5 − 0.6 − ⎟0.2 → ⎜ ⎟ = 2 ⎠ 1 V ⎝ L ⎠S ⎝ ⎝ L ⎠L
6-20
6.65
(
)
For linear operation at vo = VL : VTNL = 0.8 + 0.5 0.2 + 0.6 − 0.6 = 0.860V VGSL − VTNL ≥ VDSL : VGG − 0.20 − 0.860 ≥ 2.5 − 0.2 → VGG ≥ 3.36V
(
)
We also require : VGG ≥ 2.5 + VTNL = 2.5 + 0.8 + 0.5 2.5 + 0.6 − 0.6 = 3.79V so VGG ≥ 3.79V 6.66
⎛W ⎞ ⎛ 2 V ⎞ K ' ⎛W ⎞ = VDD | I DS = I DL | Kn' ⎜ ⎟ ⎜VDD − VTNS − L ⎟VL = n ⎜ ⎟ (VTNL ) 2⎠ 2 ⎝ L ⎠L ⎝ L ⎠S ⎝
For ratioed logic, both VH and VLare independent of K'n . VH = 2.5 V | VL = 0.2 V ⎛ 80 ⎞ However, I D ∝ Kn' | I DS = 80μA⎜ ⎟ = 64μA | P = 2.5V (64μA) = 0.160 mW ⎝ 100 ⎠ ⎛120 ⎞ (b) VH = 2.5 V VL = 0.2 V I DS = 80μA⎜⎝100 ⎟⎠ = 96μA | P = 2.5V (96μA)= 0.240 mW
Ron R R + on = on and the total area AT ∝ (WL)A + (WL)B ⎛W ⎞ ⎛W ⎞ K ⎜ ⎟ ⎜ ⎟ ⎝ L ⎠A ⎝ L ⎠B
1 1 1 KW B KW B W B2 + = → WA = → AT ∝ + WB = WB − K WB − K WB − K WA WB K d ⎛ W B2 ⎞ W B2 − 2KW B Finding the minimum : = 0 → W B = 2K & WA = 2K. ⎜ ⎟= dWB ⎝ W B − K ⎠ (W B − K )2
Setting L = 1,
6.84
+2.5 V ML
1.81 1 Y
M
MA A
6-28
2.22 1
B
2.22 1
MD
MC
B
C
2.22 1
D
2.22 1
6.85
+2.5 V ML
1.81 1
Y D
MD
8.88 1
C
MC
8.88 1
B
MB
8.88 1
A
MA
8.88 1
6.86 +2.5 V ML 1.11 1 Y
A
2.22 1
MC
MB
MA B
2.22 1
C
2.22 1
(a ) With A = B = C = 1, the circuit is equivalent to a single 6.66/1 switching device. ⎛ 6.66 ⎞⎛ 2 40μA ⎛1.81⎞ VL ⎞ 100μA⎜ ⎟⎜ 2.5 − 0.6 − ⎟VL = ⎜ ⎟(0.6) → VL = 0.1033V 2⎠ 2 ⎝ 1 ⎠ ⎝ 1 ⎠⎝ 2 40μA ⎛ 1.81⎞ (b) I DD = 2 ⎜⎝ 1 ⎟⎠(0.6) = 13.0 μA
⎛ W ⎞ 1.81 Y = (A + B)(C + D)(E + F ) | ⎜ ⎟ = 1 ⎝ L ⎠L
⎛ W⎞ ⎛ 2.22 ⎞ 6.66 | ⎜ ⎟ =3⎜ ⎟= 1 ⎝ L ⎠ A−F ⎝ 1 ⎠
6.91 (a) The only change to the schematic is to connect the gate of load transistor ML to its drain instead of its source. (b) There is no change to the logic function Y = (A + B)(C + D)(E + F ) ⎛ W⎞ ⎛ W⎞ ⎛ 4.71⎞ 14.1 1 | ⎜ ⎟ =3⎜ ⎟= (c) ⎜ ⎟ = 1 ⎝ L ⎠ L 1.68 ⎝ L ⎠ ABCDEF ⎝ 1 ⎠
6-31
6.92
⎛ W ⎞ 1.11 Y = (A + B)(C + D)E | ⎜ ⎟ = 1 ⎝ L ⎠L
⎛ W⎞ ⎛ 2.22 ⎞ 6.66 | ⎜ ⎟ =3⎜ ⎟= 1 ⎝ L ⎠ A− E ⎝ 1 ⎠
6.93 (a) In the new circuit schematic, the PMOS transistor is replaced with a saturated NMOS load device as in Fig. 6.29(b). (b) The logic function is unchanged: Y = (A + B)(C + D)E ⎛ W⎞ ⎛ W⎞ ⎛ 4.71⎞ 14.1 1 (c) ⎜ ⎟ = | ⎜ ⎟ =3⎜ ⎟= 1 ⎝ L ⎠ L 1.68 ⎝ L ⎠ ABCDE ⎝ 1 ⎠ 6.94
⎡ ⎛ 2.22 ⎞⎤ 26.6 ⎛ W⎞ ⎛ W⎞ 1 1 1 1 17.8 = 3 | + + = →⎜ ⎟ = ⎢4 ⎜ ⎜ ⎟ ⎟⎥ = ⎛ W⎞ ⎛ 26.6 ⎞ ⎛ W ⎞ 2.22 1 1 ⎝ L ⎠ A, C , D , F ⎝ L ⎠B , E ⎣ ⎝ 1 ⎠⎦ 3 ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ 1 ⎝ L ⎠B ⎝ 1 ⎠ ⎝ L ⎠E
6.95 (a) In the new circuit schematic, the PMOS transistor is replaced with a saturated NMOS load device as in Fig. 6.29(b). (b) There is no change to the logic function Y = ACDF + ACE + BDE + BF ⎛ W⎞ ⎛ W⎞ ⎛ 4.71⎞ 18.8 1 (c) ⎜⎝ L ⎟⎠ = 1.68 | ⎜⎝ L ⎟⎠ = 4 ⎜⎝ 1 ⎟⎠ = 1 L ACDF RoB + RonD + RonE setting RoB = RonE : ⎛ W ⎞ 12.6 1 1 1 2 1 1 + + = + = →⎜ ⎟ = ⎛ W⎞ ⎛ W⎞ 18.8 ⎛ W ⎞ 18.8 4.71 ⎝ L ⎠ B 1 ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ L ⎠B ⎝ L ⎠E ⎝ L ⎠B Checking : RoB + RonF =
6-32
1 1 1 1 + = ≤ so path BF is ok. 18.8 12.6 7.42 4.71
6.96
+2.5 V
Y D E
B C
A ⎛W ⎞ 1.81 ⎜ ⎟ = 1 ⎝ L ⎠L DCA and ECA paths contain three devices ⎛W ⎞ ⎛ 2.22 ⎞ 6.66 = 3⎜ ⎜ ⎟ ⎟= 1 ⎝ L ⎠ A,C , D, E ⎝ 1 ⎠ 1 1 1 + = ⎛W ⎞ ⎛W ⎞ ⎛ 2.22 ⎞ ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ L ⎠ A ⎝ L ⎠B ⎝ 1 ⎠ ⎛W ⎞ 1 1 1 3.33 + = →⎜ ⎟ = ⎛ 6.66 ⎞ ⎛W ⎞ ⎛ 2.22 ⎞ ⎝ L ⎠ 1 B ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ 1 ⎠ A ⎝ 1 ⎠B ⎝ 1 ⎠
6-33
6.97
+2.5 V
C
E
B D
A
⎛W ⎞ 1 ⎛1.11⎞ 1 ⎜ ⎟ = ⎜ ⎟= ⎝ L ⎠ L 2 ⎝ 1 ⎠ 1.80 CBA and EDA paths contain three devices ⎛W ⎞ 1 ⎛ 2.22 ⎞ 3.33 = (3)⎜ ⎜ ⎟ ⎟= 1 ⎝ L ⎠ A− E 2 ⎝ 1 ⎠
6-34
6.98
+2.5 V
Y
C E
B D
A
⎛W ⎞ 1 ⎜ ⎟ = ⎝ L ⎠ L 1.68
CBA and EDA paths contain three devices ⎛W ⎞ ⎛ 4.71⎞ 14.1 = 3⎜ ⎜ ⎟ ⎟= 1 ⎝ L ⎠ A− E ⎝ 1 ⎠
(c) Assuming equal voltage drops (0.10V) across MP and MS : MP must carry one unit of load current with one - half the drain - source ⎛ W⎞ 4.44 voltage (VDS = 0.10V ) of the switching transistor in Fig.6.29(d). → ⎜ ⎟ = 1 ⎝ L ⎠P MS must carry two units of load current with one - half the drain - source ⎛ W⎞ 8.88 voltage (VDS = 0.10V ) of the switching transistor in Fig.6.29(d). → ⎜ ⎟ = 1 ⎝ L ⎠S (d) MS will not change. MP will need to be somewhat larger. (e) Coincidence gate (Exclusive NOR)
6.107 Original design 0.20 mW - 1 mW requires 5 times larger current. ⎛ W⎞ 28.8kΩ 2.22 11.1 (a) R = = 5.76kΩ ⎜ ⎟ = 5 = 5 1 1 ⎝ L ⎠S
6.110 ⎛ W⎞ ⎛ 1.81⎞ 5.43 ⎛ W⎞ ⎛ 6.66 ⎞ 20.0 ⎛ W⎞ ⎛ 3.33 ⎞ 9.99 (a) ⎜⎝ L ⎟⎠ = 3⎜⎝ 1 ⎟⎠ = 1 | ⎜⎝ L ⎟⎠ = 3⎜⎝ 1 ⎟⎠ = 1 | ⎜⎝ L ⎟⎠ = 3⎜⎝ 1 ⎟⎠ = 1 L BCD A ⎛ W ⎞ 1 ⎛1.81⎞ ⎛ W⎞ ⎛ W⎞ 1 1 1 ⎛ 6.66 ⎞ 1.33 1 ⎛ 3.33 ⎞ (b) ⎜⎝ L ⎟⎠ = 5 ⎜⎝ 1 ⎟⎠ = 2.76 | ⎜⎝ L ⎟⎠ = 5 ⎜⎝ 1 ⎟⎠ = 1 | ⎜⎝ L ⎟⎠ = 5 ⎜⎝ 1 ⎟⎠ = 1.50 L BCD A 6.111 ⎛ W⎞ ⎛ W⎞ ⎛ W⎞ ⎛ 1 ⎞ 1 1 1 1 ⎛1.81⎞ 1 ⎛ 4.44 ⎞ (a) ⎜⎝ L ⎟⎠ = 10 ⎜⎝ 1 ⎟⎠ = 5.53 | ⎜⎝ L ⎟⎠ = 10 ⎜⎝ 1 ⎟⎠ = 2.25 | ⎜⎝ L ⎟⎠ = 2⎜⎝ 2.25⎟⎠ = 1.13 L AB CD ⎞ ⎛ W ⎞ 2.5 ⎛1.81⎞ 4.53 ⎛ W⎞ ⎛ ⎛ ⎛ 11.1⎞ 22.2 2.5 4.44 11.1 W⎞ (b) ⎜⎝ L ⎟⎠ = 1 ⎜⎝ 1 ⎟⎠ = 1 | ⎜⎝ L ⎟⎠ = 1 ⎜⎝ 1 ⎟⎠ = 1 | ⎜⎝ L ⎟⎠ = 2⎜⎝ 1 ⎟⎠ = 1 L AB CD 6.112 ⎛ W⎞ ⎛ 1.11⎞ 4.44 ⎛ W⎞ ⎛ 6.66 ⎞ 26.6 (a) ⎜⎝ L ⎟⎠ = 4⎜⎝ 1 ⎟⎠ = 1 | ⎜⎝ L ⎟⎠ = 4⎜⎝ 1 ⎟⎠ = 1 L ABCDE ⎞ ⎛ W ⎞ 1 ⎛1.11⎞ ⎛ 1 W 1 ⎛ 6.66 ⎞ 2.22 (b) ⎜⎝ L ⎟⎠ = 3 ⎜⎝ 1 ⎟⎠ = 2.70 | ⎜⎝ L ⎟⎠ = 3 ⎜⎝ 1 ⎟⎠ = 1 L ABCDE 6.113
⎛W ⎞ 2 2 1 1 ε ⎛W ⎞ (a) I D = μnCox" ⎜ ⎟(VGS − VTN ) = μn ox ⎜ ⎟(VGS − VTN ) 2 2 Tox ⎝ L ⎠ ⎝ L⎠ ⎛W ⎞ 2 1 ε ⎜ ⎟ I* I D* = μn ox ⎜ 2 ⎟(VGS − VTN ) = 2I D | D = 2 ID 2 Tox ⎜ L ⎟ 2 ⎝2⎠
(b) PD* = V (2I )= 2VI = 2PD - Power dissipation has increased by a factor of two.
6-41
6.114
dv | Assume the transition occurs in ΔT seconds generating dt 2.5V a current pulse with constant amplitude I = 10x10−12 F . ΔT 2.5x10−11 ΔT Then I avg = = 500μA and P = 64(2.5V )I avg = 64(2.5)(0.50mA)= 80 mW 50ns ΔT ⎛ 3.3 ⎞2 2 (b) P ∝V so P = 80mW ⎜ ⎟ = 139 mW ⎝ 2.5 ⎠
For each line : i = C
6.115 C C τ PHL ∝ and τ PLH ∝ KS KL
C C"oxWL L2 | For either case, τ PHL ∝ = = μn KS " W μnCox L
⎛W ⎞ 2 100x10−6 ⎛W ⎞ 1 ⎜ ⎟ (2.5 − 0.20 − 0.66) → ⎜ ⎟ = 2 ⎝ L ⎠L ⎝ L ⎠ L 1.68
80x10−6 =
(b) 80x10
−6
=
⎛W ⎞ 2 100x10−6 ⎛W ⎞ 1 ⎜ ⎟ (2.5 − 0.20 − 0.6) → ⎜ ⎟ = 2 ⎝ L ⎠L ⎝ L ⎠ L 1.81
⎛W ⎞ ⎛ ⎛W ⎞ 2.3 ⎞ 1 = 100x10−6⎜ ⎟ ⎜4 − 0.20 − 0.66 − ⎟2.3 → ⎜ ⎟ = 2 ⎠ ⎝ L ⎠L ⎝ ⎝ L ⎠ L 5.72 ⎛W ⎞ ⎛ ⎛W ⎞ 2.3 ⎞ 1 (d ) 80x10−6 = 100x10−6⎜⎝ L ⎟⎠ ⎜⎝4 − 0.20 − 0.6 − 2 ⎟⎠2.3 → ⎜⎝ L ⎟⎠ = 5.89 L L
(c) 80x10
−6
(e) V
TN
(
)
= −1+ 0.5 0.20 + 0.6 − 0.6 = −0.940V
⎛W ⎞ 1.81 2 100x10 ⎛W ⎞ ⎜ ⎟ (−0.940) → ⎜ ⎟ = 2 1 ⎝ L ⎠L ⎝ L ⎠L ⎛W ⎞ 1.60 2 100x10−6 ⎛W ⎞ (f ) 80x10−6 = 2 ⎜⎝ L ⎟⎠ (−1) → ⎜⎝ L ⎟⎠ = 1 L L 80x10−6 =
−6
6-47
6.131 For VDD = -2.5 V, we have VH = -0.20 V with a power dissipation of 0.20 mW. Since these gates are all ratioed logic design, the ratio of the W/L ratios of the load and switching transistors does not change. We only need to scale both equally to achieve the power level. ⎛ W ⎞ 100 2.22 5.55 = (a) RL = 28.8kΩ | ⎜ ⎟ = 1 ⎝ L ⎠ S 40 1 ⎛W ⎞ 100 1 ⎛ W ⎞ 100 4.71 11.8 1.49 (b) ⎜ ⎟ = = | ⎜ ⎟ = = 1 1 ⎝ L ⎠ L 60 1.68 ⎝ L ⎠ S 60 1 ⎛W ⎞ 100 1 ⎛ W ⎞ 100 1 5.55 (c) ⎜ ⎟ = = | ⎜ ⎟ = 2.22 = 1 ⎝ L ⎠ L 60 5.72 2.29 ⎝ L ⎠ S 60 ⎛W ⎞ 100 1.81 4.53 ⎛ W ⎞ 100 2.22 5.55 (d ) ⎜ ⎟ = = | ⎜ ⎟ = = 1 1 ⎝ L ⎠ L 60 1 ⎝ L ⎠ S 60 1 ⎛W ⎞ 100 1.11 2.78 ⎛ W ⎞ 100 2.22 5.55 (e) ⎜ ⎟ = = | ⎜ ⎟ = = 1 1 ⎝ L ⎠ L 60 1 ⎝ L ⎠ S 60 1
VTPL = −0.6 − 0.75 VH + 0.7 − 0.7 Solving the last two equations iteratively : VH = 2.30 V 6.135 Y is low only when both A and B are high : Y = AB or Y = AB.
Alternatively, Y is high when either A or B is low : Y = A + B = AB 6.136 Y is high only when both A and B are low : Y = AB or Y = A + B 6.137 0.0V
-0.5V
-1.0V
-1.5V
2 0V
VL = -1.90 and VH = -0.156 agree with the hand calculations in Prob. 6.132 6.138 -0.0V
-1.0V
-2.0V
3 0V
VH = -0.33 and VL -2.08 agree with the design values in Prob. 6.133.
−14 3.9εo ⎛ cm 2 ⎞ (3.9) 8.854x10 F / cm K = µ nC = µ n = µn = ⎜ 500 ⎟ Tox Tox V − sec ⎠ 10x10−9 m(100cm / m) ⎝ ' n
εox
" ox
)
F A µA = 173 x 10−6 2 = 173 2 V − sec V V ⎛ ⎞ µ 200 µA µA K 'p = µ pCox" = p Kn' = ⎜ ⎟173 2 = 69.1 2 µn V V ⎝ 500 ⎠ Kn' = 173x10−6
7.2 V
DD
vI
(5 V) B
V
S
D
p+
p+
n+
vo
D
SS
(0 V)
S
n+
n+
B
p+
p-well
PMOS transistor Ohmic contact
NMOS transistor
n-type substrate
Ohmic contact
7.3
⎛ pA ⎞ A = ⎜ 500 2 ⎟(1cm x 0.5cm)= 250 pA cm ⎠ ⎝ ⎛ pA ⎞ (b) I = I S A + 20x106 ⎜⎝100 cm2 ⎟⎠ 2x10−4 cm 5x10−4 cm = 250 + 200 = 450 pA
(a) I = I
S
(
)
(
)(
)
(c) Same as (b) 7.4
F ⎞⎛ 10mm 0.1cm ⎞ ⎛ 3.9⎜ 8.854 x10 −14 ⎟(1µm ) ⎟⎜ ⎛ ε ox A ⎞ 3.9ε o LW cm ⎠⎝ 2 mm ⎠ ⎝ ⎟⎟ = 3 C = 3⎜⎜ = 0.518 pF =3 t ox 1µm ⎝ t ox ⎠ 7.5
(a) VH = 2.5 V, VL = 0 V (b) VH = 1.8 V, VL = 0 V
7-1
7.6 (a) VH = 2.5 V, VL = 0 V (b) Same as (a). VH and VL don't depend upon W/L in a CMOS gate. 7.7 (a) VH = 3.3 V, VL = 0 V (b) Same as (a). VH and VL don't depend upon W/L in a CMOS gate. 7.8 (a) VH = 2.5V | VL = 0V | For MN , VGS = 0, so MN is cut off. For MP , VGS = −2.5, VDS = 0V and VTP = -0.60V. For VDS < VGS - VTP , M P is in the triode region.
(b) For M
N
, VGS = 2.5, VDS = 0V and VTN = 0.60V. For VDS < VGS - VTN , M N is in the triode region.
For MP , VGS = 0, so M P is cut off.
(c) For M
N
, VGS = 1.25, VDS = 1.25 V and VTN = 0.60V. For VDS > VGS - VTN , MN is saturated.
For MP , VGS = −1.25, VDS = -1.25V and VTP = -0.75V. For VDS > VGS - VTP , MP is saturated.
7.9 (a) VH = 3.3V | VL = 0V | For MN , VGS = 0, so MN is cut off. For MP , VGS = −3.3, VDS = 0V and VTP = -0.75V. For VDS < VGS - VTP , M P is in the triode region.
(b) For M
N
, VGS = 3.3, VDS = 0V and VTN = 0.75V. For VDS < VGS - VTN , MN is in the triode region.
For MP , VGS = 0, so MP is cut off.
(c) For M
N
, VGS = 1.65, VDS = 1.65 V and VTN = 0.75V. For VDS > VGS - VTN , MN is saturated.
For MP , VGS = −1.65, VDS = -1.65V and VTP = -0.75V. For VDS > VGS - VTP , MP is saturated.
7.10 (a) VH = 0 V, VL = -5.2 V (b) Same as (a). VH and VL don't depend upon W/L in a CMOS gate.
7-2
7.11 For vI = vO, both transistors will be saturated since vGS = vDS for each device. Equating the drain currents with Kn = Kp yields: (a) Both transistors are saturated with VDS = VGS
K 2 2 Kn vI − VTN ) = p (v I − VDD − VTP ) so vI − VTN = VDD − vI + VTP ( 2 2 V + VTN + VTP 2.5 + 0.6 − .6 vO = vI = DD = = 1.25V 2 2 2 2 K 100µA ⎛ 2 ⎞ (b) I DN = 2n (vI − VTN ) = 2 ⎜⎝ 1 ⎟⎠(1.25 − 0.6) = 42.3µA K 2 2 40µA ⎛ 5 ⎞ Checking I DP = p (vI − VDD − VTp ) = ⎜ ⎟(1.25 − 2.5 + 0.6) = 42.3µA 2 ⎝1⎠ 2
(c) For K
n
= 2.5K p ,
K 2.5K p 2 2 vI − VTN ) = p (vI − VDD − VTP ) or 1.58(vI − VTN )= VDD − vI + VTP ( 2 2 V + 1.58VTN + VTP 2.5 + 1.58(0.6)+ (−0.6) vO = vI = DD = = 1.104V 2.58 2.58 2 100µA ⎛ 2 ⎞ (d ) I DN = 2 ⎜⎝ 1 ⎟⎠(1.104 − 0.6) = 25.4µA | Check by finding IDP : 2 40µA ⎛ 2 ⎞ I DP = ⎜ ⎟(1.104 − 2.5 + 0.6) = 25.3µA 2 ⎝ 1⎠ 7.12 (a) For vI = vO, both transistors will be saturated since vGS = vDS for each device. Equating the drain currents with Kn = Kp yields: K 2 2 Kn vI − VTN ) = p (vI − VDD − VTP ) and vI − VTN = VDD − v I + VTP i () ( 2 2 V + VTN + VTP 3.3 + 0.75 − 0.75 vO = vI = DD = = 1.65V 2 2 2 2 K 100µA ⎛ 2 ⎞ (ii) I DN = 2n (vI − VTN ) = 2 ⎜⎝ 1 ⎟⎠(1.65 − 0.75) = 81µA 2 2 K 40µA ⎛ 5 ⎞ Checking : I DP = P (vI − VDD + VTP ) = ⎜ ⎟(1.65 − 3.3 + 0.75) = 81µA 2 ⎝ 1⎠ 2
For Kn = 2.5 Kp,
7-3
2.5K p K 2 2 vI − VTN ) = p (v I − VDD − VTP ) so 1.58(vI − VTN )= VDD − vI + VTP ( 2 2 V + 1.58VTN + VTP 3.3 + 1.58(0.75)+ (−0.75) vO = vI = DD = = 1.448V 2.58 2.58 2 100µA ⎛ 2 ⎞ (iv ) I DN = 2 ⎜⎝ 1 ⎟⎠(1.448 − 0.75) = 48.7µA | Check by finding I DP : 2 40µA ⎛ 2 ⎞ I DP = ⎜ ⎟(1.448 − 3.3 + 0.75) = 48.6µA 2 ⎝1⎠
(iii )
(b) For vI = vO, both transistors will be saturated since vGS = vDS for each device. Equating the drain currents with Kn = Kp yields: K 2 2 Kn vI − VTN ) = p (vI − VDD − VTP ) and vI − VTN = VDD − v I + VTP i () ( 2 2 V + VTN + VTP 2.5 + 0.6 − 0.6 vO = vI = DD = = 1.25V 2 2 2 2 K 100µA ⎛ 2 ⎞ (ii ) I DN = 2n (vI − VTN ) = 2 ⎜⎝ 1 ⎟⎠(1.25 − 0.6) = 42.3µA K 2 2 100µA ⎛ 2 ⎞ Checking : I DP = p (vI − VDD + VTP ) = ⎜ ⎟(1.25 − 2.5 + 0.6) = 42.3µA 2 ⎝1⎠ 2 For Kn = 2.5 Kp, 2.5K p K 2 2 vI − VTN ) = p (v I − VDD − VTP ) and 1.58(v I − VTN ) = VDD − v I + VTP ( 2 2 V + 1.58VTN + VTP 2.5 + 1.58(0.60)+ (−0.60) vO = vI = DD = = 1.104V 2.58 2.58 2 100µA ⎛ 2 ⎞ (iv ) I DN = 2 ⎜⎝ 1 ⎟⎠(1.104 − 0.60) = 25.4µA | Check by finding I DP : 2 40µA ⎛ 2 ⎞ I DP = ⎜ ⎟(1.104 − 2.5 + 0.60) = 25.3µA 2 ⎝1⎠
(iii )
7-4
7.13 (a) For vI = vO, both transistors will be saturated since vGS = vDS for each device. Equating the drain currents with Kn = Kp yields: K 2 2 Kn vI − VTN ) = p (vI − VDD − VTP ) and vI − VTN = VDD − v I + VTP i () ( 2 2 V + VTN + VTP 1.8 + 0.5 − 0.5 vO = vI = DD = = 0.90V 2 2 2 2 K 100µA ⎛ 2 ⎞ (ii ) I DN = 2n (vI − VTN ) = 2 ⎜⎝ 1 ⎟⎠(0.9 − 0.5) = 16.0µA 2 2 K 40µA ⎛ 5 ⎞ Checking : I DP = P (vI − VDD − VTP ) = ⎜ ⎟(0.9 −1.8 + 0.5) = 16.0µA 2 ⎝ 1⎠ 2
For Kn = 2.5 Kp, 2.5K p K 2 2 vI − VTN ) = p (v I − VDD − VTP ) so 1.58(vI − VTN )= VDD − vI + VTP ( 2 2 V + 1.58VTN + VTP 1.8 + 1.58(0.5)+ (−0.5) vO = vI = DD = = 0.810V 2.58 2.58 2 100µA ⎛ 2 ⎞ (iv ) I DN = 2 ⎜⎝ 1 ⎟⎠(0.810 − 0.5) = 96.2µA | Check by finding I DP : 2 40µA ⎛ 2 ⎞ I DP = ⎜ ⎟(0.8101−1.8 + 0.5) = 96.0µA 2 ⎝1⎠
(iii )
(b) For vI = vO, both transistors will be saturated since vGS = vDS for each device. Equating the drain currents with Kn = Kp yields: K 2 2 Kn vI − VTN ) = p (vI − VDD − VTP ) and vI − VTN = VDD − v I + VTP i () ( 2 2 V + VTN + VTP 2.5 + 0.75 − 0.65 vO = vI = DD = = 1.30V 2 2 2 2 K 100µA ⎛ 2 ⎞ (ii ) I DN = 2n (vI − VTN ) = 2 ⎜⎝ 1 ⎟⎠(1.30 − 0.75) = 30.3µA K 2 2 40µA ⎛ 5 ⎞ Checking : I DP = p (vI − VDD + VTP ) = ⎜ ⎟(1.30 − 2.5 + 0.65) = 30.3µA 2 ⎝ 1⎠ 2
7-5
For Kn = 2.5 Kp, 2.5K K 2 2 (iii ) 2 p (vI − VTN ) = 2p (vI − VDD − VTP ) and 1.58(vI − VTN )= VDD − vI + VTP V + 1.58VTN + VTP 2.5 + 1.58(0.75)+ (−0.65) vO = vI = DD = = 1.176V 2.58 2.58 2 100µA ⎛ 2 ⎞ (iv ) I DN = 2 ⎜⎝ 1 ⎟⎠(1.176 − 0.75) = 18.2µA | Check by finding I DP : 2 40µA ⎛ 2 ⎞ I DP = ⎜ ⎟(1.176 − 2.5 + 0.65) = 18.2µA 2 ⎝1⎠ (c) For vI = vO, both transistors will be saturated since vGS = vDS for each device. Equating the drain currents with Kn = Kp yields: K 2 2 Kn vI − VTN ) = p (vI − VDD − VTP ) and vI − VTN = VDD − v I + VTP i () ( 2 2 V + VTN + VTP 2.5 + 0.65 − 0.75 vO = vI = DD = = 1.20V 2 2 2 2 K 100µA ⎛ 2 ⎞ (ii ) I DN = 2n (vI − VTN ) = 2 ⎜⎝ 1 ⎟⎠(1.20 − 0.65) = 30.3µA K 2 2 40µA ⎛ 5 ⎞ Checking : I DP = p (vI − VDD + VTP ) = ⎜ ⎟(1.20 − 2.5 + 0.75) = 30.3µA 2 ⎝ 1⎠ 2 For Kn = 2.5 Kp, 2.5K p K 2 2 vI − VTN ) = p (v I − VDD − VTP ) and 1.58(v I − VTN ) = VDD − v I + VTP ( 2 2 V + 1.58VTN + VTP 2.5 + 1.58(0.65)+ (−0.75) vO = vI = DD = = 1.076V 2.58 2.58 2 100µA ⎛ 2 ⎞ (iv ) I DN = 2 ⎜⎝ 1 ⎟⎠(1.076 − 0.65) = 18.2µA | Check by finding I DP : 2 40µA ⎛ 2 ⎞ I DP = ⎜ ⎟(1.076 − 2.5 + 0.75) = 18.2µA 2 ⎝1⎠
.PRINT DC V(2) .END Result: vI = 1.104 V K 2.5K p 2 2 vI − VTN ) = p (VDD − vI + VTP ) and 1.58(vI − VTN )= VDD − vI + VTP ( 2 2 V + 1.58VTN + VTP 2.5 + 1.58(0.6)+ (−0.6) vO = vI = DD = = 1.10 V 2.58 2.58 7.15 (a) VH = 3.3 V. For vO = VL , assume MP is saturated and MN is in the triode region.
The average capacitance of 212 fF that is required to fit the results is consistent with the device capacitances calculated by SPICE. The approximate 3:1 relationship holds between rise/fall times and the propagation delay times in the first inverter. The first inverter response is faster than that of the fourth inverter because of the rapid rise and fall times on the input signal. The first inverter response is closest to our model used for hand calculations. However, the response of inverter four would be more representative of the actual logic situation. 7.32
(a)
100W = 1µW / gate 100 x10 6 gates
(b) I =
100W = 55.6 A 1.8V
7.33 (a)
5W = 2.5µW / gate 2x106 gates
(b) C =
2.5x10-6
(
2.52 5x106
)
2 P = CVDD f ;C =
2.5x10-6
(
3.32 5x106
)
= 45.9 fF
= 80.0 fF
7.34
⎛ pA ⎞ A = ⎜ 400 2 ⎟(0.5cm x 1cm)= 200 pA cm ⎠ ⎝ ⎛ pA ⎞ (b) I = I S A + 75x106 ⎜⎝150 cm2 ⎟⎠ 2.5x10−4 cm 1x10−4 cm = 200 + 281 = 481pA
(a ) I = I
S
(
)
(
)(
)
(c) Same as (b) 7.35
(
)( )101
2 f = 64 25x10-12 2.52 (a) P = 64CVDD
7.36
7-16
−8
= 1.00 W
(
)( )101
(b) P = 64 25x10-12 3.32
−8
= 1.74 W
Peak current occurs for vO = v I . Assume both transistors are saturated since vO = vI . 2 2 20 ⎛100x10−6 ⎞ 20 ⎛ 40x10−6 ⎞ v − V = ⎜ ⎟( I ⎜ ⎟(v I − VDD − VTP ) →1.58(v I − VTN ) = VDD − v I + VTP TN ) 2 1⎝ 1⎝ 2 ⎠ ⎠ 3.3 + 1.58(0.6)+ (−0.6) VDD + 1.58VTN + VTP = = 1.414 V 2.58 2.58 2 20 ⎛ 100x10−6 ⎞ iD = ⎜ ⎟(1.414 − 0.6) = 663 µA 2 1⎝ ⎠
First inverter : t r = 4.6 ns, t f = 5.4 ns, τ PLH = 2.6 ns, τ PHL = 2.1 ns Fourth inverter : t r = 5.8 ns, t f = 6.3 ns, τ PLH = 4.2 ns, τ PHL = 4.7 ns
τ PHL = 1.2RonnC =
τ PLH = 1.2RonpC =
0.25x10−12
⎛ 2⎞ −6 ⎜ ⎟ 50x10 (2.5 − 0.91) 1 ⎝ ⎠
(
)
0.25x10−12
= 1.58ns
⎛ 5⎞ −6 ⎜ ⎟ 20x10 (2.5 − 0.77) ⎝ 1⎠
(
)
= 1.45ns
The inverters are slower than the equations predict because of the additional capacitances in the transistor models. The effective capacitance appears to be approximately 0.4 pF. The delay of the interior inverter is substantially slower than predicted by the formula because of the slow rise and fall times of the driving signals.
First inverter : t r = 43.7 ns, t f = 20.6 ns, τ PLH = 19.7 ns, τ PHL = 9.7 ns Fourth inverter : t r = 47.5 ns, t f = 31.4 ns, τ PLH = 30.4 ns, τ PHL = 25.7 ns
τ PHL = 1.2 RonnC =
τ PLH = 1.2 RonpC =
1.2 x10−12
⎛ 2⎞ −6 ⎜ ⎟ 50 x10 (2.5 − 0.91) ⎝ 1⎠
(
)
1.2 x10−12
= 7.5 ns
⎛ 2⎞ −6 ⎜ ⎟ 20 x10 (2.5 − 0.77) ⎝ 1⎠
(
)
= 17.3 ns
The inverters are slower than the equations predict because of the additional capacitances in the transistor models. The delay of the interior inverter is substantially slower than predicted by the formula because of the slow rise and fall times of the driving signals.
7-26
7.48 (a) V
DD
20 1
D
20 1
C
20 1
B
20 1 vo
2 1
2 1
B
C
2 1
D
2 1
(b ) NMOS : 3 ⎛⎜ 2 ⎞⎟ = 6 ⎝1⎠
⎛ 20 ⎞ 60 | PMOS : 3⎜ ⎟ = 1 ⎝ 1 ⎠ 1
7-27
7.49 (a) V DD
D C
B
A
vO D
C
B
A
W ⎛2⎞ 8 = 4⎜ ⎟ = L ⎝1⎠ 1 W 5 PMOS : = L 1 (b ) NMOS : W = 2(4)⎛⎜ 2 ⎞⎟ = 16 L ⎝1⎠ 1
The transitions of the two VTCs are separated by approximately 50 mV. The dynamic characteristics for switching one input with the other constant are essentially identical. The two transitions are virtually identical because of the ideal step inputs: τPHL = 3.6 ns, τPLH = 3.6 ns, tf = 8.1 ns, tr = 7.9 ns. With the inputs switched together, τPHL and tf are reduced by 50% because the two NMOS devices are working in parallel. 7.56 The simulation results show only slight changes from those of Problem 7.55. 7.57 *PROBLEM 7.54 - TWO-INPUT CMOS NAND GATE VDD 1 0 DC 2.5 VA 2 0 DC 0 PULSE (0 2.5 0 0.1N 0.1N 25N 50N) VB 4 0 DC 2.5 * MNA 3 4 0 0 MOSN W=4U L=1U AS=16P AD=16P MPA 5 4 1 1 MOSP W=5U L=1U AS=80P AD=80P
The transitions of the two VTCs are separated by approximately 50 mV. The dynamic characteristics for switching one input with the other constant are essentially identical. The two transitions are virtually identical because of the ideal step inputs: τPHL = 3.6 ns, τPLH = 3.7 ns, tf = 8.0 ns, tr = 8.1 ns. With the inputs switched together, τPLH and tr are reduced by 50% because the two PMOS devices are working in parallel 7.58 The simulation results show only slight changes. 7.59
7-33
Worst-case paths are the same as the symmetrical reference inverter: ⎛ 1 ⎞⎛ 15⎞ ⎛ 5⎞ ⎛ 1 ⎞⎛ 4 ⎞ ⎛ 2 ⎞ PMOS tree : ⎜ ⎟⎜ ⎟ = ⎜ ⎟ | NMOS tree : ⎜ ⎟⎜ ⎟ = ⎜ ⎟ | For VDD = 2.5V , ⎝ 3 ⎠⎝ 1 ⎠ ⎝ 1 ⎠ ⎝ 2 ⎠⎝ 1 ⎠ ⎝ 1 ⎠
τ PLH = 1.2 RonP C =
1.2(1.25 pF ) 1.2C = = 3.95ns K p VGS − VTP 5 4 x10−5 −2.5 + 0.6
Since there is a 2.5 :1 ratio in transistor sizes, τ PLH = τ PHL ,
τ P = τ PHL = 3.95 ns and t r = t f = 3τ PHL = 3τ P = 11.8 ns
7-34
7.60 (a) A depletion-mode design requires the same number of NMOS transistors in the switching network, but only one load transistor. The depletion-mode design requires 5 transistors total. The CMOS design requires 8 transistors. (b) For the CMOS design, first find the worst - case delay of the circuit in Fig. 7.30 and then scale the result to achieve the desired delay. For VDD = 2.5 V,
−−−−− For the depletion - mode design, first assume that τ P is dominated by τ PLH.
τ PLH ≅ 2τ P | τ PLH = 3.6RonLC
( ) ( )( ) −12
3.6 10 ⎛W ⎞ 4.50 W = = | Since NMOS is ratioed logic, the ratios ⎜ ⎟ −8 −6 1 L ⎝ L ⎠ L 2 10 40x10 () 1 ⎛W ⎞ (2.22 /1) 4.50 = 5.52 must maintain the ratio in Fig. 7.29(d) : ⎜ ⎟ = 1 ⎝ L ⎠ S (1.81/1) 1 Using this value, τ PHL =
(b) The symmetrical inverters yield τP = 3.7 ns. Note that these results are larger than the delay equation estimate because of the slope of the waveforms.
7-54
7.85 (a)
(b) V DD CLK V DD
Z = AB
CLK
A
B
Z=A+B B
A
CLK
CLK
7-55
7.86 (a)
(b) V DD
V DD
CLK
CLK
A
A
B
B
Z = A + B = AB
Z = A + B = AB
CLK
CLK
7.87 (a)
(b) VDD
CLK
A V DD CLK Z
A
B
C
B
Z = A+B+C
C
CLK
7-56
CLK
Z = ABC
7.88 (a)
(b) V DD
CLK
A VDD
Z = A B C = A+B+C CLK
Z
B
A
B
C
C Z = A + B + C = ABC
CLK
CLK
7.89 VDD
CLK
A
B
C
D
E
F
Z = (AB+CD+EF)
CLK
7-57
7.90 VDD CLK
A
B
C
D
E
Z = (ABC+DE+F)
F
CLK
7.91 Charge sharing occurs. Assuming C2 and C3 are discharged (the worst case)
(a ) V
=
(c) V
=
C1VDD + C2 (0)
2C2VDD 2 2 = VDD | Node B drops to VDD . C1 + C2 2C2 + C2 3 3 ⎛2 ⎞ 2 3C V ⎜ ⎟ 2 DD + C V + C 0 C ( 1 2 )3 DD 3 ( ) V 1 ⎝3 ⎠ = = DD | Node B drops to VDD . (b) VB = 2C2 + C2 + C2 C1 + C2 + C3 2 2 B
The relative sizes of the 4 inverters are : 1, 3.16, 10.0, 31.6
Each inverter has a delay of 3.16τ o. The total delay is 4(3.16τ o )= 12.6τ o Note, N = 5 yields β = 2.51 and the total delay is 5(2.51τ o ) = 12.6τ o .
However, the area will be significantly larger. See Prob. 7.100. 7.99
The relative sizes of the 8 inverters are: 1, 2.82, 7.95, 22.4, 63.2, 178, 503, 1420.
Each inverter has a delay of 2.82τ o. The total delay is 8(2.82τ o )= 22.6τ o . Note, N = 7 yields β = 2.60 and the total delay is 7(2.60τ o ) = 18.2τ o.
However, the area will be significantly larger. See Prob. 7.100. 7.100 AT = Ao (1+ β + β 2 + ...+ β N −1 )= Ao
β N −1 β −1
1000 −1 = 462Ao 3.1623 −1 1000 −1 For N = 7, β = 10001/7 = 2.6827 | A = Ao = 594 Ao 2.6827 −1 Since the two values of N give similar delays, N = 6 would be used For N = 6, β = 10001/6 = 3.1623 | A = Ao
because of it requires significantly less area.
7.101 ⎡⎛ 20 ⎞ ⎤−1 −6 (a) Ronn = K V − V = ⎢⎜⎝ 1 ⎟⎠ 100x10 (2.5 − 0.6)⎥ = 263 Ω ⎦ n ( GS TN ) ⎣ 1
10 −4 10 10 (2.5 −1− 0.845)+ 4x10−5 (−0.937 + 1) → Ron = 1470Ω 1 1 (b) Ron will be the largest for the VI at which the NMOS transistor just cuts off : Gon =
[
)]
(
2.5 − VI = 0.6 + 0.5 VI + 0.6 − 0.6 → VI = 1.554V Gon =
The worst cases occur approximately at the point where the PMOS or NMOS transistors just cut off.
[
(
)]
The NMOS transistor cuts off for 2.5 − VI = 0.75 + 0.5 VI + 0.6 − 0.6 → VI = 1.426V VTP = −1.01V
⎛W ⎞ ⎛W ⎞ 1 240 = ⎜ ⎟ 4x10−5 (−1.01+ 1.426)→ ⎜ ⎟ = 250 ⎝ L ⎠ P 1 ⎝ L ⎠P
(
)
[
(
)]
The PMOS transistor cuts off for VI = 0.75 + 0.5 2.5 − VI + 0.6 − 0.6 → VI = 1.074V VTN = −1.01V
⎛W ⎞ ⎛W ⎞ 1 96.2 = ⎜ ⎟ 10−4 (2.5 −1.074 −1.01)→ ⎜ ⎟ = 250 ⎝ L ⎠ N 1 ⎝ L ⎠P
( )
7.104 (a ) The output of the first NMOS transistor will be
[
)]
(
VI = 2.5 − VTN = 2.5 − 0.75 + 0.55 VI + 0.6 − 0.6 → VI = 1.399V | VTN = 1.10V The output of the other gates reaches this same value. All three nodes = 1.40 V. For the PMOS transistors, the node voltages will all be 2.5 V.
8.10 For "0" = 0V, the bias across the source-substrate junction is 0 V, so the leakage current would be 0 and the "0" state is undisturbed. For a "1" corresponding to a positive voltage, a reverse bias across the source-substrate junction, and the diode leakage current will tend to destroy the "1" state. iL C n
VGS − VTN = 5 −1.3 −1.00 = 2.7V | VDS = 3.7 −1.3 = 2.4V → linear region ⎛1⎞⎛ 2.4 ⎞ iDS = 60x10−6 ⎜ ⎟⎜5 −1.3 −1.00 − ⎟2.4 = 216 µA which agrees with the text. 2 ⎠ ⎝1⎠⎝ 8.15
(a) "0"= +0 V | V = 3 − V = 3 − 0.7 − 0.5( V + 0.6 − 0.6 )→ V = 1.90V | "1"= 1.90 V (b) A "0" will have 0 V across the drain - substrate junction, so no leakage occurs. C
TN
C
C
A "1" will have a reverse bias of 1.9 V across the junction, so the junction leakage will tend to destroy the "1" level. (Note that this discussion ignores subthreshold leakage through the FET which has not been discussed in the text.)
8.16
(a) "1"= +5 V | V = −V = 0.8 + 0.65( 5 − V (b) V = −0.8 − 0.65( 5 + 0.6 − 0.6 )= −1.83V C
→ vO = vI = 1.597 V Sense amp current = 2iDS = 402 µA P = 1024(3.3V)(402 µA)= 1.36 W
8.22 V
G
C
C
C
C
DG
BL
GS
500 fF
BL
500 fF
The precharge transistor is operating in the linear region with VDS = 0 1 CGS = Cox" WL + CGSOW 2 −14 1 3.9 8.854x10 F / cm CGS = 10−3 cm 10−4 cm + 4x10−11 F / cm 10−3 cm = 48.6 fF 2 2x10−6 cm 1 ∆VG -3 sC BL ∆V(s) = ∆VG (s) → ∆V = = = 0.266 V 500 1 C BL 1 + +1 +1 48.6 sCGS sC BL CGS
(
) (
)(
)(
)(
)
This value provides a good estimate of the drop observed in Fig. 8.25.
8-9
8.23 The precharge transistor is operating in the linear region with VDS = 0 1 CGS = Cox" WL + CGSOW 2 −14 1 3.9 8.854x10 F / cm 10−3 cm 10−4 cm + 4x10−11 F / cm 10−3 cm = 48.6 fF CGS = −6 2 2x10 cm Using CBL = 500 fF as in the previous problem, 1 ∆VG 3 sC BL ∆VG (s)→ ∆V = = = 0.266 V ∆V(s) = 500 1 1 C BL + +1 +1 48.6 CGS sCGS sC BL
(
) (
)(
)(
)(
)
This value provides a good estimate of the observed change in Fig. 8.29. The source - substrate diode will clamp the voltage to ∆V ≤ 0.7 V.
8.24 The bitline will charge to an initial voltage of VBL = 3 - VTN
(
)
VTN = 0.7 + 0.5 3 − VTN + 0.6 − 0.6 → VTN = 1.10V | VBL = 1.90V The initial charge QI on C BL : QI = 10−12 F (1.9V )= 1.9 pC After charge sharing : VBL =
1.9 pC = 1.81V. The voltage will be restored to 1.90V 1.05 pF
by the transistor. The total charge delivered through the transistor is 9.45x10−14 C ∆Q = 0.09V (1.05 pF )= 0.0945 pC | ∆vO = = 0.945 V 10−13 F 0.945 This sense amplifier provides a voltage gain of AV = = 10.5 0.09
The latch is perfectly balanced in Part (a) and the voltage levels remain symmetrical even after the PC transistor turns off. This would not happen in the real case because of small asymmetries and noise in the latch. Even a small capacitive imbalance will cause the latch to assume a preferred state. Try setting CBL2 = 425 fF in Part (a) for example. The asymmetry in the latch in Part (b) causes it to switch to a preferred state.
With only a 3 V power supply, the maximum bit-line differential is only 1.14 V which is achieved in 120 ns. (This is relatively slow due to the discharge of large bitline capacitances and the relatively large threshold voltage of the NMOS transistors.)
With the 5 V power supply, the maximum bit-line differential is 1.75 V. A 1.5 V differential is achieved in approximately 15 ns, which is much faster than the 3 V case. 8.30
2 logic inverters per level = 14 inverters = 28 transistors. Total = 282 Transistors (b) An estimate : 128 data bits requires 128 7 - input gates for data selectors; 1 - 128 input NOR gate; 14 address bit inverters
Total = 128(8)+ 1(129)+ 14(2) = 1181 transistors without looking closely at the logic detail.
A number of additional inverters may be needed, and the 128 input gate can likely be replaced with a smaller NOR tree.
8.33 A0
Clock
A1
A2 Clock
V
DD 0
V
DD 1
V
DD 2
V
DD 3
V
DD 4
V
DD 5
V
DD 6
V
DD 7
NMOS Transistor
8-18
8.34 (a) The output of the first NMOS transistor will be
[
)]
(
V1 = 5 − VTN = 5 − 0.75 + 0.55 V1 + 0.6 − 0.6 → V1 = 3.55V | VTN = 1.45V The output of the other gates reaches this same value. All three nodes = 3.55V.
(b) The node voltages will all be
+ 5 V.
8.35 Charge sharing occurs. Assuming C2 and C3 are discharged (the worst case)
(a) V
B
=
(c) V
B
=
C1VDD + C2 (0)
2C2VDD 2 2 = VDD | Node B drops to VDD . C1 + C2 2C2 + C2 3 3 ⎛2 ⎞ 2 3C V ⎜ ⎟ 2 DD + C V + C 0 C ( 1 2 )3 DD 3 ( ) V 1 ⎝3 ⎠ b V = = = DD | Node B drops to VDD . () B 2C2 + C2 + C2 C1 + C2 + C3 2 2 =
C1VDD RC2VDD R C = = VDD ≥ VIH where R = 1 C1 + C2 + C3 RC2 + C2 + C2 R + 2 C2
R(VDD − VIH ) ≥ 2VIH
or R ≥
2VIH VDD − VIH
Using VDD = 5V , VTN = 0.7V , VTP = −0.7V in Eq. (7.9) : VIH =
Regenerative switching of the cell will take place when the voltage at Q is pulled low enough by transistor MR that the voltage at Q rises above the NMOS transistor threshold voltage. Equating drain currents for this condition yields the value of VQ . It appears that the NMOS transistor will be in the linear region, and the PMOS transistor will be saturated. ⎛ ⎞⎛ 2 4 x10−5 ⎛ 4 ⎞ 0.7 ⎞ −4 2 For VDD = 5V, ⎜ ⎟(5 − VQ − 0.7) = 10 ⎜ ⎟⎜VQ − 0.7 − ⎟0.7 → VQ = 2.64V which agrees with 2 ⎝1⎠ 2 ⎠ ⎝ 1 ⎠⎝ the assumptions. Now, MR must be large enough to force VQ = 2.64V . MR and the PMOS load transistor are both in the linear region. ⎛ 4 ⎞⎛ ⎛ ⎞ ⎛ ⎛W ⎞ 1.16 2.36 ⎞ 2.64 ⎞ −4 W 4 x10−5 ⎜ ⎟⎜ 5 − 0.7 − 0.7 − ⎟2.36 ≤ 10 ⎜ ⎟ ⎜ 5 − 0.7 − ⎟2.64 → ⎜ ⎟ ≥ 2 ⎠ 2 ⎠ 1 ⎝ 1 ⎠⎝ ⎝ L ⎠R ⎝ ⎝ L ⎠R 8.42 The inputs are active in the low voltage state. V1 low sets the latch and V2 low resets the latch. V1 = S V2 = R .
The flip-flop operates normally. Data is transferred to the master following the first clock transition and to the slave after the second clock transition. The maximum rise and fall times are highly dependent upon the position of the data transition edge. It is interesting to experiment with the data delay to see the effect. At some point the flip-flop will fail.
8-24
6.0V
Data
4.0V
CLK CLK
2.0V
Master
Data
Slave
0V
Time 0s
5ns
10ns
15ns
20ns
8-25
CHAPTER 9 9.1 Since VREF = −1.25V , and v I = −1.6V , Q1 is off and Q2 is conducting. vC1 = 0 V and vC 2 = −α F I EE RC ≅ −I EE RC = −(2mA)(350Ω) = −0.700 V
9.2 ⎛ ∆V ⎞ IC 2 0.995α F I EE = exp⎜ BE ⎟ ⇒ ∆VBE = 0.025ln = 0.132V IC1 0.005α F I EE ⎝ VT ⎠
(a) v I = VREF + ∆VBE = −1.25 + 0.132 = −1.12 V v I = VREF + ∆VBE = −1.25 − 0.132 = −1.38 V (b) v I = VREF + ∆VBE = −2.00 + 0.132 = −1.87 V v I = VREF + ∆VBE = −2.00 − 0.132 = −2.13 V 9.3 Since VREF = −2V , and v I = −1.6V , Q2 is off and Q1 is conducting.
vC 2 = 0 V and vC1 = −α F I EE RC ≅ −I EE RC = −(2.5mA)(700Ω)= −1.75 V Note that Q1 is beginning to enter the saturation region of operation, but VBC = +0.15 V is not really enough to turn on the collector-base diode. (See Problems 9.5 or 5.61.)
9.4 vI = VREF + 0.3V ⇒ Q1 on; Q2 off. IC1 = α F I EE ≅ I EE = 0.3mA | IC 2 = 0 vC1 = 0 − IC1 (R1 + RC )= −0.3mA(3.33kΩ + 2 kΩ) = −1.60 V vC 2 = 0 − IC1 R1 = −0.3mA(3.33kΩ) = −0.999 V
9-1
9.5 With VBE = 0.7 and VBC = 0.3, the transistor is technically in the saturation region, but calculating the currents using the transport model in Eq. (5.13) yields
βF =
0.98 0.2 αF αR = = 49 | β R = = = 0.25 1− α F 1− 0.98 1− α R 1− 0.2
⎡ ⎛ 0.7 ⎞ ⎛ 0.3 ⎞⎤ 10−15 ⎡ ⎛ 0.3 ⎞ ⎤ iC = 10−15 ⎢exp⎜ ⎟ − exp⎜ ⎟⎥ − ⎟ −1⎥ = 1.446 mA ⎢exp⎜ ⎝ 0.025 ⎠⎦ 0.25 ⎣ ⎝ 0.025 ⎠ ⎦ ⎣ ⎝ 0.025 ⎠ ⎡ ⎛ 0.7 ⎞ ⎛ 0.3 ⎞⎤ 10−15 ⎡ ⎛ 0.7 ⎞ ⎤ iE = 10−15 ⎢exp⎜ − exp ⎟ ⎟⎥ + ⎟ −1⎥ = 1.476 mA ⎜ ⎢exp⎜ ⎝ 0.025 ⎠⎦ 49 ⎣ ⎝ 0.025 ⎠ ⎦ ⎣ ⎝ 0.025 ⎠ 10−15 ⎡ ⎛ 0.7 ⎞ ⎤ 10−15 ⎡ ⎛ 0.3 ⎞ ⎤ iB = ⎟ −1⎥ + ⎟ −1⎥ = 29.52 µA ⎢exp⎜ ⎢exp⎜ 49 ⎣ ⎝ 0.025 ⎠ ⎦ 0.25 ⎣ ⎝ 0.025 ⎠ ⎦ At 0.3 V, the collector-base junction is not heavily forward-biased compared to the baseemitter junction, and IC = 48.99IB ≅ β F IB . The transistor still acts as if it is operating in the forward-active region. 9.6 (a) For Q2 off, VH = 0 V. For Q2 on, IC ≈ IE and
−0.2 − 0.7 − (−2)
= 100 µA VL ≅ −4000I E = −0.400 V 1.1x10 4 (b) Yes, these voltages are symmetrically positioned above and below VREF, i. e. VREF ± 0.2 V, and the current will be fully switched. See Parts (d) and (e). 0 − 0.7 − (−2) 0.4V = 118 µA R = = 3.39 kΩ (c) For v I = 0, IC ≅ I E = 4 118µA 1.1x10 IE =
(d) Q2 is cutoff. Q1 is saturated with VBC = +0.4 V. (e) Q1 is cutoff. Q2 is saturated with VBC = +0.2 V. (f) 0.2 V and 0.4 V are not large enough to heavily saturate Q1 or Q2. Although the transistors are technically operating in the saturation region, the transistors still behave as if they are in the forward-active region. (See problem 10.5).
9-2
9.7
(a) For v
−0.2 − 0.7 − (−2)
= 100 µA | VL ≅ −4000I E = −0.400 V 1.1x10 4 0 − 0.7 − (−2) 0.4V = 118 µA | R = = 3.39 kΩ For vI = VH = 0V , IC ≅ I E = 4 118µA 1.1x10 ⎛100µA + 118µA ⎞ P = 2V ⎜ ⎟ = 218 µW 2 ⎝ ⎠ R 11kΩ R 4kΩ R 3.39kΩ (b) REE' = 5EE = 5 = 2.20 kΩ | RC1' = 5C1 = 5 = 800 Ω | RC' 2 = 5C2 = 5 = 678 Ω I
= VL , I E =
9.8 VH = 0 − VBE = −0.7 V | VL = −(5mA)(200Ω)− 0.7 = −1.70 V
VREF =
VH + VL = −1.2 V | ∆V = (5mA)(200Ω)= 1.00 V 2
9.9 VH = 0 − VBE = −0.7 V | VL = −(1mA)(600Ω)− 0.7 = −1.30 V
VREF =
VH + VL = −1.0 V | ∆V = (1mA)(600Ω) = 0.600 V 2
9.10
I EE = 4(0.3mA) = 1.2 mA | I3 = I 4 = 4(0.1mA)= 0.4 mA | RC =
2kΩ = 500Ω 4
9.11
(a) R
C
=
∆V 0.8V = = 2.67 kΩ | VH = 0 − VBE = −0.7 V | VL = −0.8 − VBE = −1.5 V I EE 0.3mA
VH + VL = −1.10 V 2 ⎡ ⎡ ⎛ ∆V ⎞⎤ 0.8 ⎞⎤ ⎛ 0.8 ∆V (b) NM H = NM L = 2 − VT ⎢1+ ln⎜⎝ V −1⎟⎠⎥ = 2 − 0.025V ⎢⎣1+ ln⎜⎝ 0.025 −1⎟⎠⎥⎦ = 0.289 V ⎦ ⎣ T (c) For Q1: VCB = -0.8 - (-0.7) = -0.1 V which represents a slight forward bias, but it is not enough to turn on the diode. For Q2: VCB = -0.8 - (-1.10) = +0.3 V which represents a reverse bias. Both values are satisfactory for operation of the logic gate. VREF =
9-3
9.12 (b) For Q1 on and Q2 off, IC1 = α F I EE ≅ I EE = 0.3mA | IC2 = 0
VH + VL = −2.0V = VREF | Yes, the input and output voltage levels are 2 compatible with each other and are symmetrically placed around VREF.
(c)
R1
RC
RC
Q
v
Q
3
4 v O2
O1
vI
Q 1
Q
2
V REF 0.1 mA
0.1 mA IEE - 5.2 V
9.13 (a) See Prob. 9.12
(b) ∆V = α
0.4V = 267 Ω 1.5mA ≅ −I EE R1 − VBE = −1.5mA(800)− 0.7V = −1.90 V
I RC ≅ I EE RC | RC =
F EE
VH = 0 − α F I EE R1 − VBE
VL = 0 − α F I EE (R1 + RC )− VBE ≅ −I EE (R1 + RC )− VBE = −1.5mA(1067)− 0.7V = −2.30 V VREF =
9-4
VH + VL −1.90 − 2.30 = = −2.10 V 2 2
9.14 ∆V = ∆VBE + ∆iB 4 RC | Let the Fanout = N; β F = 30. Then there will be N base currents that must be supplied from emitter - follower transistor Q4 : ∆i E4 = N ∆VBE = VT ln ∆iB 4 =
I EE βF + 1
⎡ ⎤ ⎛ ∆I ⎞ I EE IC 4 + ∆IC 4 I + ∆I E 4 ⎥ = VT ln E 4 = VT ln⎜1+ E 4 ⎟ = 0.025ln⎢1+ N IC 4 IE 4 IE 4 ⎠ ⎝ ⎢⎣ (β F + 1)I E 4 ⎥⎦
The collector - base junction of Q2 is reverse - biased by 0.3 V. Although the collector - base junction of Q1 is forward - biased by 0.1 V, this is not large enough to cause a problem. Therefore the voltages are acceptable.
9.21 NM H =
⎡ ⎛ ∆V ⎞⎤ ∆V − VT ⎢1+ ln⎜ −1⎟⎥ 2 ⎝ VT ⎠⎦ ⎣
For room temperature, VT = 0.025V : 0.1V = For - 55C, VT = 0.0188V : 0.1V =
9.22 In the original circuit : VH = −2mA(2kΩ)− 0.7V = −1.1V | ∆V = 2mA(2kΩ)= 0.4V VL = −1.1V − ∆V = −1.5V. VH and VL are symmetrically placed about VREF .
−1.3 − 0.7 − (−5.2) V = 16.0 kΩ. R1 and R C2 remain unchanged. mA 0.2 −1.1− 0.7 − (−5.2) V For Q1 on and and Q2 off : I EE = = 0.2125mA kΩ 16.0 VL1 = −(0.2125mA)(2kΩ + RC1)− 0.7V | VL1 = −1.5V → RC1 = 1.77 kΩ. REE =
Note that there are only 3 variables (R1 , RC1 and R C2 ) and four voltage levels. Thus we cannot force them all to the desired level. For this design,
VH 2 = −(0.2125mA)(2kΩ)− 0.7V = −1.125V rather than the desired -1.10V
9.23
60kΩ (−5.2V )= −3.0V | REQ = 60kΩ 44kΩ = 25.38kΩ 60kΩ + 44kΩ −3.0 − 0.7 − (−5.2) V −3.0 − 0.7 − (−5.2) V = | I EE = β F I BS = β F 25.38 + (β F + 1)30 kΩ 25.38 + (β F + 1)30 kΩ
-55C 0.0188 V -0.846 V -1.40 V 0.554 V -1.00 V -0.918 V -0.865 V -1.08 V -1.38 V 0.053 V 0.300 V
+25C 0.0257 V -0.724 V -1.30 V 0.576 V -1.00 V -0.895 V -0.750 V -1.10 V -1.27 V 0.145 V 0.170 V
+85C 0.0309 V -0.629 V -1.22 V 0.591 V -1.00 V -0.880 V -0.660 V -1.12 V -1.19 V 0.220 V 0.070 V
VIH , VOH , VOL , and VIL were calculated from Eqns. 9.27 - 9.30. With a fixed reference voltage, the noise margins change with temperature and can become zero for a large enough temperature change.
9-9
9.26 RC
Q 4
Q A
B
C
D
V
2
E
REF
Y =A+B+C+D+E I EE R
-V
EE
9.27 R Q
C
3
Q B
A
C
D
2
V
REF
Y=A+B+C+D I EE R -V
9.28
(a ) For Q
4
on, IC 4 = α F I E 4 ≅ I E 4 =
EE
−0.7 − (−2.5)
840 VL = 1.0V − (2.14mA)(390Ω)− 0.7V = −0.540 V
= 2.14 mA
For Q4 off, and neglecting the base current in Q5 , VH = 1.0 − 0.7 = +0.300 V
(b) For v
= 0.3V, IC 2 = α F I E 2 ≅ I E 2 =
0.3 − 0.7 − (−2.5)
= 2.50 mA 840 ∆V 0.84V ∆V = 0.30 − (−0.54)= 0.84V | R = = = 336 Ω IC 2 2.50mA
9-10
A
9.29
(a) For Q
4
on, IC 4 = α F I E 4 ≅ I E 4 =
−0.7 − (−3.2)
840 VL = 1.3V − (2.98mA)(390Ω)− 0.7V = −0.56 V
= 2.98 mA
For Q4 off, and neglecting the base current in Q5 , VH ≅ 1.3 − 0.7 = +0.60 V
(b) For v
= 0.6V , IC 2 = α F I E 2 ≅ I E 2 =
0.6 − 0.7 − (−3.2)
= 3.69 mA 840 ∆V 1.16V ∆V = 0.60 − (−0.56)= 1.16V | R = = = 314 Ω IC 2 3.69mA A
9.30 V CC 390 Ω
A
B Q
2
Q
3
Q
Q
4
5
Y=A+B
840 Ω
600 Ω
-V EE
(a)
(b) The NOR output is taken from the collectors of Q2/Q3, and the 390Ω resistor, Q5, and the 600-Ω resistor are removed. 9.31
vOmin = − I EE RL = −(2.5mA)(1.2kΩ) = −3.00 V | I E = I EE +
vO 4 − 0.7 = 2.5mA + = 5.25 mA 1.2kΩ RL
VBC = 4 − 5 = −1 V , so the transistor is in the forward - active region. IB =
IE 5.25mA = = 0.103 mA and IC = β F I B = 5.15 mA. β F + 1 50 + 1
9.32
(a-b) See Problem 9.33 (c) IEE ≥ −
(VI − 0.7)V 1kΩ
=
3.7V = 3.7 mA 1kΩ
9-11
9.33 Simulation Results from B2SPICE Circuit 9.32-Transient-2 Circuit 9.32-Transient-1 +0.000e+000
(V)
+500.000u
+1.000m
Time (s) +1.500m
+0.000e+000
(V)
+500.000u
+1.000m
Time (s) +1.500m
+2.000m
+2.000m
+3.000 +3.000
+2.000 +2.000
+1.000
+1.000
+0.000e+000
+0.000e+000
-1.000
-1.000 -2.000
-2.000 -3.000
-3.000 -4.000
IEE = 4 mA
V(1)
IEE = 2 mA
V(3)
V(1)
V(3)
9.34 (a) vO = v I − 0.7V = (−1.7 + sin2000πt ) V
2.7V = 0.13 mA with no safety margin. 20kΩ The transistor will cut off at the bottom of the input waveform for IEE = 0.13 mA.
(b) vOmin = −2.7V
| - IEE RL ≤ −2.7V → IEE ≥
9.35 Simulation results from B2SPICE Circuit 9.35-Transient-1 (V)
+0.000e+000
+500.000u
+1.000m
Time (s) +1.500m
+2.000m
+0.000e+000
-500.000m
-1.000
-1.500
-2.000
-2.500
-3.000 V(1)
V(3)
9.36 (a ) The transistor cuts off for vOmin = -I EE RL = -(0.5mA)(1kΩ) = -0.5V. So vI ≥ -0.5 + 0.7 = +0.2V.
For v O > 1.5 V, the transistor enters the saturation region of operation. Therefore : 0.2 V ≤ v I ≤ 1.5 V.
(b) v
min O
= −1.5 − 0.7 = −2.2 V. We need - I EE RL ≤ −2.2V → I EE ≥
2.2V = 2.2 mA 1kΩ
9.37 vOmin = −10 − 0.7 = −10.7 V . We need - IEE RL ≤ −10.7V → IEE ≥
9-12
10.7V = 10.7 mA 1kΩ
9.38 Assuming Q1 off and using voltage division, −12 = −15 12 − (−15) 12 + = 60 mA ! 2000 500
IE =
9.39
(a) v
min O
(b) I
⎛ 4.7kΩ ⎞ = −10 − 0.7 = −10.7 V. We need -15V ⎜ ⎟ ≤ −10.7V ⎝ 4.7kΩ + RE ⎠
(15 −10.7)(4.7kΩ) = 1.89 kΩ
RE ≤
10.7
| IE =
−0.7 −0.7 − (−15) + = 7.43 mA | 4700 1890
=
E
2000 ⇒ RE = 500 Ω 2000 + RE
vI − 0.7 vI − 0.7 − VEE + RE RL
(c) I
E
=
−10 − 0.7 −10 − 0.7 − (−15) + = 0 mA 4700 1890
9.40 (a) See the solution to Problem 9.41.
(b) v (c) v
O
= v I − 0.7V = (−2.2 + 1.5sin 2000πt ) V
max I
IE =
= −1.5 + 1.5 = 0V | vOmax = −0.7V |
vO vO − VEE + RL RE
| I Emax =
−0.7 −0.7 − (−6) + = 3.93 mA 1300 4700
−3.7 −3.7 − (−6) + = 0.982 mA 1300 4700 ⎛ 4.7kΩ ⎞ 4.7kΩ(6 − 3.7) = 2920 Ω (e) We need - 6V ⎜⎝ 4.7kΩ + R ⎟⎠ ≤ −3.7V → RE ≤ 3.7 E
(d ) v
min O
= −2.2 −1.5 = −3.7V | I Emin =
9.41 Simulation results from B2SPICE Circuit 9.37-Transient-2 +0.000e+000
+500.000u
+1.000m
+1.500m
Time (s) +2.000m
+2.500m
+3.000m
+0.000e+000
-1.000
-2.000
-3.000
-4.000 V(1)
V(3)
V(5)
9-13
9.42 The outputs act as a "wired - or" connection. For v I = −0.7V, vO1 = vO 2 = −0.7 V | IE 3 = 0 | IE 4 = 0.1mA + 0.1mA = 0.200 mA For v I = −1.3V, vO1 = vO 2 = −0.7 V | IE 3 = 0.1mA + 0.1mA = 0.200 mA | IE 4 = 0 9.43
Y = A+ B | Z = A+ B 9.44 A
Y OR
B
C NOR D
9.45 For Fig. 9.21, P ≅ 0.5mA(5.2V)= 2.6mW = 2600µW. For 20µW, the power must
be reduced by 130X. The currents must be reduced by 130X and the resistors must increase by this factor to keep the logic swing the same : R C = 130(2kΩ)= 260kΩ. Using Eq. (9.54), τ P = 0.69(260kΩ)(2 pF ) = 359 ns - rather slow!
9.52 Voltage levels remain unchanged : VREF = −1 V , VH = −0.7 V , VL = −1.3 V , I EE = 0.3 mA −1− 0.7 − (−2) V 0.6V 0.6V = 1 kΩ | RC1 = = = 1 kΩ mA 0.6mA 0.3 −0.7 − 0.7 − (−2) A 1 kΩ −1− (−2) V 0.3 + 0.6 I ≅2 + mA = 0.650mA | P = 0.65mA(2V )= 1.30 mW (-28%) kΩ 2 10 Note that this gate will now have quite asymmetrical delays at the two outputs since the two collector resistors differ by a factor of two in value. REE =
9.53 The circuit is the pnp version of the ECL gate in Fig. P9.48. | Y = ABC 9.54
0.7 + 1.3 1mW = +1.0V | I = = 333µA 3V 2 (1 + 0.7)+ (0.7 + 0.7) = 1.55V The average voltage at the emitter of QD is 2 (3 −1.55)V = 4.84 kΩ | R = (3 −1)V = 60.1 kΩ | R = 0.6V = 2.23 kΩ RE = B C 0.9(333µA) 0.1(333µA) (3 −1.7)V
VL = 0 | VH = VL + ∆V = +0.6V | VREF =
4.84kΩ 9.55 *Problem 9.55(a) - PNP ECL GATE DELAY VI 4 0 PULSE(0.6 0 0 .01NS .01NS 25NS) VB 7 0 DC 0.6 VREF 6 0 DC 1.0 VEE 1 0 DC 3 QA 0 4 3 PBJT QB 0 7 3 PBJT QC 0 7 3 PBJT QD 0 3 2 PBJT QE 5 6 2 PBJT RB 1 3 60.1K RE 1 2 4.84K
Although the transistor is technically in the forward-active region, (and operating with IC = βF IB), it is esentially off - its terminal currents are zero for most practical purposes. 9.57
⎛ 1 ⎞ For IC = 0, VCESAT = VT ln⎜ ⎟ ⎝αR ⎠
VCESAT
1+
IC (β R + 1)I B
⎛ 1 ⎞ = VT ln⎜ ⎟ ⎝αR ⎠
IC βF I B ⎛ β + 1⎞ ⎛ 1.25 ⎞ = VT ln⎜ R ⎟ = 0.025ln⎜ ⎟ = 0.402 V ⎝ 0.25 ⎠ ⎝ βR ⎠ 1−
9-19
9.58 (a) For the Transport model with VBE = VBC, the transport current iT = 0: β 40 I ⎡ ⎛V ⎞ ⎤ I ⎡ ⎛V ⎞ ⎤ I IC = S ⎢exp⎜ BC ⎟ − 1⎥ and IE = S ⎢exp⎜ BE ⎟ − 1⎥ ⇒ C = F = = 160 β R ⎣ ⎝ VT ⎠ ⎦ β F ⎣ ⎝ VT ⎠ ⎦ IE β R 0.25
(b)
v BE = VB − 0.6 | v BC = VB − 0.8 = v BE − 0.2
⎤ ⎡ v v ⎤ I ⎡ v iE = IS ⎢exp BE − exp BC ⎥ + S ⎢exp BE −1⎥ VT VT ⎦ β F ⎣ VT ⎦ ⎣ ⎡ v v −0.2 ⎤ IS ⎡ v BE ⎤ −1⎥ iE = IS ⎢exp BE − exp BE exp ⎢exp ⎥+ VT VT VT VT ⎦ β F ⎣ ⎦ ⎣ ⎛ ⎡ v ⎤ I ⎡ v ⎤ 1 ⎞⎡ v ⎤ v ⎤ I ⎡ iE ≅ IS ⎢exp BE ⎥ + S ⎢exp BE ⎥ = IS ⎜1+ ⎟⎢exp BE ⎥ = S ⎢exp BE ⎥ VT ⎦ β F ⎣ VT ⎦ VT ⎦ α F ⎣ VT ⎦ ⎣ ⎝ β F ⎠⎣ −−−−− ⎡ v v −0.2 ⎤ IS ⎡ v BE − 0.2 ⎤ iC = IS ⎢exp BE − exp BE exp −1⎥ ⎥ − ⎢exp VT ⎦ β R ⎣ VT VT VT ⎦ ⎣ ⎡ v ⎤ 40 i iC ≅ IS ⎢exp BE ⎥ | C = α F = = 0.976 41 VT ⎦ iE ⎣ i (c ) C = −1 → iB = iE − iC = 2iE | Both junctions will be forward - biased. Neglect iE ⎛ v I v v v ⎞ v I I the -1 terms : S exp BE + S exp BC = 2IS ⎜ exp BE − exp BC ⎟ + 2 S exp BE βF VT β R VT VT VT ⎠ βF VT ⎝ v BE − v BC
9.68 ⎛ 1 ⎞ Using Eqs. 9.44 and 9.47 : VCC − iC RC = VT ln⎜ ⎟ ⎝αR ⎠ 1+
iC 1.25(1.09mA)
⎛1⎞ 5 − 2000iC = 0.025ln⎜ ⎟ ⎝ .2 ⎠ 1−
iC 40(1.09mA)
1+
iC (β R + 1)iB
1−
iC β F iB
→ iC = 2.4659 mA
vCESAT = 5 − 2000iC = 0.0682V
9.69 V H = 2.5 V | VL = VCESAT = 0.15 V VIL = 0.7 − VCESAT = 0.55V | VOL ≅ VL = 0.15V VIH ≅ VBESAT 2 = 0.8 V | VOH ≅ V H = 2.5 V NM L = 0.55 − 0.15 = 0.40 V NM H = 2.5 − 0.8 = 1.7 V 9.70
For vI = VH , we require VCC = VBE2SAT + VBC1 + I B1 RB = 0.8 + 0.7 + ∆V = 1.5V + ∆V where ∆V is the voltage across the base resistor. ∆V must be large enough to absorb VBE process variations and to establish the base current. 0.5 V should be sufficient. Thus VCC = 2.0 V or more is acceptable. 9.71 The VTC transitions are set by the values of vBE and vBESAT and are not changed by the power supply voltage. (b) VIL = 0.66 V and VIH = 0.80 V. But VOH ≅ VH = 3 V and VOL ≅ VL = 0.15 V. (c) NMH = 3 - 0.8 = 2.2 V | NML = 0.66-0.15 = 0.51 V. 9.72 We need to reduce the currents by a factor of 11.2. Thus, RB = 11.2 (4kΩ) = 44.8 kΩ and RC = 11.2 (2kΩ) = 22.4 kΩ 9.73 (a) *Problem 9.73 - Prototype TTL Inverter +Delay VI 1 0 DC 0 PWL(0 0 0.2N 5 25N 5 25.2N 0 +50N 0) VCC 5 0 DC 5 Q1 3 2 1 NBJT Q2 4 3 0 NBJT RB 5 2 4K RC 5 4 2K *RB 5 2 45.2K
9.74 (a) VH = 5V | VL = VCE2SAT = 0.15V 5 − 0.15 − 0.6 = −1.06 mA 4000 = −I S ≅ 0 where IS is the diode saturation current.
vI = VL = 0.15V , I IN = − vI = VH = 5V , I IN
5 − 0.8 − 0.6
(b) I = 4000 = 0.90mA; 2000 + N (1.06mA)≤ 40(0.9mA); N ≤ 31. (c) -1.06 mA compared to -1.01 mA and 0 mA compared to 0.22 mA. 5 - 0.15
B
9.75 If we assume that the diode on-voltage is 0.7 V to match the base-emitter voltage of the BJT, then the VTC will be the same as that in Fig. 9.35. Both VTCs will be the same.
The fall time of the output of the TTL gate is somewhat slower than the DTL gate since transistor Q1 must come out of saturation. However, the rise time of the DTL gate is extremely slow because there is no reverse base current to remove the charge from the transistor base. 9.78 *Figure 9.78 - DTL Inverter Delays VI 1 0 DC 0 PWL(0 0 0.2N 5 25N 5 25.2N 0 50N 0) VCC 5 0 DC 5 *DTLA D1A 6 1 D1 D2A 6 7 D1 RBA 5 6 4K RCA 5 8 2K Q2A 8 7 0 NBJT *DTL-B D1B 2 1 D1 D2B 2 3 D1 Q2B 4 3 0 NBJT RBB 5 2 4K RCB 5 4 2K RB1 3 0 1K .OP .TRAN 0.1N 100N .MODEL NBJT NPN BF=40 BR=0.25 IS=5E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .MODEL D1 D IS=5E-16 TT=0.15NS CJO=1PF .PROBE V(1) V(2) V(3) V(4) V(6) V(7) V(8) .END
Without the 1-kΩ resistor, the rise time of the DTL gate is extremely slow because there is no reverse base current to remove the charge from the transistor base. The resistor provides an initial reverse base current of -0.7 mA to turn off the transistor and significantly reduces the rise time and propagation delay. 9.79 See problem 9.80. 9.80 *Figure 9.79 - Inverter VTC VI 1 0 DC 0 VCC 6 0 DC 3.3 Q1 3 2 1 NBJT Q2 5 3 4 NBJT Q3 5 4 0 NBJT R1 6 2 4K R2 6 5 2K R3 4 0 3K .OP .DC VI 0 3.3 0.01 .MODEL NBJT NPN BF=40 BR=0.25 IS=1E-16 TF =0.15NS TR=15NS +CJC=0.5PF CJE=.25PF CJS=1.0PF RB=100 RC=5 RE=1 .PROBE V(1) V(2) V(3) V(4) V(5) .END
Circuit 9.108-DC Transfer-1 VO (V)
+0.00e+000
+500.00m
+1.00
+1.50
VI +2.00
+2.50
+3.00
+3.50
+3.00
+2.50
+2.00
+1.50
+1.00
+500.00m
+0.00e+000
V(2)
V(7)
The first break point occurs when the input reaches a voltage large enough to just start turning on Q2, at approximately VCESAT1 + VBE2 = 0.04V + 0.6 V = 0.64V. The second breakpoint begins when the input reaches VCESAT1 + VBE2 +VBE3 = 0.04V + 0.7 + 0.6 V = 1.34V. Note 9-28
that the shallow slope is set by the ratio of R2/R3 = 2/3, and also note that Q3 cannot saturate. From the B2SPICE simulation, VH = 3.3 V, VL ≅ VBE3 + VCESAT2 = 0.82V, VIH = 1.38 V, VOL = 0.84 V, VIL = 1.38 V, VOH = 2.82 V. NMH = 2.82 – 1.38 = 1.54 V. NML = 1.38 - 0.84 = 0.54 V. 9.81 VCC = 5 V
0.875 mA
2k Ω
4kΩ iR
N(0.875 mA)
vH < 5 V
N
iC = 0 VL 0.15 V
0.875 mA
Q2
Q1
+
"Off"
0.19 V -
From the analysis in the text, we see that the fanout is limited by the VH condition. 5 − 0.7 − 0.8 V iB1 = = 0.875mA | iE1 = −β R iB1 = −0.875mA 4 kΩ 5 − 2000(N )(0.875x10−3 )≥ 1.5 → N ≤ 2 → Fanout = 2 9.82 V CC = 5 V
1.2(4 k Ω)
1.2(2k Ω)
1.2(2k Ω) 1.5 V iB1 + 0.7 V VH
iIH = β RiB1
Q1
N
+
(βR + 1)i B1 Q2
0.15 V
+ 0.8 V
-
9-29
From the analysis in the text, we see that the fanout is limited by the VH condition. 5 − 0.7 − 0.8 V iB1 = = 0.729mA | iE1 = −β R iB1 = −0.25(0.729mA) = 0.182mA 4 (1.2) kΩ 5 − 2000(1.2)(N )(0.182x10−3 )≥ 1.5 → N ≤ 8.01 → Fanout = 8 iB1 =
5 − 2000(0.8)(N )(0.273x10−3 )≥ 1.5 → N ≤ 8.01 → Fanout = 8 The result is independent of the tolerance if the resistors track each other. Note that Eq. 9.83 also yields N = 8 if more digits are used in the calculation. 9.83 From the analysis in the text, we see that the fanout is limited by the VH condition.
iB1 =
5 − 0.7 − 0.8 RB
iE1 = −β R iB1 = −0.25iB1
5 − 0.7 − 0.8 5 − 2000(N )(0.25) ≥ 1.5 → RB ≥ 5 kΩ RB 9.84 (a) Q4 is in the forward - active region with I E = (β F + 1)I B
5 − 0.7 − 0.6 = 234 mA 1600 5 − 0.8 − 0.6 5 − 0.6 − 0.15 (b) Q4 saturates; I E = I B + IC = 1600 + 130 = 34.9 mA I E = 101
9.85 (a) PD = 5V (234mA) = 1.17 W (b) PD = 5V (34.9mA) = 0.175 W
28.3(0.1625 mA) ≥ N (0.247 mA) + 1.875mA → N = 11 9.96 (a) Y = ABC
(c ) v I
(b) VL = VCESAT 3 = 0.15 V
| V H = 3.3 − VBE1 − VD = 3.3 −1.4 = 1.9 V
= 1.9V, input diode is off and iIH = 0. v I = 0.15V, iIL = −
3.3 − 0.7 − 0.15 = −408 µA 6000
2.0V
vO
1.5V
1.0V
0.5V
vI 0V 0V
1.0V
2.0V
3.0V
4.0V
The VTC starts to decrease immediately because Q2 is ready to conduct due to the 0.7-V drop across the input diode. When the input has increased to approximately 0.7 V, Q3 begins to conduct and the output drops rapidly. The VTC is much sloppier than that of the corresponding TTL gate. For this particular circuit VIL = 0 and VIH = 0.8 V. Based upon our definitions, NML = 0. However, the initial slope can be reduced by changing the ratio RC/R2 so that VIL = 0.7 V.
9-37
9.97 (a) If either input A is low or input B is low, VB2 will be low. Q2 will be off, Q3 will be on and Y will be low. Therefore Y = A + B → Y = AB . +5 V
(a) VH = VCC = 1.5 V | VL = "VCESAT1" = 0.7 − 0.45 = 0.25 V (b) For v I = 1.5V , the input diode is off, and IIH = 0. 1.5 − 0.45 − 0.25 = 1.00 mA 800 (c ) Note that Q1 operates as if it were in the forward - active region : For v I = 0.25V , IIL =
β F IB1 ≥ NIIL + IR
2
9.99 vBE + vD2 − vD1 = vCE
⎛ 1.5 − 0.45 − 0.70 ⎞ 1.5 − 0.25 | 40⎜ → N = 16 ⎟ ≥ N (0.001) + ⎝ ⎠ 800 1000 | For vD2 ≅ vD1 , vCE = v BE = 0.7 V
iC = iCC + iD1 | iB = iBB − iD1 | iC = β F iB iCC + iD1 = β F (iBB − iD1) → iD1 =
β F iBB − iCC 20(0.25)−1 = mA = 0.191 mA 21 βF + 1
iD2 = iBB − iD1 = 0.25 − 0.191 = 0.059 mA | iC = 20iB = 20iD2 = 1.18 mA
9.100 In this circuit as drawn, the collector - base junction of Q1 is bypassed by a Schottky diode. Q1 will be "off" with VBC = +0.45 V . 5 − 0.45 − 0.7 iB1 = = 963 µA | IIN = 0 | iB 2 = iB1 = 963 µA 4000 9.101 4.0V
Y = A + B + C | V H = 0 V | VL = VREF − 0.4 0 + (VREF − 0.4 ) V H + VL = VREF | = VREF → VREF = −0.40 V | VL = −0.80V 2 2
9-41
9.104 The circuit can be modeled by a normal BJT with a Schottky diode in parallel with the collector base junction. If iC and iB are defined to be the collector- and base-currents of the BJT, iC + iB =
5 − 0.7 1.075mA = 1.075mA | iC ≅ β F iB → iB = = 26.9 µA | iC = 1.05 mA 4000 40
+5 V i=0 4 kΩ
iC
iB
Q1
9.105 If we assume 50% of the gates are switching (an over estimate), 50W = 2µW /gate | τ P = 1ns | PDP = (2µW )(1ns) = 2 fJ (a) P = 0.5(50x10 6 )
(b) PDP = (0.1mW )(0.1ns) = 10 fJ
| The result in Part (a) is off the graph!
9.106 If we assume 50% of the gates are switching (an over estimate), 100W = 1µW /gate | τ P = 0.25ns | PDP = (1µW )(0.25ns) = 0.25 fJ (a) P = 0.5(200x10 6 )
CHAPTER 10 10.1 A/C temperature Automobile coolant temperature gasoline level oil pressure sound intensity inside temperature Battery charge level Battery voltage Fluid level Computer display hue contrast brightness Electrical variables voltage amplitude voltage phase
current amplitude current phase power power factor spectrum Fan speed Humidity Lawn mower speed Light intensity Oven temperature Refrigerator temperature Sewing machine speed Stereo volume Stove temperature Time TV picture brightness TV sound level Wind velocity
10.2 (a) 20 log (120) = 41.6 dB | 20 log (60) = 35.6 dB | 20 log (50000) = 94.0 dB
20 log(100000) = 100 dB | 20 log(0.90) = −0.915 dB (b) 20 log (600) = 55.6 dB | 20 log (3000) = 69.5 dB | 20 log (106 ) = 120 dB 20 log(200000) = 106 dB | 20 log(0.95) = −0.446 dB (c) 10 log (2x109 ) = 93.0 dB | 10 log (4x105 ) = 56.0 dB 10 log (6x108 ) = 87.8 dB | 10 log(1010 ) = 100 dB 10.3 (a) 4 vO
2
0 vS
-2
x10 -3
-4 0
0.5
1
1.5
2
2.5
3
3.5
4
10-1
(b) 500 Hz : (c) 500 Hz : (d) 500 Hz : (e) Yes
1∠0 o | 1500 Hz : 0.333∠0 o | 2500 Hz : 0.200∠0 o 2∠30 o | 1500 Hz : 1∠30 o | 2500 Hz : 1∠30 o 2∠30 o | 1500 Hz : 3∠30 o | 2500 Hz : 5∠30 o
10.4 Vs = 0.0025V | PO = 40W | Vo = 2PO RL = 2(40)(8) = 25.3V
25.3 = 10100 | 20 log (10100)= 80.1 dB .0025 0.0025V V 25.3V = 45.45nA | I o = o = = 3.162 A Is = 5kΩ + 50kΩ 8Ω 8Ω 3.162 A = 6.96 x 10 7 | 20 log 3.48 x 10 7 = 157 dB Ai = 45.45nA 40W = 7.04 x 1011 | 10 log 7.04 x 1011 = 118 dB Ap = .0025V (45.45nA) Av =
(
)
(
)
2 10.5 Vs = 0.01V | PO = 20mW | Vo = 2PO RL = 2(.02)(8) = 0.566V 0.566 = 56.6 | 20 log (56.6) = 35.0 dB .01 0.01V V 0.566V Is = = 192nA | Io = o = = 70.8mA 8Ω 2kΩ + 50kΩ 8Ω 70.8mA Ai = = 3.68 x 10 5 | 20 log (3.68 x 10 5 )= 111 dB 192nA 0.02W Ap = = 2.08 x 10 7 | 10 log (2.08 x 10 7 )= 73.2 dB .01V (192nA) 2 Av =
10.6
(a) v Rth
v th
+ -
vo =
(b) v vo =
th
= voc = 0.768 2 = 1.09 V
⎛ 0.768 − 0.721⎞ v −v RL v th → Rth = RL th o = 430⎜ ⎟ = 28.0 Ω 0.721 Rth + RL vo ⎝ ⎠ th
= voc = 0.760 2 = 1.08 V
⎛ 0.760 − 0.740 ⎞ v −v RL v th → Rth = RL th o = 1040⎜ ⎟ = 28.1 Ω 0.740 Rth + RL vo ⎝ ⎠
(c) 1.09 V and 1.08 V → 9% error and 8% error 10-2
G4 laptop – 1 V, 28 Ω.
10.7
10.8 (a) Vo = 2RL PO = 2(8)(20) = 17.9V Pi =
Vi2 12 1V 17.9V = = 25.0µW | I i = = 49.9µA | I o = = 2.24 A 2Ri 40066 20000Ω + 32Ω 8Ω
Av =
Vo 17.9V 20W 2.24 A = = 17.9 | AP = = 8.00x105 | Ai = = 4.49x10 4 Vi 1V 25µW 49.9µA
(b) V = 17.9 V ; recommend ± 20 - V supplies o
10.9 2P R The 24-Ω case represents a good trade off between voltage and current. V = 2PR
| I=
R (Ω)
V (V)
I (mA)
8
1.27
158
24
2.19
91.3
1000
14.1
14.1
10.10 In the dc steady state, the internal circuit voltages cannot exceed the power supply limits. (a) +15 V (b) -9 V 10.11
(a) For VB = 0.6V , VO = +8V | Av = Av = 32 dB ∠AV = 180
o
dvO dvI
= v I =0.6V
12 − 4 = −40 0.5 − 0.7
| VM ≤ 0.100 V for linear operation
(b) vI (t )= (0.6 + 0.1sin1000t ) V
vO (t )= (8 − 4sin1000t ) V
10-3
10.12 (a) For VB = 0.5V , VO = +12V |
dvO is different for positive and negative values of dvI
VM sin1000t. Thus, the gain is different for positive and negative signal excursions and the output will always be a distorted sine wave. This is not a useful choice of bias point for the amplifier. (b) For VB = 1.1V , VO = +2V and
dvO = 0. The gain is zero for this bias point. dvI
Thus this is also not a useful choice of bias point for the amplifier.
10.13
(a) For V
B
= 0.8V , VO = +3V | Av =
dvO dv I
= v I =0.8V
4−2 = −10 0.7 − 0.9
Av = 20dB ∠AV = 180 o | VM ≤ 0.100 V for linear operation
(b) For V
B
= 0.2V , VO = +14V | Av =
dvO dv I
=0 v I =0.8V
The output signal will be distorted regardless of the value of VM . 10.14 14
vO 12 10
8 6 4
Time 2 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
The amplifier is operating in a linear region. vO = 8 - 4 sin 1000t volts There are only two spectral components: 8 V at dc and -4 V at 159 Hz
10-4
10.15 For sin 1000t ≥ 0, vO = 12 − 4 sin 1000t
For sin 1000t < 0, vO = 12 −1 sin 1000t 14
vO 12
10
8 Time 6 0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
Using the MATLAB FFT capability with a fundamental frequency of 1000/2
Hz:
t=linspace(0,2*pi/1000,1000); y=12-4*sin(1000*t).*(sin(1000*t)>=0)-sin(1000*t).*(sin(1000*t)=0)sin(1000*t).*(sin(1000*t)=0)+2*sin(w).*sin(w)> 50π , Av (s) ≈
2π x 10 5 fH ≈ = 100 kHz | However, we are not that lucky at low frequencies. 2π 10 3 s2 10 3 ω L2 10 3 For s =0.95*anom & a> -400d
SPICE yields: fo = 38.9 kHz, Q = 8.1, Center frequency gain = 38.8 dB. These values are off due to the finite bandwidth of the op-amp and its excess phase shift at the center frequency of the filter. The center frequency is substantially shifted.
11-25
11.85
(a) BW
=
ωo Q
=
1 rad rad | ω L = 0.833 | ω H = 1.167 3 s s
1
rad rad 1 | ω 'o = ω o = 1 | Q' = = 4.65 s s 0.215 1 1 R2 1 | Q= | = 2Qω o C1 = C2 = C : ω o = 2 Rth Rth C C Rth R2 BW ' = BW 2 2 −1 = 0.215
⎛ ⎞2 ⎛ ⎞2 ⎛ ⎞2 2 ⎛ Rth ⎞ ⎜ −2Qsω o ⎟ ⎛ Rth ⎞ ⎜ −6s ⎟ ⎜ −6s ⎟ b A s = | For R3 = ∞, ABP (s) = ⎜ ⎟ =⎜ ⎟ ⎜ ( ) BP ( ) ⎜ ⎟ ⎜ ⎟ s ⎟ ⎝ R1 ⎠ ⎜⎜ s2 + s ω o + 1⎟⎟ ⎝ R1 ⎠ ⎜ s 2 + s + 1⎟ ⎜ s 2 + + 1⎟ ⎝ ⎝ 3 ⎠ 3 ⎠ Q ⎝ ⎠ 2
11.87 Using normalized frequency and R3 = ∞ : 5 kHz → ω o = 1 and 6 kHz → ω o = 1.1 ⎛ −10s ⎞⎛ ⎞ −12s 120s 2 ABP (s) = ⎜ 2 ⎟⎜ ⎟= ⎝ s + 0.2s + 1⎠⎝ s 2 + 0.24s + 1.44 ⎠ s 4 + 0.44s3 + 2.484s2 + 0.528s + 1.44
At the new center frequency s = jω o , − 0.44ω 3o + 0.528ω o = 0 → ω o = 1.095
and A(jω o ) = 1429 = 63.1 dB
The bandwidth points can be found using MATLAB: w=linspace(.9,1.5,250); [m,p,w]=bode([120 0 0],[1 .44 2.484 .528 1.44],w); 20*log10(max(m)) ans = 63.098 ((20*log10(a))>60.098).*(w.'); From this last vector one can easily find: ωo = 1.095 or fo = 5.48 kHz, ωL = 0.970 or fo = 4.85 kHz, ωH = 1.237 or fo = 6.19 kHz, BW = 1.34 kHz, Q = 4.09
11.89 Using ABP = 20 dB at the center frequency : Rin = R1 = 10 kΩ | 10 = KQ = R2 = 100 kΩ | K =
10 1 1 = 2 | R = KR1 = 20 kΩ | C = = = 0.0133 µF. ω o R 2π (600Hz)20kΩ Q
11.90 Q is independent of C in the Tow-Thomas biquad.
11-28
R2 R1
SQ C = 0.
11.91 vO
T/2
T
3T/2
2T
0 t
-5 V
11.92 The waveform going into the low - pass filter is the same as that in Prob. 11.91 ⎛ 8.2kΩ ⎞ except the amplitude will be VM = 1V ⎜− ⎟ = −3.037 V. ⎝ 2.7kΩ ⎠
1T ⎛ 10kΩ ⎞ 2 2 (−3.037) The average value of the waveform is V = ⎜ − = +0.759 V. ⎟ T ⎝ 10kΩ ⎠ 11.93 The Fourier series converges very rapidly since only the even terms exist for n ≥ 2 and the terms decrease as 1/n2. Thus the RMS value will be dominated by the first term (n = 1). ⎛ ω ⎞2 π 1 ω 120π 2 Require : ≤ 0.01 | 50 π ≤ 1+ | ω ≥ = = 2.40 Hz ( ) ⎟ ⎜ o 2 157 157 ⎝ωo ⎠ ⎛ ω ⎞2 1+ ⎜ ⎟ ⎝ωo ⎠ 11.94 vO 0.5 V
t 0 T/2
0
T
3T/2
2T
11.95 vO 1.0 V
t 0 0
T/2
T
3T/2
2T
11-29
11.96 *Figure P11.94 - RECTIFIER VS 1 0 PWL(0 0 1M 1 3M -1 5M 1 7M -1 8M 0) R1 1 2 10K R2 4 5 10K R3 5 6 10K R4 2 4 10K R5 1 5 20K D1 3 2 DIODE D2 4 3 DIODE EOP1 3 0 0 2 1E5 EOP2 6 0 0 5 1E5 .MODEL DIODE D IS=1E-12A .TRAN .01M 8M .PRINT TRAN V(6) .PROBE V(1) V(2) V(3) V(4) V(5) V(6) .END 11.97 *Figure P11.95 - RECTIFIER VS 1 0 PWL(0 0 1M 1 3M -1 5M 1 7M -1 8M 0) R1 0 2 10K R2 4 5 10K R3 5 6 20K R4 2 4 10K D1 3 2 DIODE D2 4 3 DIODE EOP1 3 0 1 2 1E5 EOP2 6 0 1 5 1E5 .MODEL DIODE D IS=1E-12A .TRAN .01M 8M .PRINT TRAN V(6) .PROBE V(1) V(2) V(3) V(4) V(5) V(6) .END 11.98 −V V V V1 = I S exp o1 | VO1 = −VT ln 41 | VO 2 = −VT ln 42 10kΩ VT 10 I S 10 I S ⎛ V V ⎞ VV VO3 = −(VO1 + VO2 )= VT ⎜ ln 41 + ln 42 ⎟ = VT ln 18 2 2 10 I S ⎠ 10 I S ⎝ 10 I S ⎛ VV ⎞ VV V VO = −10 4 I D = −10 4 I S exp D = −10 4 I S exp⎜ ln 18 2 2 ⎟ = − 14 2 VT 10 I S ⎝ 10 I S ⎠
11-30
11.99 Simplify the circuit by taking a Thevenin equivalent of the 5V source and two 10kΩ 10kΩ resistors : VTH = 5V = 2.5V | RTH = 10kΩ 10kΩ = 5kΩ 10kΩ + 10kΩ 100kΩ 5kΩ VO = 5V − Using superposition : V+ = 2.5 +5 = 2.62V 100kΩ + 5kΩ 100kΩ + 5kΩ 100kΩ VO = 0V : V+ = 2.5 = 2.38V VN = 2.62 − 2.38 = 0.24V 100kΩ + 5kΩ 11.100
4.3kΩ = −0.993 V 4.3kΩ + 39kΩ 4.3kΩ = 0.993 V VO = 10V : V+ = 10 4.3kΩ + 39kΩ VN = 0.993 − (−0.993)= 1.99 V VO = −10V : V+ = −10
11.101
4.3kΩ = 0.487 V 4.3kΩ + 39kΩ 4.3kΩ = −0.487 V For VO = −4.3 − 0.6 = −4.9V : V+ = −4.9 4.3kΩ + 39kΩ VN = 0.487 − (−0.487) = 0.974 V For VO = 4.3 + 0.6 = 4.9V : V+ = 4.9
12.9 Driving the output of the circuit in Fig. 12.3 with a current source of value iX: vX v − Av id iX = iO + i2 | i2 = ; iO = X ; v id = −i 2 R1 R1 + R2 RO 1+ Aβ v + Ai 2 R1 R1 iO = X = vX where β = RO RO R1 + R2 1+ Aβ vX v RO i X = vX + and R out = X = (R1 + R2 ) RO R1 + R2 i X 1+ Aβ 12.10
Assuming i− 1 R1 + R2 200 200
Ro 35 ≅ = 0.14Ω meets the specification 1+ Aβ 250
R in = Rid (1+ Aβ )≅ 500kΩ(250)= 125MΩ does not meet the requirements. So the specifications cannot be met using a single-stage amplifier built using the op-amp that was specified in the problem. 12.17 The non-inverting amplifier is the only one that can hope to achieve both the required gain and with such a high value of input resistance:
Av =
1
β
= 200 and Aβ =
10 4 = 50 200
Rin = Rid (1+ Aβ ) = 1MΩ(51) = 51 MΩ - too small R out =
Ro 100Ω = = 1.96Ω - too large (1+ Aβ ) 51
If the gain specification is met, the input and output resistance specifications will not be met. 12.18
⎛ R2 ⎞⎛ Aβ ⎞ The open-circuit voltage is v th = v s ⎜− ⎟⎜ ⎟ . Checking the loop-gain: ⎝ R1 ⎠⎝ 1+ Aβ ⎠ ⎛ R ⎞ ⎛ ⎛110kΩ ⎞ ⎞ 6.8kΩ Aβ = (5x10 4 )⎜ ⎟ = 2910 >> 1 so v th = v S ⎜− 2 ⎟ = −v S ⎜ ⎟ = −16.2v S ⎝ 6.8kΩ + 110kΩ ⎠ ⎝ 6.8kΩ ⎠ ⎝ R1 ⎠
Rth = Rout =
12-6
Ro R 250Ω ≅ o = = 85.9 mΩ 1+ Aβ Aβ 2910
12.19 A v S . Checking the loop gain : 1+ Aβ ⎛ R2 ⎞ ⎛ ⎛ ⎞ 56kΩ ⎞ 0.39kΩ Aβ = 10 4 ⎜ ⎟ = 69.2 >> 1 so vth ≅ vS ⎜1+ ⎟ = v S ⎜1+ ⎟ = 145 vS ⎝ 0.39kΩ + 56kΩ ⎠ ⎝ 0.39kΩ ⎠ ⎝ R1 ⎠
The open circuit voltage is vth =
or more exactly : vth = v S
Ro 200Ω A 10 4 = vS = 143 vS | Rth = Rout = = = 2.85 Ω 1+ 69.2 1+ Aβ 70.2 1+ Aβ
12.20 Applying the definintion of fractional gain error: R ⎡ R2 (1± ε)⎤ Aβ ⎥ − 2 − ⎢− ⎡ (1± ε)⎤ Aβ R1 ⎢⎣ R1(1 m ε)⎥⎦ 1+ Aβ Aβ ⎥ FGE = = 1− ⎢ ≅ 1− (1± 2ε) R 1+ Aβ ⎢⎣ (1 m ε)⎥⎦ 1+ Aβ − 2 R1 FGE ≅ 1−
Aβ 1 Aβ Aβ m 2ε = m 2ε 1+ Aβ 1+ Aβ 1+ Aβ 1+ Aβ
For Aβ >> 1, FGE ≅ 1 m 2ε = Aβ
1
(
)
1 2x10 1000 5
106
1 m 2ε which must be ≤ 0.01. A = 10 20 = 2.00x105 Aβ m 2ε ≤ 0.01 | Taking the positive sign, 2ε ≤ 0.005 and ε ≤ 0.25%
12.21 Using the results from Prob. 12.20, 54
Av = 10 20 = 501 | For Aβ =
4x10 4 1 = 79.8 >> 1, so FGE ≅ m 2ε which must be ≤ 0.02 501 Aβ
1 1 m 2ε = m 2ε ≤ 0.02 | Taking the positive sign, 2ε ≤ 0.00747 and ε ≤ 0.374% 79.8 Aβ
12.22 V+ = 3V
99kΩ 3 - 2.722 2.722 − VO = 2.722 V | = 10.1kΩ + 99kΩ 9.9kΩ 101kΩ
| VO = −0.111 V | VOideal = 0 V
12-7
12.23
99kΩ 3.95 - 3.675 3.675 − VO = 3.675 V | = | VO = 0.869 V 101kΩ 10.1kΩ + 99kΩ 9.9kΩ For matched resistors, VOideal = −10(V1 − V2 ) = −10(3.95 − 4.05)= +1.00 V
V+ = 4.05V
⎛ 1− 0.869 ⎞ ⎟ = 13.1% 1 ⎝ ⎠
ε = 100%⎜ 12.24
v1 + v 2 = 10sin120πt V and v id = v1 − v 2 = 0.50sin5000πt V 2 v − v− v ic − v + 0.09258 99kΩ = 0.90742v ic | i = ic = = v ic (b) v + = v ic 9.9kΩ 9.9kΩ 9.9kΩ 10.1kΩ + 99kΩ 0.09258 v O = v− − i(101kΩ) = v + − i(101kΩ) = 0.90742v ic − v ic (101kΩ) 9.9kΩ v v O = −0.037v ic and Acm = O = −0.037 | The value of Adm = −10 is not v ic
(a) v ic =
affected by the small tolerances.
(c) CMRR =
Adm = 270 - a paltry 48.6 dB Acm
(d ) vO = Admv id + Acmv ic = −0.370sin(120πt ) − 5.00sin(5000πt ) V 12.25 5 + 5.01 = 5.005V. The maximum equivalent input error is 2 5.005 VIC = = 0.500 mV , but the sign is unknown. Therefore the meter reading CMRR 10 4 may be anywhere in the range 9.50 mV ≤ Vmeter ≤ 10.5 mV.
VIC =
12-8
12.26
(a) V = 15V 10kΩ + 30kΩ = 11.25 V 30kΩ
10kΩ = 3.75 V 10kΩ + 30kΩ 20kΩ V + V 11.25 + 3.75 V1 - V2 = 15V = 7.50 V | VCM = 1 2 = = 7.50V. 2 10kΩ + 30kΩ 2 VCM VCM The maximum equivalent input error is . We need < 10−4 (V1 - V2 ) CMRR CMRR 4 10 (7.5V ) CMRR > = 10 4 or 80 dB. 7.5V 10.2kΩ 10kΩ (b) V1 = 15V 20.2kΩ = 7.574 V | V2 = 15V 20.2kΩ = 7.426 V 200Ω V +V V1 - V2 = 15V = 0.1485 V | VCM = 1 2 = 7.50V. 2 20.2kΩ 10 4 (7.5V ) VCM −4 We need < 10 (V1 - V2 ) or CMRR > = 5.05x105 or 114 dB. CMRR 0.1485V 1
| V2 = 15V
12.27 One worst-case tolerance assignment is given below. The second is found by reversing the pairs of resistor values.
i
9.995 k Ω
i
10.005 k
Ω v
O
v i c
+ 10.005 k
Ω 9.995 k Ω
9.995 v −v v − v+ 0.50025 = 0.49975v ic | i = ic − = ic = v ic 9.995kΩ 9.995kΩ 9.995kΩ 10.005 + 9.995 0.50025 vO = v− − i(10.005kΩ)= v + − i(10.005kΩ)= 0.49975v ic − v ic (10.005kΩ) 9.995kΩ v vO = −0.001vic and Acm = O = −0.001 | The value of Adm = 1 is not affected by the vic v+ = v ic
(b) V = (−0.005V − 0.001V )1+ Aβ = (−0.005V − 0.001V ) A
O
(c) Error
=
-0.460 - (-0.546) = −0.187 or −18.7% -0.460
12.38 Inverting Amplifier : vO = Av v S = −6.2vS as long as v O ≤ 10V as constrained by the op - amp power supply voltages
(a) VO = −6.2() 1 = -6.2V, feedback loop is working and V- = 0 (b) VO = −6.2(−3) = +18V; VO saturates at VO = +10V
The feedback loop is "broken" since the open - loop gain is now 0. (The output voltage does not change when the input changes so A = 0) 6.2kΩ 1kΩ + 10 = −1.19V By superposition, V− = −3 7.2kΩ 7.2kΩ
12.39 vO
10 V Gain = -6.2
5V
vS -2 V
-1 V
1V
2V
-5 V
-10 V
12-13
12.40 Inverting Amplifier : vO = Av v S = −10vS as long as v O ≤ 10V as constrained by the op - amp power supply voltages
(a) VO = −10(0.5) = -5.00 V, the feedback loop is working, and V- = 0 (b) VO = −10(1.2) = -12.0V; VO saturates at VO = +10V
The feedback loop is "broken" since the open - loop gain is now 0. (The output voltage does not change when the input changes so A = 0) 10kΩ 1kΩ −10 = 0.182 V By superposition, V− = 1.2 11kΩ 11kΩ
12.41 vO
10 V
5V
Gain = -10.0
vS -2 V
-1 V
1V
2V
-5 V
-10 V
12.42 Noninverting Amplifier : vO = Av v S = +40vS as long as v O ≤ 15V (a) VO = 40(0.25V ) = +10V, the feedback loop is working, and VID = 0
(b) VO = 40(0.5V ) = 20V; VO saturates at VO = +15V
The feedback loop is "broken" since the open - loop gain is now 0. (The output voltage does not change when the input changes so A = 0) 1kΩ = 0.125V. VID = V+ − V− = 0.5V −15 1kΩ + 39kΩ
12-14
12.43 vO 15 V
7.5 V Gain = +40.0 vS -1 V
-0.5 V
0.5 V
1V
-7.5 V
-15 V
12.44 Noninverting Amplifier : vO = Av v S = +43.9vS as long as v O ≤ 15V (a) VO = 43.9(0.25V ) = +11.0V, feedback loop is working, and VID = 0 (b) VO = 43.9(0.5V ) = 22.0V; VO saturates at VO = +15V
The feedback loop is "broken" since the open - loop gain is now 0. (The output voltage does not change when the input changes so A = 0) 0.91kΩ = 0.158 V. VID = V+ − V− = 0.5V −15 0.91kΩ + 39kΩ
12-15
12.45 v
S
+
i
O
i
L
v
O
i2
10 k Ω R R
2
1
iO = iL + i2 and iO ≤ 1.5mA. The output voltage requirement gives i L ≤ which leaves 0.500mA as the maximum value of i2 . i2 = The closed - loop gain of 40 db (A v = 100) requires
10V = 1.00mA 10kΩ
10V gives (R1 + R2 )≥ 20kΩ. R1 + R2
R2 = 99. R1
The closest ratio from the resistor tables appears to be
R2 = 100 which is within 1% R1
of the desired ratio. (This is close enough since we are using 5% resistors.) There are many many choices that meet both
R2 = 100 and (R1 + R2 )≥ 20kΩ. R1
However, the choice, R1 = 200Ω and R 2 = 20kΩ is not acceptable because its minimum value does not meet the requirements : 20.2kΩ(1− 0.05) = 19.2kΩ.
The smallest acceptable pair is R1 = 220Ω and R 2 = 22kΩ.
12-16
12.46 R R v
2
1
i
2
S
v
5k Ω
L
R
O
+
i
i O
L
15V = 3 mA so i 2 ≤ 1 mA 5kΩ v 15 i 2 = O ≤ 1 mA requires R 2 ≥ = 15kΩ R2 .001 i O = i L + i 2 ≤ 4mA and i L =
To account for the resistor tolerance, 0.95R2 ≥ 15kΩ requires R 2 ≥ 15.8kΩ . For AV = 46 dB = 200, R2 = 200 R1, and one acceptable resistor pair would be R1 = 1 kΩ and R2 = 20 kΩ. Many acceptable choices exist. An input resistance constraint might set a lower limit on R1.
12.47 The maximum base current is limited to 5 mA, so the maximum emitter current is limited to
I E = (β F + 1)I B = 51(5mA)= 255 mA. Since I E =
10V 10V , R≥ = 39.2 Ω. R 255mA
12.48 R R v
2
1
i
2
S
v
5k Ω
L
R
O
+
i
i O
L
10V 10V = 2.5 mA and iL = = 2 mA so i2 ≤ 0.5 mA 4kΩ 5kΩ 10V R R2 ≥ = 20kΩ Av = 46dB ⇒ 2 = 200 R1 0.5mA
iO = iL + i2 ≤
One possible choice would be R2 = 20 kΩ and R1 = 100 Ω. However, the op-amp would not be able to supply enough output current if tolerances are take into account. Better choices would be R2 = 22 kΩ and R1 = 110 Ω or R2 = 200 kΩ and R1 = 1 kΩ which would give the amplifier a much higher input resistance. (b) V =
vo max 200
=
10V = 50 mV (c) Rin = R1 = 110 Ω and 1 kΩ for the two designs given above. 200
Overall amplifier : 10kΩ (−5.00)= +50.0 | Rin = 24.0 kΩ | Rout = 6.00 mΩ 10.0kΩ + 11.0mΩ For all practical purposes, the numbers the same. R out = 6.00 mΩ is a good Av = −10.0
approximation of 0 Ω, and Av = −10.0(−5.00)= +50.0
12.56 −60db/decade requires 3 poles - 3 x (-20db/decade). Using three identical fH3 amplifiers : Av = 3 1000 = 10 and f H1 = = 1.96(20kHz) = 39.2kHz. 1
R2 = 10R1 | f H =
1 | R2C = = 4.06x10−6 s 3 2πR2C 2π 39.2x10
Try C = 270 pF. R2 =
12-20
2 3 −1 1
(
)
1 = 15.0 kΩ, R1 = 1.5kΩ 2πf H C
12.57
s + ωB Ro Ro = = Ro ω 1+ A(s)β 1+ s + ω B + ωT β T β s + ωB s s 1+ 1+ s + ωB Ro Ro ωB ωB = Ro = ≅ s s + ω B (1+ Aoβ ) (1+ Aoβ ) 1+ (1+ Aoβ ) 1+ s ω B (1+ Aoβ ) βωT
⎞ ⎟ ⎛ s + ωB ) ⎞ ⎟ = R1 + ⎜ Rid R2 ( ⎟ s + ω B + ωT ⎠ ⎟ ⎝ ⎟ ⎠
(s + ω B )
Rid R2 (s + ω B ) s + ω B + ωT = R1 + (s + ω B ) Rid (s + ω B + ωT ) + R2 (s + ω B ) Rid + R2 s + ω B + ωT ⎛ ⎛ R2 s ⎞ s ⎞ Rid R2ω B ⎜1+ Rid ⎟ ⎜1+ ⎟ 1+ Ao ) ( ⎝ ωB ⎠ ⎝ ωB ⎠ Z in = R1 + = R1 + Rid + R2 s R2 Rid ω B (1+ Ao ) + R2ω B + s(Rid + R2 ) 1+ Rid + (1+ Ao ) ω B (1+ Ao ) Rid + R2 (1+ Ao ) Z in = R1 +
⎛ s ⎞ 1+ ⎜ ⎟ ⎛ R2 ⎞ ⎝ ωB ⎠ ⎟ Z in = R1 + ⎜⎜ Rid Rid + R2 s (1+ Ao )⎟⎠ 1+ ⎝ ω B (1+ Ao ) R + R2 id (1+ Ao )
We see from the spreadsheet that a cascade of seven identical stages is required to achieve the bandwidth specification. Fortuitously, it also meets the input and output resistance specs. For the non-inverting amplifier cascade: R R AV = 1+ 2 = 4.12 → 2 = 3.12 R1 R1 A similar spreadsheet for the cascade of identical inverting amplifiers indicates that it is impossible to meet the bandwidth requirement.
12-27
12.66
R2 R = 4.12 → 2 = 3.12 | Exploring the 5% resistor R1 R1 R tables, we find R2 = 62kΩ and R1 = 20kΩ yields 2 = 3.10 as a reasonable pair. R1
(a) From Problem 11.99, Av = 1 +
The nominal gain of the cascade is then Av = (4.10) =1.948 x 10 4 . 7
Av = 86db ± 1dB ⇒ 1.778 x 10 4 ≤ AV ≤ 2.239 x 10 4 and the gain is well within this range. Many amplifiers will probably fail due to tolerances with 5% resistors. A Monte Carlo analysis would tell us. If we resort to 1% resistors to limit the tolerance spread, R2 = 30.9 kΩ and R1 = 10.0 kΩ is one of many possible pairs. 1 5 x10 6 | f H1 = βf T = = 1.22 MHz (b) For R2 = 62kΩ and R1 = 20kΩ, β = 4.1 4.1 1
f H = 1.22 MHz 2 7 − 1 = 394 kHz
12-28
12.67/12.68 One possibility: Use a cascade of two non-inverting amplifiers, and shunt the input of the first amplifier to define the input resistance.
60db → Av = 1000 | A single - stage amplifier with a gain of 1000 would have a bandwidth of only 5 kHz using this op - amp. Two stages should be sufficient if Rin and R out can also be met. A design with f H 2 >> f H1 will be tried. First stage : Non - inverting with bandwidth of 20 kHz f 20kHz 1 β1 = H1 = = 0.004 | Av1 = = 250 → Av 2 = 4 → β 2 = 0.25 → f H 2 = 1.25 MHz fT 5 MHz β1 Since f H 2 >> f H1, f H = f H1 = 20kHz. Ao = 85 dB = 17800 100 Ro2 = = 0.0225Ω which is ok. Checking Rout = 1 + Aoβ 2 1 + 17800(0.25) Choosing resistors from the Appendix, a possible set is Amplifier 1: R1 = 1.2kΩ, R 2 = 300 kΩ and shunt the input with R 3 = 27kΩ Amplifier 2 : R1 = 3.3kΩ, R 2 = 10 kΩ ⎛ ⎞ ⎜ 17800 17800 ⎟ Checking gain : Av = = 997.5 = 60.0 dB ⎜ 17800 17800 ⎟ ⎜1 + ⎟ 1+ 251 ⎝ 4.03 ⎠ vS
12.72 function [gain,bw]=Prob1272a ao=50000; ft=1e6; for i=1:500, r1=22000*(1+0.1*(rand-0.5)); r2=130000*(1+0.1*(rand-0.5)); beta=r1/(r1+r2); gain(i)=ao/(1+ao*beta); bw(i)=beta*ft; end; end [gain,bw]=prob1272a; mean(gain) ans = 6.9140 std(gain) ans = 0.2339 mean(bw) ans = 1.4478e+05 std(bw) ans = 4.8969e+03 Three sigma limits: 6.21 ≤ Av ≤ 7.62
130 kHz ≤ BW ≤ 159 kHz
function [gain,bw]=Prob1272b for i=1:500, ao=100000*(1+1.0*(rand-0.5)); ft=2e6*(1+1.0*(rand-0.5)); r1=22000*(1+0.1*(rand-0.5)); r2=130000*(1+0.1*(rand-0.5)); beta=r1/(r1+r2); gain(i)=ao/(1+ao*beta); bw(i)=beta*ft; end; end [gain,bw]=prob1272b; mean(gain) ans = 6.9201 std(gain) ans = 0.2414 mean(bw) ans = 2.8925e+05 std(bw) ans = 8.5536e+04 Note that the bandwidth is essentially a uniform distribution. 3σ: 6.20 ≤ Av ≤ 7.64 98.9% of the values fall between: 146 kHz ≤ BW ≤ 439 kHz
12.73
(
)
SR ≥ VOω = (15V )(2π ) 2x10 4 Hz = 1.89x106
12.74 f =
SR 10V 1 = −6 = 159 kHz 2πVo 10 s 20πV
12.75
12-32
V V or 1.89 µs s
The negative transition requires the largest slew rate : SR =
V ∆V 20V = = 10 µs 2µs ∆t
12.76 (a) For the circuit in Fig. 12.26 : Rid = 250 kΩ | R = 1 kΩ − an arbitrary choice
ωB =
(
2π 5 x106 8 x10
4
) = 125π rad/s |
C=
1
ωB R
=
1
(125π )1000
= 2.55 µF | Ro = 50Ω | Ao = 80,000
(b) Add a resistor from each input terminal to ground of value 2 R
12.80 Student PSPICE cannot handle 6 copies of the uA741 op amp, but since all the stages are the same, we can square the output from a 3-stage version or cube the output from a two-stage model.
200
100
0
-100 100Hz 300Hz 1.0KHz DB(V(I1:+))+ DB(V(I1:+))
3.0KHz
10KHz
30KHz
100KHz
300KHz
1.0MHz
3.0MHz
10MHz
Frequency
From the SPICE graph, BW = 54.3 kHz.
12-35
12.81 *PROBLEM 12.81 - Six Stage Amplifier VS 1 0 AC 1 XA1 1 2 0 AMP XA2 2 3 0 AMP XA3 3 4 0 AMP XA4 4 5 0 AMP XA5 5 6 0 AMP XA6 6 7 0 AMP .SUBCKT AMP 1 2 8 RID 1 3 1E9 RO 7 2 50 E2 7 8 6 8 1E5 *Two dummy loops provide separate control of Gain & BW tolerances G1 8 4 1 3 .001 R11 4 8 RG 1000 E1 5 8 4 8 1 RC 5 6 1000 C 6 8 CC 15.915UF * R2 2 3 RR 130K R1 3 8 RR 22K .ENDS .MODEL RR RES (R=1 DEV=5%) .MODEL RG RES (R=1 DEV=50%) .MODEL CC CAP (C=1 DEV=50%) .AC DEC 20 1E3 1E6 .PROBE V(7) .PRINT AC V(7) .MC 1000 AC V(7) MAX OUTPUT(EVERY 20) *.MC 1000 AC V(7) MAX OUTPUT(RUNS 77 573 597 777) .END Maximum gain = 103 dB; Minimum gain = 98.5 dB Maximum Bandwidth = 65 kHz; Minimum bandwidth = 38 kHz (These are approximate.) 12.82 1 = 7.96 pF 2π (1000Ω)(20 MHz)
Rid = 1010 Ω
C=
12.83 A ≥ 118 dB
CMRR ≥ 80 dB
I B ≤ 8.8 nA
IOS ≤ 2.2 nA
12-36
Ro not specified
PSRR ≥ 100 dB VOS ≤ 1.5 mV Power Supplies ± 18 V maximum
Nominal values only : Rid = 1010 Ω
12.84
A = 4 x106
SR = 12.5 V/µs nominal
f T = 20 MHz
(a ) Use the expressions in Tables 12.1 and 12.2. 100
Ro 250Ω = = 40.0 mΩ 1 + Aβ 105 1+ 16 2 MHz 2 MHz = 182kHz f HC = βC fT = = 125kHz f HA = f HB = β A fT = 11 16 For the overall amplifier : Av = −1500 | Rin = 47.0 kΩ | Rout = 40.0 mΩ Rout = RoutC =
vOA v = +5.00 µV | v -B = OB5 = −50.0 µV 5 -10 -10 The output of the third amplifier is saturated at -18 V, and the inverting input is no longer near 270kΩ 18 kΩ + (−18V ) = +3.56 V ground potential. Using superposition, v -C = 5V 18kΩ + 270kΩ 18kΩ + 270kΩ The remaining three nodes are V+ = +18 V V− = −18 V and Vgnd = 0 V .
Ro 250Ω = = 40.0 mΩ 1+ Aβ 105 1+ 16 R 250Ω Ro 250Ω max max min min o Rout ≅ RoutC = = = 43.9 mΩ Rout ≅ RoutC = = = 36.4 mΩ min 5 max 10 105 1+ Aβ 1+ Aβ 1+ 1+ 17.6 14.6 2 MHz 2 MHz f HA = f HB = β A fT = = 182kHz f HC = βC fT = = 125kHz 11 16 Using the definition of bandwidth : 10 10 15 1500 = → f H = 79.8 kHz 2 2 2 2 ⎛ fH ⎞ ⎛ fH ⎞ ⎛ fH ⎞ 1+ ⎜ ⎟ 1+ ⎜ ⎟ 1+ ⎜ ⎟ ⎝182kHz ⎠ ⎝182kHz ⎠ ⎝ 125kHz ⎠ nom nom Rout ≅ RoutC =
2 MHz 2 MHz = 200kHz f HC = βC fT = = 137kHz 10.0 14.6 9.048 13.57 1111 = → f Hmax = 87.5 kHz 2 2 2 ⎛ f max ⎞ ⎛ f max ⎞ 1+ ⎜ H ⎟ 1+ ⎜ H ⎟ ⎝ 200kHz ⎠ ⎝ 137kHz ⎠
max max f HA = f HB = β A fT =
9.048 ⎛ f max ⎞2 1+ ⎜ H ⎟ ⎝ 200kHz ⎠
2 MHz 2 MHz = 167kHz f HC = βC fT = = 114kHz 12.0 17.6 11.05 16.58 2025 = → f Hmax = 73.0 kHz 2 2 2 ⎛ f max ⎞ ⎛ f max ⎞ H H 1+ ⎜ ⎟ 1+ ⎜ ⎟ ⎝167kHz ⎠ ⎝ 114kHz ⎠
max max f HA = f HB = β A fT =
11.05 ⎛ f max ⎞ 1+ ⎜ H ⎟ ⎝167kHz ⎠
2
12-38
12.86 (a ) Use the expressions in Tables 12.1 and 12.2. Three identical gain blocks. A = 10
5MHz = 185kHz f H = f H1 2 3 −1 = 94.3kHz f H1 = β A f T = 27 For the overall amplifier : Av = +19700 | Rin = 1.50 MΩ | Rout = 38.8 mΩ | f H = 94.3 kHz
Ro 250Ω = = 98.0 mΩ 1+ Aβ 10 4 1+ 4.9 3MHz 3MHz = 612kHz f HC = βC fT = = 29.7kHz f HC = f HA = β A fT = 4.9 101 For the overall amplifier : Av = −2380 | Rin = 613 MΩ | Rout = 98.0 mΩ Rout = RoutC =
Using the definition of bandwidth : 99
4.9 ⎛ fH ⎞ 1+ ⎜ ⎟ ⎝ 612kHz ⎠
2
4.9
⎛ fH ⎞ 1+ ⎜ ⎟ ⎝ 29.7kHz ⎠
2
⎛ fH ⎞ 1+ ⎜ ⎟ ⎝ 612kHz ⎠
2
=
2380 2
→ f H = 29.6 kHz
Note that the bandwidth is controlled by amplifier B because it's bandwidth is much smaller than the others.
Ro 200Ω = = 98.0 mΩ 1+ Aβ 10 4 1+ 4.9 Ro 200Ω Ro 200Ω max max min min Rout ≅ RoutC = = = 115 mΩ Rout ≅ RoutC = = = 83.4 mΩ min 4 max 10 10 4 1+ Aβ 1+ Aβ 1+ 1+ 5.77 4.19 3MHz 3MHz f HA = f HB = β A fT = = 612 kHz f HC = β B fT = = 29.7kHz 4.9 101 The bandwidth is controlled by the narrow bandwidth stage. nom nom Rout ≅ RoutC =
f Hnom = 29.7 kHz
12-42
f Hmin = β Bmin f T =
3MHz = 24.3 kHz 123
f Hmax = β Bmax f T =
3MHz = 36.2 kHz 82.8
CHAPTER 13 13.1 Assuming linear operation : vBE = 0.700 + 0.005sin 2000πt V ⎡⎛ 5mV ⎞ ⎤ vce = ⎢⎜ ⎟(−1.65V )⎥ sin 2000πt = −1.03sin 2000πt V ⎣⎝ 8mV ⎠ ⎦ vCE = 5.00 −1.03sin 2000πt V ; 10 - 3300IC ≥ 0.700 → IC ≤ 2.82 mA
13.2 Assuming linear region operation : vGS = 3.50 + 0.25sin 2000πt V ⎡ 0.25V ⎤ −2V )⎥ sin 2000πt = −1.00sin 2000πt V vds = ⎢ ( ⎣0.50V ⎦ vDS = 4.80 −1.00sin 2000πt V vDS ≥ vGS − VTN →10 − 3300I D −1.00sin 2000πt ≥ 3.50 + 0.25sin 2000πt −1 For sin 2000πt = 1, I D ≤
10 −1− 3.5 − 0.25 + 1 V = 1.89 mA 3300 Ω
13.3 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a coupling capacitor that couples the ac component of the signal at the collector to the output vO. C3 is a bypass capacitor. (b) The signal voltage at the top of resistor R4 will be zero. 13.4 (a) C1 is a bypass capacitor. C2 is a coupling capacitor that couples the ac component of vI into the amplifier. C3 is a coupling capacitor that couples the ac component of the signal at the collector to output vO. (b) The signal voltage at the base will be vb = 0. 13.5 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a bypass capacitor. C3 is a coupling capacitor that couples the ac component of the signal at the collector to output vO. (b) The signal voltage at the emitter will be ve = 0. 13.6 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a bypass capacitor. C3 is a coupling capacitor that couples the ac component of the signal at the drain to output vO. (b) The signal voltage at the source will be vs = 0. 13.7
13-1
(a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a coupling capacitor that couples the ac component of the signal at the drain to output vO. 13.8 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a bypass capacitor. C3 is a coupling capacitor that couples the ac component of the signal at the drain to output vO. (b) The signal voltage at the source will be vs = 0. 13.9 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a bypass capacitor. C3 is a coupling capacitor that couples the ac component of the signal at the collector to output vO. (b) The signal voltage at the emitter will be ve = 0. 13.10 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a coupling capacitor that couples the signal from the emitter of Q1 back to the node joining R1 and R2. C3 is a coupling capacitor that couples the ac component of the signal at the emitter to the output vO. (b) The signal voltage at the collector will be zero. 13.11 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a bypass capacitor. C3 is a coupling capacitor that couples the ac component of the signal at the drain to the output vO. (b) The signal voltage at the top of R4 will be zero. 13.12 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a coupling capacitor that couples the ac component of the signal at the drain to output vO. 13.13 (a) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a coupling capacitor that couples the ac component of the signal at the drain to the output vO. 13.14 dc voltage sources produce constant values of output voltage. Hence no signal voltage can appear at the terminals of the source. The signal component of the voltage is forced to be zero, and a direct path to ground is provided for signal currents.
VCE = 18 − 2.7x105 IC − 2.28x105 I E = 6.99 V Q − point : (22.0 µA, 6.99 V )
13.16 SPICE results: (a) (22.5 µA, 6.71 V) (b) (22.6 µA, 6.69 V) The discrepancies between the results in Probs. 13.15 and 13.16 arise because VBE = 0.575 V with IS = 5 fA. Very little changes occurs with the addition of VA. 13.17 NPN Common-Emitter Amplifier +12 V
3.9 k Ω IG = 0, so VG = 0. Assume active region operation. 2 4x10−4 VGS + 5) | VGS = −2000I D ( 2 M 2 4x10−4 VGS = −2000 VGS + 5) → VGS = −2.50V ( 2 V I D = − GS = 1.25 mA 2000 2 k Ω VDS = 18 − 3900I D − 2000I D = 10.6V
ID =
RG
10 M Ω
Q − point : (1.25 mA, 10.6 V )
13.34 SPICE results: The Q-point is the same (1.25 mA, 10.6 V) .
13-9
13.35 +15 V
7.5 k Ω
M RG 2 225x10−6 0 − (−3) = 1.01 mA IG = 0, so VG = 0 and VGS = 0. I D = 2 Q − point : (1.01 mA, 7.41 V ) VDS = 15 − 7500I D = 7.41V
[
2.2 M Ω
]
13.36 SPICE results: The Q-point is the same (1.01 mA, 7.41 V). 13.37 (a)
+ Q
R
C
R
RI vi
vo
3
R1
R2 RE
(b)
+ vi
+
RI
RB
ro
v rπ
-
gmv
RE
13-10
RC
R
3
vo -
(c) C1 is a coupling capacitor that couples the ac component of vI into the amplifier. C2 is a coupling capacitor that couples the ac component of the signal at the collector to the output vO. C3 is a bypass capacitor. 13.38(a) Figure P13.4 Q1
+
RI v
R
RE
i
R
C
vo
3
-
(a)
(c ) ro -
RI v
R
i
g v m
v E
rπ
C1 − Bypass +
RC
R3
vo
+
(b)
C2 − Coupling
-
C3 − Coupling 13.38(b) Figure P13.5 RI
+ Q1
vi
R1
R
R
C
v
3
o
R2
(c )
-
(a)
C1 − Coupling RI vi (b)
R1
R2
rπ
+
+
v
vo
-
g v m
ro
R
C
R
3
-
C2 − Bypass C3 − Coupling
13-11
13.39(a) Figure P13.9 + Q R
RI vi
R
R
C
v
3
o
R
1
(c )
-
2
(a)
C1 − Coupling RI vi
R
R
1
rπ
2
(b)
+
+
v
v g v
-
m
r
o
R
C
R
3
Q1 RI R
1
vi
+ R
RE
2
(a)
R
v
o
3
(c )
-
+
RI R1 vi
C1 − Coupling
v rπ
-
ro
g v m
C2 − Coupling
+
13-12
C2 − Bypass
-
C3 − Coupling
13.39(b) Figure P13.10
(b)
o
R2
RE
R
v
o
3
-
C3 − Coupling
13.40(a) Figure P13.6 R
I
+
M
1
R
R
D
vi
R1
v
3
o
R
(c )
-
2
(a)
C1 − Coupling +
R
+
I
vi
v R1
R
2
-
(b)
r
gm v
R
o
D
R
vo 3
C2 − Bypass
-
C3 − Coupling
13.40(b) Figure P13.7 M
1
+
RI vi
R
D
R1
R
v
3
o
-
(a)
(c )
ro -
RI vi (b)
R
1
v +
+ gmv RD
R
vo
C1 − Coupling
3
-
C2 − Coupling
13-13
13.41(a) Figure P13.8 +
M
1
RD
RI vi
R1
R
v
3
o
R2
(c )
-
(a)
C1 − Coupling +
RI vi
+
v R1
R2
gmv
-
(b)
ro
RD
R
vo 3
C2 − Bypass
-
C3 − Coupling
13.42(a) Figure P13.12 M1
+
RI vi
RD
R
1
R
vo
3
-
(a)
(c )
r
o
-
RI vi (b)
v R
1
+
+ gmv RD
R
v
o
C1 − Coupling
3
-
C2 − Coupling
13.43 RI: Thévinen equivalent source resistance; R1: base bias voltage divider; R2: base bias voltage divider; RE and R4: emitter bias resistors - determine the emitter current; RC: collector bias resistor - sets the collector-emitter voltage; R3: load resistor 13.44 RI: Thévinen equivalent source resistance; R1: gate bias voltage divider; R2: gate bias voltage divider; R4: source bias resistor - sets source current; RD: drain bias resistor - sets drain-source voltage; R3: load resistor
13-14
13.45 RI: Thévinen equivalent source resistance; R1: base bias voltage divider; R2: base bias voltage divider; RE: emitter bias resistor - determines the emitter current; RC: collector bias resistor - sets the collector-emitter voltage; R3: load resistor 13.46
SPICE AV result is somewhat lower because ro is included. 13.67 Av ≅ −10VCC = −10(12) = −120 13.68 Av ≅ −10(VCC + VEE ) = −10(15 + 15) = −300 13.69 Av = −10(VCC + VEE )= −10(1.5 + 1.5)= −30; This estimate says no.
However, if we look a bit deeper, Av = −40(IC RC ) = −40VRC ,and we let VRC = then we can achieve A v = −40(1.5)= −60.
(V
CC
+ VEE ) 2
= 1.5V ,
So, with careful design, we can probably achieve a gain of 50. 13.70 Using our rule - of - thumb estimate,
1 = −10 Av ≅ −10VCC = −10(1.5)= −15 | Av = −10()
Note that this result assumes that IC varies with VCC. 13.71
(a) i = 10kΩ = 0.5 mA, but i ≤ 0.2I for small - signal operation. (b) V ≥ V + i R + I R = 0.7 + 5 + 25 = 30.7 V 5V
c
CC
c
BE
c
L
C
C
So IC ≥ 5ic = 2.5 mA.
L
13.72 Av = 40dB = 100 | v o = 100v be = 100(0.005V ) = 0.500V .
13-23
13.73 For common - emitter stage : Av = 50dB → Av = −316
15V = 47.5mV which is far too big for small- signal operation. 316 The will be significant distortion of the sine wave. vbe =
13.83 Virtually any Q-point is possible. RIN is set by RG which can be any value desired since there is no gate current. (Note this is not the case with a BJT for which base current must be considered.)
13-26
13.84 Note that iG ≅ 0 for this device.
Load line : 400 = 133000iP + v PK and vGK = −1.5V Two points (i P , v PK ) : (3mA, 0V) and (0mA, 400V) → Q - pt : (1.4 mA, 215 V) ro =
250V − 200V 2.3mA − 0.7mA = 55.6kΩ | g m = = 1.6mS | µ f = 89.0 2.15mA −1.25mA −1V − (−2V )
(
)
(
)
Av = −g m RP ro = −1.6mS 133kΩ 55.6kΩ = −62.7 13.85
gm2 (0.5S) = 5 A! BJT : IC = gmVT = 0.5S (0.025V ) = 12.5mA | MOSFET : ID = = 2K n 2(25mA /V 2 ) 2
The BJT can achieve the required transconductance at a 400 times lower current than the MOSFET. For a given power supply voltage, the BJT will therefore use 400 times less power. 60 = 120Ω (versus ∞ for the FET). Note, however, that rπ is small for the BJT: rπ = 0.5 13.86 Since a relatively high input resistance is required at a relatively high current, a FET should be used. If a BJT were selected, it would be very difficult to achieve the required input resistance because its value of rπ is low: β V 100(.025V ) rπ = o T = = 250 Ω IC 10mA 13.87
13.88 V I µ f ≅ A = 40VA = 40(50)= 2000 | g m = C = 40IC = 40 2x10−4 = 8.00 mS VT VT
(
)
(
)
2 2x10−4 2 2 2I D µf ≅ = = 200 | g m = = = 0.800 mS VGS − VTN 0.5 λ(VGS − VTN ) 0.02(0.5)
13-27
13.89 Either transistor could be used. For a BJT operating in the common-emitter configuration or an FET operating in the common-source configuration:
100(0.025V ) = 33.3 mA - A fairly high current rπ 75Ω For the FET : Rin = RG and setting RG = 75 Ω is satisfactory, particularly if a depletion mode FET is available. The input of a CE circuit operating at a much lower current could also be swamped by the addition of a 75-Ω resistor in parallel with its input. (Note that common-base and common-gate amplifiers from Chapter 14 could also be used.) For the BJT : Rin ≅ rπ | BJT : IC =
β oVT
=
13.90 26
(a) Av = 10 20 = 20.0. Either a BJT or MOSFET can achieve the required gain. However, based upon the material in Chapter 13, an FET should be chosen since the input voltage of 0.25 V is 50 time larger than the permissible value for vbe (0.005 V) for the BJT. For the FET, a value of VGS – VTN = 1.25 V will satisfy the small-signal limit with vgs = 0.25 V. (The generalized commonemitter stage with emitter degeneration can also satisfy the requirements.) (b) The FET is also best for this case, since the amplifier will see input signals much greater than the 5-mV limit of the BJT. 13.91
Av ≅ −
(12) = −12 or 21.6 dB VDD =− VGS − VTN 1
13.92 15 7.5V vd = = 7.5V peak | 15dB → Av = −5.62 | vgs = = 1.34V | VGS − VTN ≥ 5(1.34)= 6.70V 2 5.62 Yes, it is possible although the required value of (VGS − VTN ) is getting rather large. 13.93
Av ≅
VDD VGS − VTN
|
9 ≥ 30 → VGS − VTN ≤ 0.300 V VGS − VTN
13.94
For VDS = ID =
VDD VDD , Av = − 2 VGS − VTN
| 30 =
15 VGS − VTN
| VGS − VTN = 0.5 V
2 1mA VGS − VTN ) = 125 µA | Q - point : (125 µA,7.5 V ) ( 2
13-28
13.95
vgs ≤ 0.2(VGS − VTN ) requires (VGS − VTN ) ≥
0.1 = 0.5V 0.2 Av = 35dB → Av = −56.2. Using the rule - of - thumb estimate to select VDD : Av = −
and VDD = 56.2(0.5V )= 28 V
VDD VGS − VTN
13.96
vgs ≤ 0.2(VGS − VTN ) requires (VGS − VTN ) ≥
0.5 = 2.5V 0.2 Av = 20dB → Av = −10. Using the rule - of - thumb estimate to select VDD : Av = −
and VDD = 10(2.5) = 25 V
VDD VGS − VTN
13.97
⎛ VDD ⎞ N ⎛ 10 ⎞ N We desire ⎜ ⎟ ≥ 1000 | ⎜ ⎟ ≥ 1000 ⎝ VGS − VTN ⎠ ⎝ VGS − VTN ⎠ For VGS − VTN = 1 V , N = 3 meets the requirements, but with no safety margin. For VGS − VTN = 0.75 V , N = 3 easily meets the requirements. 13.98 For the bias network : VEQ = 10V
Rout = 1kΩ 22.4kΩ 1+ 0.096(15) = 982 Ω 13.122 SPICE Results: Q-point: (2.39 µA, 3.69 V), Av = 29.7 dB, Rin = 1.49 kΩ, Rout = 977 Ω The results agree closely with the hand calculations in Prob. 13.121. The small disagreements arise from m atu us in 13.123 0 = 106 I B + 0.7 + 66(161.5kΩ)I B − 5
I B = 0.369 µA | IC = 65I B = 24.0 µA
VCE = 5 −1000IC −1615I E − (−5)= 3.66 V g m = 40(24.0µA) = 0.959mS | rπ =
13.137 The Q - point from problem 13.21 is (371µA, 2.72V).
(
)
(
2 VCC 8R | ε = 100% 2 L = 25 % VCC 2RL
)
vo ≤ g m vbe ro RC R3 = 40(371µA)(5mV ) ∞ 13kΩ 100kΩ = 0.854 V 13.138 The Q - point from Problem 13.23 is (82.2µA,6.04V ).
(
)
(
)
id ≤ 0.4I D = 32.9µA | vds ≤ 0.4I D ro RD R3 = 32.9µA ∞ 82kΩ 470kΩ = 2.30V 13.139 The Q - point from Problem 13.27 is (307µA,3.88V ).
(
)
(
)
id ≤ 0.4I D = 307µA | vo ≤ 0.4I D ro RL R3 = 307µA ∞ 24kΩ 470kΩ = 2.80V Checking the bias point : VR D = 307µA(24kΩ) = 7.37V | 2.80 < 7.37 & 2.80 < 3.88 -1
13.140 The Q - point from problem 13.17 is (1.78mA, 6.08V ).
(
)
(
)
ic ≤ 0.2IC = 0.356 mA | vc ≤ 0.2IC ro RC R3 = 0.356mA ∞ 6kΩ 100kΩ = 2.02V 13.141 The Q - point from problem 13.33 is (1.25 mA, 10.6 V ).
(
)
(
Neglecting ro ,
)
id ≤ 0.4I D = 0.500mA | vd ≤ 0.4I D RD R3 = 0.500mA 3.9kΩ 36kΩ = 1.76 V 13.142 The Q - point from problem 13.35 is (1.01 mA, 7.41 V ).
(
)
(
)
id ≤ 0.4I D = 0.404mA | vd ≤ 0.4I D RD R3 = 0.404mA 7.5kΩ 220kΩ = 2.93 V
13-40
13.143 VCE = 20 − 20000IC : Two points on the load line (0mA, 20V ) , (1mA, 0V )
At IB = 2µA, the maximum swing is approximately 2.5 V limited by VRC . For IB = 5µA,the maximum swing is approximately - 8.5 V limited by VCE . IC I B= 10 µA
1000 µA
I = 8 µA B
750 µA I = 6 µA B
500 µA
I B = 5 µA I = 4 µA B
250 µA 8.5 V
9V I = 2 µA B
V
0
CE
0
10 V
2.5 V
20 V
13-41
CHAPTER 14 14.1 (a) Common-collector Amplifier (npn) (emitter-follower) RI
Q1 R
vi
R
1
2
+
R
R
E
3
vo
-
(b) Not a useful circuit because the signal is injected into the drain of the transistor. M
As indicated above, the nearest 5% values would be 33 kΩ and 3.3 kΩ.
14.12 Rin = rπ = 250 kΩ | rπ =
βo gm
=
β oVT IC
| IC =
β oVT rπ
=
75(0.025V ) 250kΩ
= 7.50 µA
⎛ r ⎞ β R 75RL = −10 | RL = 33.3 kΩ → 33 kΩ Av = −g m RL ⎜ π ⎟ = − o L = − Rth + rπ 100Ω + 250kΩ ⎝ Rth + rπ ⎠ The closest 5% value is RL = 33 kΩ.
14.13
⎡ix − gm v gs⎤ ⎡ go −go ⎤⎡v d ⎤ ⎢ ⎥=⎢ ⎥⎢ ⎥ | v gs = −v s ⎣ +gm v gs ⎦ ⎣−go go + GS ⎦⎣ v s ⎦ ⎡ix ⎤ ⎡ go −(gm + go ) ⎤⎡v d ⎤ ⎥⎢ ⎥ ⎢ ⎥=⎢ ⎣0 ⎦ ⎣−go gm + go + GS ⎦⎣ v s ⎦
vd
gm vgs + vgs
r
o
ix R
R th
5
ix (gm + go + GS ) = ix ∆ go G S ⎛ g ⎛ v G ⎞ r ⎞ = d = RS ⎜1+ m + S ⎟ = RS ⎜1+ µ f + o ⎟ ix RS ⎠ ⎝ go go ⎠ ⎝
∆ = goGS | v d = (gm + go + GS ) Rout
Rout = ro + (1+ µ f )RS ≅ ro + µ f RS = ro (1+ gm RS )
(15 − 0.7 )V = 1.29 µA | I C = 129 µA | VCE = 30 − 39000 I C − 100000 I E 1MΩ + (100 + 1)100kΩ 100(0.025V ) = 19.4kΩ | r - no V specified - neglect Active region is correct. | r = IB =
π
129 µA
o
= 11.9 V
A
RL = 500kΩ 39kΩ = 36.2kΩ | Rin = RB rπ = 1MΩ 19.4kΩ = 19.0kΩ ⎛ Rin ⎞ 19.0kΩ ⎞ ⎟⎟ = 40(0.129mA)(36.2kΩ )⎛⎜ Av = − g m RL ⎜⎜ ⎟ = −182 ⎝ 500Ω + 19.0kΩ ⎠ ⎝ RI + Rin ⎠ Rout = RC ro = 39 kΩ ⎛ Rin ⎞ 0.005V 19.0kΩ ⎞ ⎛ ⎟⎟ = vi ⎜ vi ≤ = 5.13 mV vbe = vi ⎜⎜ ⎟ = 0.974vi k 0 . 974 + R R 500 Ω + 19 . 0 Ω ⎠ ⎝ I in ⎝ ⎠ Av ≅ −10(VCC + VEE ) = −10(30 ) = −300. | A closer estimate is - 40VR C = -40(5.03) = −201
14.15
62kΩ = 6.80V | REQ = 20kΩ 62kΩ = 15.1kΩ 20kΩ + 62kΩ (9 − 0.7 − 6.80)V = 4.82µA | I = 361 µA | V = 9 − 3900I − 8200I = 4.61 V IB = C EC E C 15.1kΩ + (75 + 1)3.9kΩ
VEQ = 9
Active region is correct. | rπ =
75(0.025V ) 361µA
= 5.19kΩ | VA not specified, choose ro = ∞
Rin = 15.1kΩ 5.19kΩ = 3.86 kΩ | Rout = ro 8.2kΩ = 8.2 kΩ | g m = 40IC = 12.6 mS RL = ro 8.2kΩ 100kΩ = 8.2kΩ 100kΩ = 7.58kΩ ⎛ Rin ⎞ ⎛ 3.86kΩ ⎞ Av = −g m RL ⎜ ⎟ = −(12.6mS )(7.58kΩ)⎜ ⎟ = −75.9 ⎝1kΩ + 3.86kΩ ⎠ ⎝ RI + Rin ⎠ Rout 8.2kΩ RB 15.1kΩ −β o ) = −75) = −4.23 Ai = ( ( RB + rπ Rout + R3 15.1kΩ + 5.19kΩ 8.2kΩ + 100kΩ vbe = vi
Rin 3.86kΩ 5.00mV = vi = 0.794v i | vi = = 6.30 mV 1kΩ + 3.86kΩ 0.794 RI + Rin
Av ≅ −10VCC = −10(9)= −90. | The voltage gain is slightly below the rule - of - thumb estimate.
Rin 368kΩ = vi = 0.997v i | VGS − VTN = 1kΩ + 368kΩ RI + Rin
vgs ≤ 0.2(VGS − VTN )→ vi ≤ 0.2
2(79.7µA) 250µA/V 2
= 0.798V
0.798V VDD 15 = 0.160 V | Av ≅ − =− = −18.8 0.997 0.798 VGS − VTN
VDD . We have VR L = 79.7µA(75kΩ)= 5.98V = 0.399VDD 2 The estimate also doesn't account for the presence of R3 . The rule - of - thumb estimate assumes VR L =
(12 − 0.7)V = 14.9µA | I = 1.19 mA | V = 24 − 9100I = 13.2 V 20kΩ + (80 + 1)9.1kΩ 80(0.025V ) (100 + 13.2)V = 95.1kΩ = 1.68kΩ | r = Active region is correct. | r = IB =
Rin = RB rπ + (β o + 1)RL = 50.0kΩ 3.03kΩ + (126)3.71kΩ = 45.2 kΩ Av = +
(β + 1)R + (β + 1)R o
rπ
L
o
⎛ R ⎞ ⎛ ⎞ 126(3.71kΩ) 50.0kΩ in ⎜ ⎟= ⎜ ⎟ = 0.984 R + R 500Ω + 50.0kΩ 3.03kΩ + 126 3.71kΩ ⎝ ⎠ ⎝ ⎠ ( ) I in L
⎞ ⎛ ⎤ ⎛ R ⎞⎛ ⎞⎡ rπ 3.03kΩ 50.0kΩ in ⎟=⎜ ⎢ ⎥ = 6.34x103 vi vbe = vi ⎜ ⎟⎜⎜ ⎟ ⎟ R + R 500Ω + 50.0kΩ r + β + 1 R 3.03kΩ + 126 3.71kΩ ⎠⎢⎣ ⎝ I ( o ) L⎠ ⎝ ( )⎥⎦ in ⎠⎝ π vi ≤
2 5x10−4 5 −1.5) = 3.06 mA | VDS = 5 − (−5)= 10V - Pinchoff region ( 2
(
)
[
]
operation is correct. | g m = 2 5x10−4 (3.06mA) 1+ 0.02(10) = 1.92mS 1 + 10 V = 19.6 kΩ − Cannot neglect! | RL = 19.6kΩ 100kΩ = 16.4kΩ ro = 0.02 3.06 mA 1 Rin = RG = 1 MΩ | Rout = ro = 507 Ω gm ⎛ 1.92mS (16.4kΩ) ⎞ 1MΩ Rin ⎛ g m RL ⎞ ⎟ = 0.960 ⎜ Av = + = + ⎜ ⎟ 10kΩ + 1MΩ ⎜⎝1+ 1.92mS (16.4kΩ)⎟⎠ RI + Rin ⎝ 1+ g m RL ⎠ ⎤ ⎛ ⎞⎡ ⎛ Rin ⎞⎛ 106 Ω 1 ⎞ 1 ⎥ = 0.0305v i ⎢ v gs = v i ⎜ ⎟ ⎟⎜ ⎟ = vi⎜ 4 6 ⎝ RI + Rin ⎠⎝ 1+ g m RL ⎠ ⎝ 10 Ω + 10 Ω ⎠⎢⎣1+ 1.92mS (16.4kΩ)⎥⎦ vi ≤ VDS
0.2(5 −1.5)
= 23.0 V But, vDS must exceed vGS − VTN ≅ VGS − VTN = 4V for pinchoff. 0.0305 = 10 − vo = 10 − 0.970vi ≥ 4 → vi ≤ 6.19 V − Limited by the Q - point voltages
14.25
(9 − 0.7)V = 187 nA | I = 18.7 µA | V 1MΩ + (100 + 1)430kΩ 100(0.025V ) Active region is correct. | r = = 134kΩ | IB =
C
π
CE
18.7µA
= 18 − 430000I E = 9.89 V
ro =
(60 + 9.89)V = 3.74 MΩ - neglected 18.7µA
In the ac model, R1 appears in parallel with rπ . The circuit appears to be using a transistor with rπ' = 500kΩ rπ = 106kΩ
14.26 vi ≤ 0.005(1+ g m RL ) | RL = RE R3 ≅ RE ⎛ I R ⎞ vi ≤ 0.005(1+ g m RL ) = 0.005(1+ g m RE ) = 0.005⎜1+ C E ⎟ VT ⎠ ⎝ ⎛ ⎛ I R ⎞ I R ⎞ vi ≤ 0.005⎜1+ α F E E ⎟ ≅ 0.005⎜1+ E E ⎟ VT ⎠ VT ⎠ ⎝ ⎝ ⎛ VR ⎞ ⎛ VR E ⎞ vi ≤ 0.005⎜1+ E ⎟ = 0.005⎜1+ ⎟ = 0.005 + 0.2VR E VT ⎠ ⎝ ⎝ 0.025 ⎠
14.27 β o = g mrπ = 3.54mS (1MΩ) = 3540 | RL = 2kΩ 100kΩ = 1.96kΩ
14.29 vbe = vi − vo = (1− Av )vi | 0.005 ≤ (1− Av )7.5 → Av =
vo 7.5 − 0.005 ≥ = 0.999333 vi 7.5
1 500RE 1 | RL = RE 500Ω = | Av = ⎛ V 500 + RE 500 + RE ⎞ V 1+ T 1+ T ⎜ ⎟ I E RL I E RE ⎝ 500 ⎠ 1 V ⎛ 500 + RE ⎞ −4 ≥ 0.999333 → T ⎜ ⎟ ≤ 6.67x10 ⎛ ⎞ I R 500 V 500 + RE ⎠ E E ⎝ 1+ T ⎜ ⎟ I E RE ⎝ 500 ⎠ From Prob. 14.28, Av =
500I E RE 0.025V ≥ = 37.5V | VCC ≥ I E RE + 0.7 + 7.5 500 + RE 6.67x10−4 Some design possibilities are listed in the table below.
RE
IE
VCC
VCC IE
100 Ω
450 mA
53 V
24 W
250 Ω
225 mA
64 V
16 W
360 Ω
179mA
73V
13 W
500 Ω
150 mA
83 V
12 W
750 Ω
125 mA
102 V
13 W
1000 Ω
113mA
120 V
14 W
2000 Ω
93.8 mA
196 V
18 W
Using a result near the minimum-power case in the table: RE = 510 Ω E= 149 mA and VCC = 85 V. 149mA For β F = 50 : I B ≅ = 2.92 mA | Set I R1 = 5I B = 14.6mA ≅ 15mA 51 V + VBE 149mA(510Ω)+ 0.7 R1 = E = = 5.07kΩ → 5.1 kΩ | I R 2 = I R1 + I B ≅ 18mA I R1 15mA 85 − VBE − VBE 8.3V = = 462Ω → 470 Ω I R2 18mA It is obviously very difficult to achieve the required level of linearity! R2 =
14.32 The voltage gain is approximately 0. The signal is injected into the collector and taken out of the emitter. This is not a useful amplifier circuit.
⎛ RS ⎞ 0.504mS (14.4kΩ) ⎛ 3.9kΩ ⎞ ⎜ ⎟= ⎜ ⎟ = 4.12 1+ g m RI RS ⎝ RI + RS ⎠ 1+ 0.504mS (0.796kΩ)⎝1kΩ + 3.9kΩ ⎠ g m RL
(
)
Ai = Av
1kΩ + 1.32kΩ RI + Rin = 4.12 = 0.187 R3 51kΩ
vgs = vi
1.32kΩ 1.32kΩ ≤ 0.2(VGS + 2) | v i ≤ 0.2(−0.992 + 2)→ vi ≤ 0.354 V 1kΩ + 1.32kΩ 1kΩ + 1.32kΩ
14.36
(2x10 )(V = −4
ID
GS
+ 1) | 2
2 15 + VGS = 10−4 (VGS + 1) → VGS = −2.363V 68kΩ
2 15 + VGS ID = = 186µA | VDS = − 30 − (68kΩ + 43kΩ)I D = −9.35V | 68kΩ 2(186µA) 1 Pinchoff region is correct. | g m = = 0.274mS | Rin = 68kΩ = 3.46kΩ 2.36 −1 gm
[
]
Rout ≅ RD = 43kΩ | RL = 43kΩ 200kΩ = 35.4kΩ Rin 3.46kΩ g m RL = (0.274mS )(35.4kΩ)= 9.05 RI + Rin 0.250kΩ + 3.46kΩ ⎛ 3.71kΩ ⎞ R + Rin 3.46kΩ Ai = Av I = 9.05⎜ ≤ 0.2(VSG −1) ⎟ = 0.168 | vgs = vi R3 0.250kΩ + 3.46kΩ ⎝ 200kΩ ⎠ 3.46kΩ vi ≤ 0.2(2.36 −1)→ v i ≤ 0.292 V 0.250kΩ + 3.46kΩ Av =
⎛V + V ⎞ ⎛ 50 + 10.7 ⎞ Rout = (β o + 1)ro = (β o + 1) ⎜ A CE ⎟ = 126 ⎜ ⎟ = 154 MΩ ⎝ 49.6µA ⎠ ⎝ IC ⎠
14.43 43
Rin = 350Ω | Av = 10 20 = 141 | Low Rin , large gain A common - base amplifier can achieve these speocfications. 1 1 → IC ≅ = 71.4 µA gm 40(350)
Rin ≅
A common emitter amplifier operating at a higher current is an alternate choice. 100 Rin ≅ rπ → IC ≅ = 7.14 mA 40(350) For both cases, Av ≅ 10VCC → VCC = 14 V 14.44 Rin = 0.3 MΩ | Av = 10
46 20
= 200 | Fairly large Rin , large gain
A common - emitter amplifier operating at a low current can achieve both a large gain and input resistance. Av ≅ 20VCC → VCC = 10V Achieving this gain with an FET is much more difficult : Av ≅
VDD V = DD → VDD ≅ 50V which is unreasonably large. VGS −V TN 0.25V
Rin = 10 MΩ | Av = 10 20 = 20 | Large Rin , moderate gain These requirements are readily met by a common - source amplifier. VDD 15V = = 30. For example, Av ≅ VGS −V TN 0.5V A common - emitter stage operating at a low collector current with ⎛ ⎞ 10 MΩ an unbypassed emitter resistor ⎜ R E ≅ = 100kΩ⎟is a second possibility, 100 ⎝ ⎠ but the circuit will require careful design.
14.46 58 20
Rin = 50kΩ | Av = 10 = 792 | A bipolar transistor would be required for such a large gain. However, this is a large fraction of the BJT amplification factor [i. e. (40/V)(75V) = 3000] and will be very difficult to achieve with the information thus far (the active load discussed later is a possibility). Using our rule - of - thumb for the common - emitter amplifier, Av ≅ 10VCC → VCC = 80 V which is too large. Thus, it is not possible is the best answer. 14.47 An inverting amplifier with a gain of 40 dB is most easily achieved with a common - emitter stage : Av ≅ 10VCC → VCC = 10 V. The input resistance can be achieved by shunting the input with a 5 - Ω resistor. Setting rπ = 5 Ω would require IC ≅
100(0.025V )
= 0.5A and would 5Ω waste a large amount of power to achieve the required input resistance. It would be better to operate the transistor at a much lower current and "swamp" the input resistance by shunting the input with a 5 - Ω resistor
14.48 A non - inverting amplifier with a gain of 20 and an input resistance of 5 kΩ should be readily achievable with either a common - base or common - gate amplifier with proper choice of operating point. The gain of 10 is easily achieved with either the VDD 1 or Av ≅ 10VCC . Rin ≅ = 5 kΩ is within FET or BJT design estimate : Av ≅ gm VGS − VTN easy reach of either device. The gain and input resistance can also be easily met with either a common - emitter, or common - source stage with a resistor shunt at the input.
For an emitter - follower, R in ≅ (β o + 1)RL ≅ 101(20kΩ) = 2.02 MΩ. So an BJT
cannot meet the input resistance requirement. A source follower provides a gain of approximately 1 and can easily achieve the required input resistance.
14.50 A gain of 0.97 and an input resistance of 400kΩ should be achievable with g m RL = 0.97 either a source - follower or an emitter - follower. For the FET, Av ≅ 1+ g m RL requires g m RL = 33.3 :
2I D RL = 33.3 → I D RL = 8.3V for a design with VGS − VTN = 0.5V. VGS − VTN
The BJT can achieve the required gain with a much lower power supply and
can still meet the Rin requirement : Rin ≅ β o RL ≅ 100(5kΩ) = 500kΩ. Av ≅
g m RL = 0.97 | g m RL = 33.3 → IC RE = 33.3(0.025)= 0.833 V. 1+ g m RL
The requirements can be met with careful bias circuit design and specification of a BJT with minimum current gain of at least 100.
14.51 66
Av = 10 20 = 2,000. This value of voltage gain approaches the amplification factor
of the BJTs : Av ≤ µ f = 40VA = 40(75)= 3000. Such a large gain
requirement cannot be met with single - transistor BJT amplifiers using the resistive loaded amplifiers in this chapter (Remember the 10VCC limit). FETs typically have much lower values of µf and are at an even worse disadvantage. None of the single - transistor amplifier configurations can meet the gain requirements.
14.52 Such a large output resistance will require either a CE or CB stage or a CS or CG stage. For a BJT, Rout ≤ β oro
β oVA
100(75V )
= 7.5µA using typical 109 Ω values for β o and VA . We need to also see how much voltage is required. IC
= 109 Ω or IC =
75 We also need ro (1+ g m RE )> 109 Ω or 40(IC RE ) > 109 Ω → IC RE > 2.5 V whihc is reasonable. 7.5µA For a MOSFET, Rout = ro (1+ g m RS ) ≅ g mro RS = RS =
109 (0.01/V )(0.25V ) 2
= 1.25 MΩ
2RS = 109 Ω λ(VGS − VTN )
For typical values,
Using this value to estimate the required voltage,
2 2Kn ⎛ RS ⎞ 2(0.001)⎛1.25x106 ⎞ RS 9 g mro RS = 2Kn I D = 10 Ω → I D = 18 ⎜ ⎟ = ⎜ ⎟ = 31.3µA and λI D 10 ⎝ λ ⎠ 1018 ⎝ 0.01 ⎠ 2
VR S = 39 V which is getting large. So the BJT appears to be the best choice.
14.53 Rout =
Rth + rπ βo + 1
| Assuming Rth ≅ RI and rπ = 0, Rout ≥
RI 250 = = 1.66 Ω β o + 1 151
14.54 Rin = rπ + (β o + 1)RE ≅ rπ + β o RE = rπ (1+ g m RE ) | rπ' = rπ (1+ g m RE ) g m' = ro' =
βo βo βo ic gm = ≅ = = vi rπ + (β o + 1)RE rπ + β o RE rπ (1+ g m RE ) 1+ g m RE
ic vc
⎛ βR ⎞ ⎛ β R ⎞ = ro⎜1+ o E ⎟ ≅ ro⎜1+ o E ⎟ = ro (1+ g m RE ) for rπ >> RE rπ ⎠ ⎝ rπ + RE ⎠ ⎝ v i =0 ⎛
⎛ gm ⎞ gm ⎞ ' ' ' ⎟rπ (1+ g m RE ) = β o | µ f = g mro = ⎜ ⎟ro (1+ g m RE ) = µ f ⎝1+ g m RE ⎠ ⎝1+ g m RE ⎠
β o' = g m' rπ' = ⎜
14.55 *Problem 14.55 - Common-Emitter Amplifier 5mV VCC 6 0 DC 9 VEE 4 0 DC -9 VS 1 0 SIN(0 0.005 1K) C1 1 2 1U RB 2 0 10K RC 6 5 3.6K RE 3 4 2K C2 3 0 50U C3 5 7 1U
14.56 *Problem 14.56 - Output Resistance VCC 2 0 DC 10 IB1 0 1 DC 10U Q1 2 1 0 NBJT IB2 0 3 DC 10U RE 4 0 10K Q2 2 3 4 NBJT .OP .DC VCC 10 20 .025 .MODEL NBJT NPN IS=1E-16 BF=60 VA=20 .PRINT DC IC(Q1) IC(Q2) .PROBE IC(Q1) IC(Q2) .END Results: A small value of Early voltage has been used deliberately to accentuate the results. Note that the transistors have significantly different values of F because of the collectoremitter voltage differences and low value of VA. NAME Q1 Q2 MODEL NBJT NBJT IB 1.00E-05 1.00E-05 IC 8.77E-04 6.72E-04 VBE 7.61E-01 7.61E-01 VBC -9.24E+00 -2.41E+00 VCE 1.00E+01 3.18E+00 BETADC 8.77E+01 6.72E+01 GM 3.39E-02 2.60E-02 RPI 2.59E+03 2.59E+03 RO 3.33E+04 3.33E+04 From SPICE : Rout1 =
(20 −10)
V (20 −10) V = 43.5 kΩ = 34.1 kΩ | Rout 2 = (1.17 − 0.877) mA (903 − 673) µA
For circuit 1: Rout1 = ro1 = 33.3 kΩ ⎛ ⎞ β o RE For circuit 2 : Rout 2 = ro2⎜1+ ⎟ + (Rth + rπ ) RE (See Eq. 14.28) ⎝ Rth + rπ + RE ⎠ But Rth = ∞ → Rout 2 = ro2 + RE = 33.3kΩ + 10kΩ = 43.3 kΩ
100(952Ω) β o RL =− = −0.984 rπ + (β o + 1)RE 645Ω + 101(952Ω)
(β + 1)R + (β + 1)R o
rπ
E
o
E
=
101(952Ω)
645Ω + 101(952Ω)
= 0.993
The small - signal requirement limits the output signal to : vbe = vi − vo2 = vi (1− 0.993) = 0.007vi | v i ≤ vo1 ≤ 0.984(0.714V ) = 0.703V
0.005 = 0.714V 0.007
We also need to check VCB : VC = 5 − 3.87mA(1kΩ)= 1.13V and VB = −10 4 I B = −0.387V.
The total collector - base voltage of the transistor is therefore : VCB = 1.52V − 0.984v i − vi . We require VCB ≥ 0 for forward - active region operation. Therefore : vi ≤ 0.766 V. The small - signal limit is the most restrictive.
⎛ R ⎞ 0.201mS (6.65kΩ) ⎛ 51kΩ ⎞ S ⎜ ⎟= ⎜ ⎟ = 1.10 1+ g m RI RS ⎝ RI + RS ⎠ 1+ 0.201mS (0.981kΩ)⎝1kΩ + 51kΩ ⎠ g m RL
(
)
(b) SPICE Results: Q-point: (32.9 µA, 12.7 V), Av = +1.10, Rin = 4.50 kΩ, Rout= 19.8 kΩ 14.77 The power supply should be +16 V. (a ) Assume Active Region operation. Since there is no negative feedback (RS = 0),
we should include the effect of channel - length modulation. VGS = 0 2 4x10−4 −5) (1+ 0.02VDS ) and VDS = 16 −1800I D → I D = 5.59 mA ( 2 = 16 −1800I D = 5.93 V > 5 V - Active region is correct.
g m = 2 4x10−4 (5.59mA) 1+ 0.02(5.93) = 2.24mS | ro =
(
)
Rin = 10.0 MΩ | Rout = RD ro = 1.52 kΩ (b) SPICE Results: Q-point: (5.59 mA, -5.93V), Av = -3.27, Rin = 10.0 MΩ, Rout= 1.52 kΩ 14.78
(10 − 0.7)V = 14.0µA | I = 1.12 mA | V = 20 − 7800I = 11.3 V 33kΩ + (80 + 1)7.8kΩ 80(0.025V ) (100 + 11.3)V = 99.4kΩ = 1.79kΩ | r = Active region is correct. | r = IB =
14.86 (a) Use C2 to set the lower cutoff frequency to 1 kHz. C1 and C3 remain negligible at 1 kHz.
C2 = 0.056 µF, C1 = 1800 pF, C3 = 0.015 µF (b) SPICE Results: fL = 925 Hz 14.87 (a ) Use C3 to set the lower cutoff frequency to 2 kHz. C1 remains negligible at 2 kHz.
C1 = 8200 pF, C3 = 820 pF
(b) Use C to set the lower cutoff frequency to 1 kHz. C 1
2
and C3 remain negligible at 1 kHz.
C1 = 0.042 µF, C2 = 1800 pF, C3 = 0.015 µF (c) SPICE Results: For (a) fL = 1.96 kHz. For (b) fL = 1.02 kHz 14.88 Av =
g m RL 2I D ≥ 0.95 → g m RL ≥ 19 | g m = 2Kn I D | VGS − VTN = = 0.5V 1+ g m RL Kn
(0.5) (0.03) = 3.75mA = 2
ID
2
| RL ≥
19 2(0.03)(0.00375)
= 1.27kΩ
RL = RS 3kΩ → RS ≥ 2.19kΩ | VSS = VGS + (3.75mA)RS | Possible designs : 2.4kΩ, 11.5V ; 2.7kΩ, 12.6V ; 3.0kΩ, 13.75V - Making a choice which uses a nearly minimum value of supply voltage gives : VSS = 12 V , RS = 2.4 kΩ.
For a common - emitter amplifier with RE = 0, Rin ≅ rπ =
β oVT IC
| IC =
100(0.025V ) 75Ω
= 33.3 mA
14.90 Using Eqn. 14.73 : 50 = 50 = g m RL
RE 4.3V → RE = 8.65kΩ | IC ≅ = 497µA RE 1+ 40(4.3)
2(50) g R Rin | Assuming RI = 50Ω, 50 = m L → RL = = 5.03kΩ RI + Rin 2 40(497µA)
RL = RC 100kΩ → RC = 5.30kΩ | VEC = 5 + 0.7 − IC RC = 3.07V - Active region is ok. 1
= 3.18nF → C1 = 0.033 µF
C1 >>
2π (500kHz)(50Ω + 50Ω)
C2 >>
1 = 3.02 pF → C2 = 33 pF 2π (500kHz)(105kΩ)
14.91 The base voltage should remain half way between the positive and negative power supply voltages. If VEE = +10V and VCC = 0V, then VB should = 5 V which can be obtained using a resistive voltage divider from the +10V supply. We now have the standard four-resistor bias circuit. The base current is 327 µA/80 = 4.08 µA. C1
C2
75 Ω v
+ 13 k Ω
8.2 k Ω
RE
RC 100 k Ω
S
120 k Ω + 10 V
R1
110 k Ω
CB
v O
-
R2
Setting the current in R1 to 10I B = 40µA, R1 =
5V = 125kΩ →120kΩ. 40µA
5V = 114kΩ →110kΩ. 44µA Note that the base terminal must now be bypassed with a capacitor. The current in R2 = 11I B = 44µA, and R 2 =
14.95 This analysis assumes that the source and load resistors are fixed, and that only ⎛ Rin ⎞ the amplifier parameters are changing. Av = g m RL ⎜ ⎟ ⎝ RI + Rin ⎠ 1 g R 1 ≅ | Av ≅ m L Since RE >> 75Ω, RE RI ≅ 75Ω and Rin ≅ RE 1+ g m RI gm gm
To achieve Avmax , RL → RLmax , g m → g mmax which requires
(5.25 − 0.7)V = 364µA 13kΩ(0.95)
IC → ICmax = 0.988
g m = 40(364µA) = 14.6mS | Avmax =
| RLmax = 8.2kΩ(1.05)100kΩ = 7.93kΩ
14.6mS (7.93kΩ) 1+ 0.0146(75)
= 55.3
min min which requires To achieve A min v , R L → RL , g m → g m
IC → ICmin = 0.988
(4.75 − 0.7)V = 293µA 13kΩ(1.05)
g m = 40(293µA) = 11.7mS | Avmin =
| RLmin = 8.2kΩ(0.95)100kΩ = 7.23kΩ
11.7mS (7.23kΩ) 1+ 0.0117(75)
= 45.1 | 45.1 ≤ Av ≤ 55.3
The range is only slightly larger than that observed in the Monte Carlo analysis in Table 14.15. 14.96 *Problem 14.96 - Common-Base Amplifier - Monte Carlo Analysis *Generate Voltage Sources with 5% Tolerances IEE 0 8 DC 5 REE 8 0 RTOL 1 EEE 6 0 8 0 1 * ICC 0 9 DC 5 RCC 9 0 RTOL 1 ECC 7 0 9 0 -1 * VS 1 0 AC 1 RS 1 2 75 C1 2 3 47U RE 3 6 RTOL 13K Q1 4 0 3 PBJT RC 4 7 RTOL 8.2K C2 4 5 4.7U R3 5 0 100K .OP .AC LIN 1 10KHZ 10KHZ .PRINT AC VM(5) VP(5) .MODEL PBJT PNP (BF=80 DEV 25%) (VA = 60 DEV 33.33%)
.MODEL RTOL RES (R=1 DEV 5%) .MC 1000 AC VM(5) YMAX .END Results: Mean value Av = 47.5; 3σ limits: 42.5 ≤ Av ≤ 52.5. However, the worst-case values observed in the analysis are Avmin = 43.2 and Avmax = 51.9. The mean is 5% lower than the design value. The width of the distribution is approximately the same as that in Table 14.15. 14.97 (a ) This analysis assumes that the source and load resistors are fixed, and that only
the amplifier parameters are changing. Av = Rth = RE RI and
RE = RI + RE
Since R E >> RI , Rth and
g m RL ⎛ RE ⎞ ⎜ ⎟ 1+ g m Rth ⎝ RI + RE ⎠
1 where RE = 13.3kΩ and RI = 75Ω RI 1+ RE
RE are essentially constant. To achieve Avmax , RL → RLmax , g m → g mmax RI + RE
To achieve Avmin , RL → RLmin , g m → g mmin which requires IC → ICmin = 0.988
(4.90 − 0.7)V = 309µA 13.3kΩ(1.01)
| RLmin = 8.25kΩ(0.99)100kΩ = 7.55kΩ
12.4mS (7.55kΩ)⎡ 13.3(1.01) ⎤ ⎢ ⎥ = 48.2 1+ 0.0124(75) ⎢⎣ 75 + 13.3(1.01)⎥⎦ (b) Using a Spreadsheet similar to Table 14.16: Mean value Av = 49.6; 3σ limits: 48.2 ≤ Av ≤ 50.9. The worst-case values observed in the analysis are Avmin = 48.4 and Avmax = 50.8. g m = 40(309µA) = 12.4mS | Avmax =
14.98 *Problem 14.98 - Common-Base Amplifier - Monte Carlo Analysis *Generate Voltage Sources with 2% Tolerances IEE 0 8 DC 5 REE 8 0 RTOL 1 EEE 6 0 8 0 1 * ICC 0 9 DC 5 RCC 9 0 RTOL 1 ECC 7 0 9 0 -1
* VS 1 0 AC 1 RS 1 2 75 C1 2 3 100U RE 3 6 RR 13.3K Q1 4 0 3 PBJT RC 4 7 RR 8.25K C2 4 5 1U R3 5 0 100K .OP .AC LIN 1 10KHZ 10KHZ .PRINT AC VM(5) VP(5) IM(VS) IP(VS) .MODEL PBJT PNP (BF=80 DEV 25%) (VA = 60 DEV 33.33%) .MODEL RTOL RES (R=1 DEV 2%) .MODEL RR RES (R=1 DEV 1%) .MC 1000 AC VM(5) YMAX *.MC 1000 AC IM(VS) YMAX .END Results: Mean value: Av = 47.2; 3σ limits: 45.7 ≤ Av ≤ 48.5 Mean value: Rin = 83.4 Ω; 3σ limits: 79.5 Ω ≤ Av ≤ 87.6 Ω 14.99 Rin = RE
RE 1 RE = = = g m 1+ g m RE 1+ 40IC RE
I E RE = 2.5 − 0.7 = 1.8V | 75 =
RE RE = 80 1+ 39.5I E RE 1+ 40 I E RE 81
RE → RE = 5.41kΩ 1+ 39.5(1.8)
80 1.8V = 329µA | Rth = 75Ω 5.41kΩ = 74.0Ω | g m = 40(329µA)= 13.2mS 81 5.41kΩ g m RL ⎛ RE ⎞ Av = ⎜ ⎟ → RL = 7.59kΩ 1+ g m Rth ⎝ RI + RE ⎠
IC =
7.59kΩ = RC 100kΩ → RC = 8.21kΩ | VC = −2.5V + IC RC = +0.201V | Oops! We are violating our definition of the forward - active region. If we use the nearest 5% values, RE = 5.6kΩ and RC = 8.2kΩ, IC = 318µA and VC = +0.108V. The transistor is just entering saturation.
The Q - points and small - signal parameter values have already been found in the text. ⎛ ⎞ Rin The bypass capacitors do not affect Rin : Rin = RG = 1 MΩ | Av = ⎜ ⎟ Avt1 Avt 2 Avt 3 ⎝ 10kΩ + Rin ⎠
Rin Avt1 Avt 2 | Rin = 113kΩ (rπ 1 + (β o1 + 1)R5 ) = 113kΩ (10.8kΩ + (101)20kΩ) = 107kΩ RI + Rin 107kΩ Av = (−0.830)(−0.822) = +0.670 2kΩ + 107kΩ The voltage gain is completely lost. | Rout ≅ 20kΩ Av =
R1S = RI + Rin = 45.3kΩ R2S = R3 + Rout = 24.0kΩ R3S ≅ RC = 2kΩ ⎤ 1 ⎡ 1 1 ⎢ −5 ⎥ = 0.492 Hz SPICE result : f L = 0.39Hz + fL ≅ 2π ⎢⎣10 (45.3kΩ) 47x10−6 (24.0kΩ)⎥⎦ Note that C3 is not in the signal path and doesn't contribute to f L .
14.115 Use C3 = 2.2 µF (10 − 0.7)V = 1.43 µA | I = 114 µA | V = 20 − 39000I − 68000I = 7.71 V IB = C CE C E 1MΩ + (80 + 1)68kΩ Active region is correct. | rπ =
81(0.025V ) 114µA
= 17.8 kΩ | ro =
75 + 7.71 = 726 kΩ 114µA
RL = 500kΩ 39kΩ 726kΩ = 34.5kΩ | Rin = RB rπ = 1MΩ 17.8kΩ = 17.5 kΩ ⎛ Rin ⎞ ⎛ ⎞ 17.5kΩ Av = −g m RL ⎜ ⎟ = 40(0.114mA)(34.5kΩ)⎜ ⎟ = −153 ⎝ 500Ω + 17.5kΩ ⎠ ⎝ RI + Rin ⎠ Rout = RC ro = 39kΩ 726kΩ = 37.0 kΩ R1S = RI + Rin = 18.0kΩ R3S = Rout + R3 = 537kΩ R2S = RE
Assume Active Region operation. Since there is no negative feedback (RS = 0), we should include the effect of channel - length modulation. VGS = 0 2 4x10−4 −5) (1+ 0.02VDS ) and VDS = 16 −1800I D → I D = 5.59 mA ( 2 = 16 −1800I D = 5.93 V > 5 V - Active region is correct.
ID = VDS
50 + 5.93 = 10.0kΩ Rin = 10.0 MΩ | Rout = RD ro = 1.52 kΩ 5.59x10−3 R1S = RI + Rin = 10.0 MΩ R2 S = Rout + R3 = 37.5kΩ ⎤ 1 1 ⎡ 1 ⎢ ⎥ = 0.497 Hz SPICE result : f L = 0.427 Hz + fL ≅ 2π ⎢⎣2.2µF (10.0 MΩ) 10µF (37.5kΩ)⎥⎦
ro =
14.122 Use C1 = C2 = C3 = 1 µF 0.05 2 (VGS + 2) and VGS = −1800ID M1: Assume saturation: ID = 2 2 0.05 VGS + 2) or 45VGS2 + 181VGS + 180 = 0 VGS = −1800 ( 2 VGS = −2.22V ,−1.80V | VGS = −1.80 V and I D = 1 mA
VDS = 20 −15000(0.001)−1800(0.001) = 3.2 V > VGS − VTN 0.05 2 (VGS + 2) and VGS = −2500ID M2: Assume saturation: ID = 2 2 0.05 VGS + 2) or 62.5VGS2 + 251VGS + 250 = 0 VGS = −2500 ( 2 VGS = −1.83 V and I D = 0.723 mA VDS = 20 − 2500(0.723mA) = 18.2 V > VGS − VTN
(
)
g m1 = 2(0.05)(0.001) = 10.0mS | g m2 = 2(0.05) 7.23x10−4 = 8.50mS R1S = Rin = 1800
1 = 1800 100 = 94.7Ω | R2 S = 15kΩ + 1MΩ = 1.02 MΩ g m1
1 = 2500 118 = 113Ω | R3 S = 10kΩ + Rout = 10.1kΩ g m2 ⎤ 1 ⎡ 1 1 1 ⎢ ⎥ = 1.42 kHz SPICE result : f L = 1.68 kHz fL ≅ + + 2π ⎢⎣1µF (113Ω) 1µF (1.02 MΩ) 1µF (10.1kΩ)⎥⎦
VCE = 18 − 105 IC − (−0.7)= 0.92 V | Q - point : (182 µA, 0.92 V )
Note that RC is quite large and the common - mode input range is poor. More realistic choices might be 47 kΩ or 51 kΩ 100 (b) g m = 40 IC = 7.28 mS | rπ = g = 13.7 kΩ | Add = −g m RC = −7.28mS (100kΩ)= −728 m Acc = −
100(100 kΩ) β o RC =− = −1.05 rπ + (β o + 1)2 REE 13.7 kΩ + 101(94 kΩ)
For differential output : CMRR =
−33.7 =∞ 0
−728 For single - ended output : CMRR = 2 = 346, a paltry 50.8 dB! −1.05 Rid = 2rπ = 27.4 kΩ | Ric =
vic = 5 V , vC1 = vC 2 = 7.03 + Accvic = 7.03 − 0.439(5) = 4.84 V
Note that the BJT's are just beyond the edge of saturation! 1 β F ⎛ 5V − VBE − (−12V )⎞ 1 ⎛ 100 ⎞⎛17V − 0.7V ⎞ ⎟= ⎜ b I = α I = ( ) C F E 2 β + 1⎜⎜ ⎟ 2 ⎝ 101⎟⎠⎜⎝ 2.7 x105 ⎟⎠ = 29.9 µA R F EE ⎝ ⎠ VC1 = VC 2 = 12 − 2.4 x105 IC = 4.82 V | Part (a) has a small error of 0.02 mV
(c) The common - mode signal voltage applied to the base - emitter junction is vbe = vic
A common - mode input voltage of 5 volts exceeds the small - signal limit. 15.6 We should first check the feasibility of the design using the Rule- of - Thumb estimates similar to
those developed in Chapter 13 (Eq. (13.55)). The required Add = 794 (58 db).
(This sounds fairly large - a significant fraction of the BJT amplification factor µf .) Even assuming we choose to drop all of the positive power supply voltage across RC
(which provides no common - mode input range) : Add = g m RC = 40IC RL ≤ 40VCC = 40(9)= 360. Thus, a gain of 794 is not feasible with this topology!
15.7 We should first check the feasibility of the design using the Rule- of - Thumb estimates
similar to those developed in Chapter 13 (Eq. (13.55)). The required Add = 200 (46 db).
For symmetric supplies, Add ≅ 10(VCC + VEE ) = 240. Thus, a gain of 200 appears feasible. Rid = 2rπ = 1MΩ → rπ = 500kΩ | IC = IE =
IC
αF
=
β oVT rπ
=
100(0.025V ) 500kΩ
= 5.00 µA
101 V − VBE (12 − 0.7)V IC = 5.05µA | REE = EE = = 1.12 MΩ 100 2I E 2(5.05µA)
Add = −g m RC = −200 (46dB) | RC =
200 200 = = 1.00 MΩ g m 40 5x10−6
(
)
Checking the collector voltage : VC = 12 − (990kΩ)(5µA)= 7V | Picking the closest 5% valuesfrom the table in the Appendix : REE = 1.1 MΩ and RC = 1 MΩ are the final design
values. These values give IC = 5.09µA and Add = −204 (46.2dB).
Simulation results from B2SPICE. The amplifier is over driven causing the output to be distorted. Using the Fourier analysis capability of SPICE, THD = 16.9% 15.14 15-8
I EE 80 ⎛10µA ⎞ 5 = ⎜ ⎟ = 4.94µA | VEC = 0.7 − −3 + 3.9x10 IC = 1.77V 81 ⎝ 2 ⎠ 2
(
)
Q - points : (4.94µA, 1.77V ) | g m = 40IC = 0.198mS | rπ = Add = −g m RC = −0.198mS (390kΩ)= −77.2 Acc = −
80 = 404kΩ gm
80(390kΩ) β o RC =− = −0.0385 rπ + (β o + 1)2REE 404kΩ + 81(10 MΩ)
Rid = 2rπ = 808kΩ | Ric = Note that Ric is similar to
rπ + (β o + 1)2REE 2
βoro 2
For example, if VA were 80V ,
=
808kΩ + 81(10 MΩ) 2
= 405 MΩ
so that Ric = 405 MΩ will not be fully acheived.
β oro 2
≅
80 ⎛ 80 ⎞ ⎟ = 648 MΩ ⎜ 2 ⎝ 4.94µA ⎠
For a differential output : Adm = Add = −77.2 | Acm = 0 | CMRR = ∞ For a single - ended output : Adm = CMRR =
Add = −38.6 | Acm = Acc = −0.661 2
−38.6 = 1000 or 60.0dB | VBC ≥ 0 requires VIC ≥ VC = −1.07V and −0.0385
Without detailed knowledge of the circuit for IEE , we can only estimate that VIC should not exceed VIC + 0.7 ≤ VCC − 0.7V which allows 0.7V for biasing I EE → −1.07V ≤ VIC ≤ +1.6V.
15.21 For a differential - mode input : ⎞⎛ ⎞⎛ ⎛v ⎛ v ∆g ⎞ ∆g ⎞ vod = −⎜ id − ve ⎟⎜ g m + m ⎟ R + ⎜− id − ve ⎟⎜ g m − m ⎟ R = −g m R vid + ∆g m Rve 2 ⎠ 2 ⎠ ⎠⎝ ⎠⎝ ⎝2 ⎝ 2 ⎛ ⎞ ∆g vod = −g m R⎜ vid + m ve ⎟ | At the emitter node : gm ⎠ ⎝ ⎞⎛ ⎞ ⎛ v ⎞⎛ ⎞ ⎛ vid ∆g m ∆g + g π ⎟ + ⎜− id − ve ⎟⎜ g m − m + g π ⎟ − GEE ve = 0 ⎜ − ve ⎟⎜ g m + 2 2 ⎠⎝ ⎠ ⎝ 2 ⎠⎝ ⎠ ⎝2
ve =
1 ∆g m 1 ∆g m β o REE vid ≅ vid VGS − VTN ). Q - Point = (24.2µA, 5.36V )
First, we should check our rule - of - thumb. Since we have symmetric power supplies, Add ≅ VDD + VSS = 10 or 20 dB. We should be ok. Rod = 2RD = 5kΩ → RD = 2.5kΩ | Selecting closest 5% value : RD = 2.4kΩ 20
Add = −g m RD = 10 20 = 10 | g m =
(4.17x10 ) = 348µA = 2(25x10 ) 2
−3
ID
−3
RSS =
10 = 4.17mS = 2Kn I D 2400
| VGS = VTN +
2I DS = 1.16V Kn
VSS − VGS 5 −1.16 = = 5.52kΩ | Selecting closest 5% value : RSS = 5.6kΩ 2I D 2(348µA)
15.26 (a ) This solution made use of the m - file listed above Prob. 15.22. VSS − VGS = 2I S RSS = 2I D RSS | VGS = VTN + VTN = VTO + γ
Add = −g m RD = 10 20 = 31.6 | First, we should check our rule - of - thumb.
Since we have symmetric power supplies, Add ≅ (VDD + VSS ) = 15, within a factor of about 2. We should be ok if we reduce the value of VGS − VTN . (Remember, our rule - of - thumb used VGS − VTN = 1V.) | g m RD = 31.6 =
2I D RD VGS − VTN
Maximum common - mode range requires minimum I D RD ⇒ minimum VGS − VTN Choosing VGS − VTN = 0.25V to insure strong inversion operation, I D RD =
0.25(31.6) 2
(0.25) (0.005) = 156µA 2I D → ID = Kn 2 2
= 3.95V | 0.25V =
I SS = 2I D = 312 µA | RD =
3.95V = 25.3kΩ → 27kΩ, the nearest 5% value. 156µA
I SS = 10µA | VO = −12 + (820kΩ)I D = −3.80V | For vI = 0, vO = VO = −3.80 V 2
( )
2 10−5 2I D = 1− = 0.86 V | VGS − VP = −0.14V VGS = VTP + KP 10−3 VDS ≤ −0.14V for pinchoff. So VD ≤ −1 V for pinchoff. g m = 2(1mA)(10µA) = 141µS | Add = −g m RD = −(141µS )(820kΩ)= −116 Acc = 0 for RSS and ro = ∞ | vO = VO −
(b) 2 ≤ 0.2V v1
GS
Add 116.0 v1 = −3.80 + (0.02)= −2.64V 2 2
− VP = 0.2(0.14) = 28.0mV | v1 ≤ 56 mV based upon the small - signal limit
These voltages can barely be supported by the 1.5- V negative power supply. VS1 = −VGS1 = −1.45V which is more negative than the -1.5 - V supply. Also,
VS 2 = VS1 − VGS 3 = −1.45V + 1.63 = +0.18V , but for I D3 = 100µA, VD3 = −1.5 + 10−4 (10kΩ)= −0.5V. M3 is just beyond pinchoff, and current source I2 has a very small voltage across it.
For VO = 0 → VEC 4 = 12 V and VEC 3 = 12 − 0.7 = 11.3 V | For balance, VCE1 = VCE 2 = 11.3 V ⎛ I 1 ⎞ 12V IC 4 + IC 3 = IC 4 + α F 3 I B 4 = IC 4 + α F 3 C 4 = IC 4 ⎜1+ | IC 4 = 495 µA | IC 3 = 4.95 µA ⎟= βF ⎝ β F + 1⎠ 24kΩ
15.56 The amplifier has an offset voltage of approximately 3.92 mV. Use this value to force the output to nearly zero. A transfer function analysis then yields
Av = +28,627 Rout = 2.868 MΩ
Rin = +50.051 kΩ
These values are similar to the hand calculations in Prob. 15.55. Rin and Rout are larger because the hand calculations did not adjust the value of current gain based upon the Early voltage. 15.57
15.64 *Problem 15.64 – Figure P15.63 *Vos (the dc value of V2) has been carefully adjusted to set Vo ≈ 0 VCC 8 0 DC 5 VEE 9 0 DC -5 V1 1 10 AC 0.5 V2 3 10 DC 1.21M AC -0.5 VIC 10 0 DC 0 I1 8 2 DC 496.3U R1 8 2 1MEG M1 4 1 2 2 PFET M2 5 3 2 2 PFET RD1 4 9 5.6K RD2 5 9 5.6K
The new output stage can be treated as an improved single transistor using the equation set from prob. 15.48 and the results from Ex. 15.4 Rin4-5 = 2β orπ 4 + β o2 RL = 2(100)(505Ω)+ 1002 (2kΩ) = 20.1MΩ | Av2 becomes
(
)
(
)
Av2 = −g m3 ro3 Rin4−5 = −22mS 161kΩ 20.1MΩ = −3510 | The gain of the g m4 RL 40 4.95x10−3 (2kΩ) g m4 RL 2 = = 0 = 0.995 emitter follower becomes Av3 ≅ g m4 RL 2 + g m4 RL 2 + 40 4.95x10−3 (2kΩ) 1+ 2 Av = −3.50(−3510)(0.995)= 12200.
(
(
)
)
CMRR and Rid do not change : CMRR = 63.5 dB and Rid = 101 kΩ Rout =
2 r 2 161kΩ + o32 = + = 26.2 Ω −3 g m4 β o 40 4.95x10 10 4
(a) Working backwards from the output :V = V − V = 12 − 0 = 12.0V | I = I = 5.00mA 2(0.005) 2I V =V + = 0.75 + = 2.16V | V = −(V − V )= −(12 − 2.16)= −9.84V K 0.005 DS 4
DD
O
D4
3
D4
GS 4
TN
DS 3
DD
GS 4
n
I D3 = I2 = 2.00mA | VGS 3 = VTP −
2(0.002) 2I D 4 = −0.75V − = −2.16V Kn 0.002
VD2 = VDD + VGS 3 = 12V − 2.16V = 9.84V | I D1 = I D2 =
15.72 The amplifier has an offset voltage of approximately –6.69 mV. This value is used to force the output to nearly zero. A transfer function analysis then yields
Av = +517 Rout = 339 Ω
Rin = +1.00 x 1020 Ω
These values are similar to the hand calculations in Prob. 15.71.
15.74 The amplifier has an offset voltage of approximately 48.69 mV. This value is used to force the output to nearly zero. A transfer function analysis then yields
Av = +2810
Rout = 339 Ω
Rin = +1.00 x 1020 Ω
These values are similar to the hand calculations in Prob. 15.73
2I D1 ⎛ 2I D2 ⎞ ⎟ | I D2 = I D1 − ⎜⎜VTP − Kn ⎝ K p ⎟⎠ I D1 =
0.5 → I D2 = I D1 = 9.38 µA 163.3
15.91 I SS ≥
5V 5V = = 5.00mA | iS = I SS + iL RL 1kΩ 5V 5V = I SS + 5.00mA | iSmin = I SS − = I S − 5.00mA 1kΩ 1kΩ = 5.00mA, iSmax = 10.0mA | iSmin = 0 | iD = 0.005(1+ sin 2000πt ) A
iSmax = I SS + For I SS
Power delivered from the supplies : P (t )= 10V (iD )+ 10V (I SS )= 0.05(2 + sin 2000πt ) W 1 T
Pav =
T
∫ 0.05(2 + sin 2000πt )dt = 100mW 0
⎛ 5 ⎞2 1 12.5mW Signal power developed in RL : Pac = ⎜ ⎟ = 12.5mW | η = 100% = 12.5% 100mW ⎝ 2 ⎠ 1kΩ
15.92 +5V T
t
0 -5V
15-60
2 2 1 ⎡(+5V ) T (−5V ) T ⎤ ⎥ = 10.0mW Pac = ⎢ + 5kΩ 2 ⎥⎦ T ⎢⎣ 5kΩ 2 1⎡ 5V T −5V T ⎤ Pav = ⎢5V − 5V = 10.0mW T ⎣ 5kΩ 2 5kΩ 2 ⎥⎦
15.102 The dc analysis is the same as Problem 15.101. However, the bypass capacitor provides as
ac ground at the base of the transistor so that Rth = 0. ⎛ ⎛ 100(220kΩ) ⎞ β o RE ⎞ ⎟ = 169 MΩ ⎜ Rout = ro ⎜1+ ⎟ = 2.50 MΩ⎜1+ ⎟ 110kΩ + 220kΩ ⎝ rπ + RE ⎠ ⎠ ⎝
A spread sheet will be used to assist in this design using β F = β o = 100 & VA = 70V The maximum current in the two bias resistors is 0.2mA. To allow some room for tolerances, choose I1 ≅ 0.15mA. Neglecting the transistor base current, 12V V V = 80kΩ | R2 = B (R1 + R2 ) = B 80kΩ | RB = R1 R2 0.15mA 12 12 (VB − 0.7) or R = 1 ⎛⎜100(VB − 0.7) − R ⎞⎟ | V = 12 − I R IC = 100 E B⎟ CE E E 101 ⎜⎝ RB + 101RE IC ⎠ ⎛ ⎞ β o RE 70 + VCE ro = | Rout = ro ⎜1+ ⎟ IC ⎝ RB + rπ + RE ⎠ Now, a spreadsheet MATLAB, MATHCAD, etc. can be used to explore the design space with VB as the primary design variable. R1 + R2 =
The first solution is the lowest value of VB that was found to meet the output specification using the nearest 5% values. The second is one in which the values were found to be very close to existing standard 5% resistor values, but it uses twice the value of VB and has a smaller output voltage compliance range.
(b) Using the CVD model for diode Q for dc calculations, (12V − 0.7) 68kΩ = −7.61V | R = 68kΩ 33kΩ = 22.2kΩ | V = −8.08 − I + I R V = ( ) ( ) 68kΩ + 33kΩ ⎛ V − 0.7 − (−12) V − 0.7 − (−12)⎞ ⎟22.2kΩ → V = −7.65V V = −7.61− ⎜⎜ + ⎟ 126 20kΩ 126 100kΩ ( ) ( ) ⎝ ⎠ 125 ⎛ V − 0.7 − (−12)⎞ 125 ⎛ V − 0.7 − (−12)⎞ ⎜ ⎜ ⎟ = 181 µA | I = α I = ⎟ = 36.2 µA I =α I = 3
vx = ve + (ix − g mv )ro | v = (− Av e )− ve = −ve (1+ A) | ix = Gve + g π (1+ A)ve | Combining : Rout = ro = Rout
vx 1+ µ f (1+ A) 1 = + ≅ ro (1+ β o ) for g π (1+ A)>> G and µ f (1+ A)>> 1 ix G + g π (1+ A) g o
50V + 10V = 605kΩ | Rout = 605kΩ(121)= 73.2 MΩ 99.2µA cannot exceed β oro because of the loss of base current through rπ .
15.121 ROUT is limited to βoro of the BJT. We need to increase the effective current gain of the transistor which can be done by replacing Q1 with a Darlington configuration of two transistors. +V CC I
o
+ V
REF
A
Q
2
Q1
R -V
EE
2 2 Now ROUT can approach the βoro product of the Darlington which is Rout ≅ β o ro2 . See Prob. 3 15.48
The approximate CMRR estimate is CMRR ≅ g m1 Rout 3 = 0.419mS (903kΩ) = 378 (51.6 dB)
15.125
ro1 since the collector current of the 2 current source is twice that of the input transistors. For a single- ended output, Assuming all devices are identical, Rout = β o1
Add = −
β µ g m1 RC RC R g β r | Acc = − = − C | CMRR = m1 o1 o1 = o1 f 1 ⎛ r ⎞ 2 β o1ro1 2 2 2⎜β o1 o1 ⎟ 2⎠ ⎝
Using our default paramters: CMRR ≅ 20β o1VA1 = 20(100)(70)= 140,000 (103dB) (Note that this analysis neglects the contribution of the output resistance ro of the input pair. If this resistance is included, a theoretical cancellation occurs and Acc = 0! Of course the output β o ro resistance expression Rout = is not precise, but an improvement over the CMRR expression 2 above is possible.)
15.128 4.02kΩ(1+ 0.15)(1− 0.03) ≤ R ≤ 4.02kΩ(1+ 0.15)(1+ 0.03) | 4.48kΩ ≤ R ≤ 4.76kΩ 15.129
⎛V ⎞ ⎛V ⎞ I ⎛V − V ⎞ I IC1 = I S1 exp⎜ BE1 ⎟ | IC2 = I S 2 exp⎜ BE 2 ⎟ | C2 = S 2 exp⎜ BE 2 BE1 ⎟ | ∆VBE = VBE2 − VBE1 VT ⎝ VT ⎠ ⎝ VT ⎠ IC1 I S1 ⎝ ⎠ ⎛ ∆I ⎞ ⎛ ∆I ⎞ I +I ∆I S = I S1 − I S 2 | I S = S1 S 2 | I S1 = I S ⎜1+ S ⎟ | I S 2 = I S ⎜1− S ⎟ 2 ⎝ 2I S ⎠ ⎝ 2I S ⎠ ⎡ ⎛ ∆I ⎞ ⎤ ⎢ I S ⎜1+ S ⎟ ⎥ ⎤ ⎡ ⎛ IC 2 I S1 ⎞ ⎢ 1 ⎝ 2I S ⎠ ⎥ = 0.025ln⎢ (1.05)⎥ = 2.50 mV = 0.025ln I = I : ∆V = V ln a ⎜ ⎟ ( ) C 2 C1 BE T ⎢() ⎛ ∆I S ⎞ ⎥ ⎝ IC1 I S 2 ⎠ ⎢⎣(0.95)⎥⎦ ⎟⎥ ⎢ I S ⎜1− ⎝ 2I S ⎠ ⎦ ⎣ ⎡ (1.10)⎤ (b) ∆VBE = 0.025ln⎢⎢ 0.90 ⎥⎥ = 5.02 mV )⎦ ⎣( ⎛ ∆I S ⎞ ⎜1+ ⎟ ⎛V − V ⎞ ⎛ 0.001⎞ IS ⎠ ∆I I S1 ⎝ (c) I = ⎛ ∆I ⎞ = exp⎜⎝ BE2V BE1 ⎟⎠ = exp⎜⎝ 0.025⎟⎠ = 1.04 → I S = 0.02 or 2% S2 T S S ⎜1− ⎟ IS ⎠ ⎝
15.130 (a) For v1 = 0 = v2 , VBE1 = VBE 2 and the collector currents are the same.
So, VOS = 0. Only the base currents will be mismatched. ⎛ VBE ⎞⎛ VCE ⎞ ⎛ VBE ⎞⎛ VCE ⎞ b 1 + | I I = I 1− 0.025 exp = I 1+ 0.025 exp ⎜ ⎟ ⎜ ⎟ ( ) C1 S ( ) ⎝ V ⎠⎝ V ⎠ C 2 S ( ) ⎜⎝ V ⎟⎠⎜⎝1 + V ⎟⎠ T A T A ⎛ V ⎞⎛ V ⎞ ⎛ V ⎞⎛ V ⎞ I +I ∆IC = IC 2 − IC1 = 0.05I S exp⎜ BE ⎟⎜1 + CE ⎟ | IC = C1 C 2 = I S exp⎜ BE ⎟⎜1 + CE ⎟ VA ⎠ 2 VA ⎠ ⎝ VT ⎠⎝ ⎝ VT ⎠⎝ ∆I ∆I VOS = C = VT C = 0.025V (0.05)= 1.25 mV gm IC ⎞ ⎞ ⎛ VBE ⎞⎛ ⎛ VBE ⎞⎛ VCE VCE ⎜ ⎟ ⎜ 1 + 1 + c I = I exp = I exp | I ( ) C1 S ⎜⎝ V ⎟⎠⎜ V 1+ 0.025 ⎟ C 2 S ⎜⎝ V ⎟⎠⎜ V 1− 0.025 ⎟⎟ )⎠ )⎠ T ⎝ T ⎝ A( A( ⎛ V ⎞⎛ ⎛ V ⎞⎛ V V ⎞ V ⎞ ∆IC = IC 2 − IC1 ≅ I S exp⎜ BE ⎟⎜1-1.025 CE −1+ 0.975 CE ⎟ = I S exp⎜ BE ⎟⎜0.05 CE ⎟ VA VA ⎠ VA ⎠ ⎝ VT ⎠⎝ ⎝ VT ⎠⎝ ⎛ VCE ⎞ ⎜ ⎟ ⎛ VBE ⎞⎛ VCE ⎞ IC1 + IC 2 ∆IC ∆IC ⎝ VA ⎠ = I S exp⎜ = VT = 0.025V (0.05) IC = ⎟⎜1 + ⎟ | VOS = ⎛ VCE ⎞ 2 VA ⎠ gm IC ⎝ VT ⎠⎝ ⎜1 + ⎟ VA ⎠ ⎝ V For CE = 0.1, VOS = 114 µV VA
(d ) V
OD
VOS =
[
]
= IC (RC + 0.025RC )− (RC − 0.025RC ) = 0.05IC RC
VOD V = VT OD = 0.025V (0.05) = 1.25 mV g m RC IC RC
⎛ V ⎞⎛ 14.3 VBE ⎞ 12 − 0.7 = 151 µA | I REF = IC1 + (1+ 5 + 8.3)I B | I REF = I S exp⎜ BE ⎟⎜1+ + ⎟ 4 7.5x10 ⎝ VT ⎠⎝ β FO VA ⎠
V 5 1+ CE 2 1+ ⎛ VBE ⎞⎛ VCE2 ⎞ VA 60 IO2 = 5I S exp⎜ | IO2 = 5(151µA) = 631 µA ⎟⎜1+ ⎟ = 5I REF 14.3 VBE 14.3 0.7 VA ⎠ ⎝ VT ⎠⎝ 1+ + 1+ + 50 60 β FO VA VA + VCE2 60 + 5 = = 103 kΩ IC 2 6.31x10−4 V 3 1+ CE 3 1+ VA 60 IO3 = 8.3I REF = 8.3(151µA) = 1.02 mA 14.3 VBE 14.3 0.7 1+ + 1+ + 50 60 β FO VA Rout2 = ro2 =
Rout3 = ro3 =
VA + VCE3 60 + 3 = = 61.8 kΩ IC 3 1.02x10−3
(b) Since all areas are scaled equally, the current ratios stay the same, and there is no change from part (a). This ignores the slight change in VBE of Q1 due to its area change. 12 − 0.7 − 0.7 I = 141 µA | I REF = IC1 + (1+ 5 + 8.3) B 4 β FO + 1 7.5x10 ⎛ V ⎞⎛ 2V ⎞ 14.3 I REF = I S exp⎜ BE ⎟⎜⎜1+ + BE ⎟⎟ ⎝ VT ⎠⎝ β FO (β FO + 1) VA ⎠ V 1+ CE 2 ⎛ VBE ⎞⎛ VCE2 ⎞ VA IO2 = 5I S exp⎜ ⎟⎜1+ ⎟ = 5I REF 14.3 2V VA ⎠ ⎝ VT ⎠⎝ 1+ + BE β FO (β FO + 1) VA
⎛ 5 8.3⎞ I B 12 − 0.7 − 0.7 = 106 µ A | I = I + 1+ + ⎜ ⎟ REF C1 100x103 ⎝ 3 3 ⎠ β FO + 1 ⎛ V ⎞⎛ 5.43 2V ⎞ I REF = I S exp⎜ BE ⎟⎜⎜1+ + BE ⎟⎟ ⎝ VT ⎠⎝ β FO (β FO + 1) VA ⎠ V 1+ CE 2 ⎛ ⎞ ⎛ ⎞ V 5 5 V VA IO2 = I S exp⎜ BE ⎟⎜1+ CE 2 ⎟ = I REF 5.43 2V VA ⎠ 3 3 ⎝ VT ⎠⎝ 1+ + BE β FO (β FO + 1) VA I REF =
⎡ix ⎤ ⎡gm1 + gπ 3 −gπ 3 ⎤⎡v e ⎤ | ⎢ ⎥=⎢ ⎥⎢ ⎥ ⎣0 ⎦ ⎣gm1 − gπ 3 gπ 3 + go2 ⎦⎣v b ⎦ IC1 ≅ IC 2 ≅ IC 3 so the small - signal parameters are matched ⎛ β 1⎞ ∆ = 2gm1gπ 3 + gm1go2 + gπ 3 go2 = gm1gπ 3 ⎜⎜2 + o + ⎟⎟ ≅ 2gm1gπ 3 for µ f >> β o >> 1 µf µf ⎠ ⎝ g + go2 g −g i ⎛ β ⎞ i = x ⎜⎜1+ o ⎟⎟ ≅ x | v b = −ix m1 π 3 v e = ix π 3 ∆ 2gm1 ⎝ µ f ⎠ 2gm1 ∆ g + go2 i ⎛ 1⎞ i i v b − v e = −ix m1 = − x ⎜⎜1+ ⎟⎟ ≅ x rπ 3 | i1 = gπ 3 (v b − v e ) = x ∆ 2gπ 3 ⎝ µ f ⎠ 2 2 i βr βr i v 1 v x = v e + (ix − β oi1)ro3 = x + ix ro3 + β o ro3 x | Rout = x = + ro3 + o o3 ≅ o o3 2gm1 2 ix 2gm1 2 2
(a) Assuming balanced drain voltages, I VGS1 = VTN +
2I D1 2I REF = 0.75 + Kn1 4 5Kn'
5 − 0.75 − I REF =
( )
2I REF
( )
4 5K
' n
D3
= I D1 = I REF
| VGS 3 = 0.75 + 2I REF
− 0.75 −
(
4 20Kn'
30kΩ
)
|
⎛W ⎞ ⎜ ⎟ ⎝ L ⎠1 I REF = ⎛W ⎞ 4 ⎜ ⎟ ⎝ L ⎠2 2I REF
(
4 20Kn'
(30kΩ)I
REF
| I REF =
5 − VGS1 − VGS 3 30kΩ
)
= 3.5 −1.5
I REF 10Kn'
2 Using Kn' = 25x10-6 and rearranging : 9x108 I REF − 2.19x105 I REF + 12.25 = 0
I REF = 21.8 µA. Drain voltage balance on M1 and M2 4 ⎛ W ⎞ 80 2I REF 2I REF | VTN + = VTN + | ⎜ ⎟ = ⎛W ⎞ ' ⎝ L ⎠4 1 4 20Kn' ⎜ ⎟ Kn ⎝ L ⎠4
I REF = 87.2 µA and IO = requires VGS 4 = VGS 3
(
)
(b) This part requires an iterative solution or the use of a computer solver. Assuming VDS balance between M1 and M2 , λ ≠ 0 will not affect the current mirror ratio, but it will change VGS and hence I REF slightly. One iterative approach : Guess VGS1 | Then I D1 =
2 5Kn' VGS1 − VTN ) (1+ λVGS1 ) ( 2
Since I D3 = I D1 , VGS 3 = VTN +
[
2I DS1
]
20K 1+ λ (5 − VGS1 ) ' n
5 − VGS1 − VGS 3 I and I D1 = REF . 30kΩ 4 If the second value of I D1 does not agree with the first, then try a new VGS1. I REF =
A spreadsheet yields : VGS1 = 1.336V , VGS 3 = 1.381V , I REF = 87.5µA, IO = 21.7µA. Note: There is essentially no change from the first answer!
The circuit is the same as Fig. 16.20 with the addition of RREF in parallel with ro2. We require RREF >> ro2 in order not to reduce the gain of the feedback loop. A current source with a source resistor which achieves ROUT = ro(1+gmRs) should be sufficient. A cascode or Wilson source will also work. 15.175
M1 and M2 are voltage balanced. (a) Rout = µ f 4ro2 | All Kn are the same : IO = I REF = 17.5µA VGS1 = 0.75 +
⎛W ⎞ ⎜ ⎟ ⎝L⎠ (a) M1 and M 2 are voltage balanced, so IO = ⎛ W ⎞2 IREF = 1.05IREF = 18.4µA, a 5% error. ⎜ ⎟ ⎝ L ⎠1
(b) To first order, IO does not depend upon W/L of M 3 and M 4 .
The mismatch will create
a small VDS mismatch between M1 and M 2 , but this error will be negligible. An estimate of this effect is ∆Io = go2∆VDS where ⎛ 2ID 3 ⎞ ⎛ 2ID 4 ⎞ 2ID 2ID 2ID − = 0.026 ∆VDS = VGS 3 − VGS 4 = ⎜VTN + ⎟ − ⎜VTN + ⎟= Kn 3 ⎠ ⎝ Kn 4 ⎠ Kn3 0.95K n 3 Kn3 ⎝ ∆VDS = 0.026
15.203 This problem should refer to Prob. 15.202 (a) and (b) *Problem 15.203(a) - MOS reference current cell VDD 1 0 DC 5 AC 1 VSS 5 0 DC -5 M1 3 3 5 5 NFET W=10U L=1U M2 2 3 4 5 NFET W=20U L=1U M3 3 2 1 1 PFET W=10U L=1U M4 2 2 1 1 PFET W=10U L=1U R 4 5 10K .MODEL NFET NMOS KP=25U VTO=0.75 PHI=0.6 GAMMA=0 LAMBDA=0.017 .MODEL PFET PMOS KP=10U VTO=-0.75 PHI=0.6 GAMMA=0 LAMBDA=0.017 *.MODEL NFET NMOS KP=25U VTO=0.75 PHI=0.6 GAMMA=0 LAMBDA=0 *.MODEL PFET PMOS KP=10U VTO=-0.75 PHI=0.6 GAMMA=0 LAMBDA=0 *Problem 15.203(b) - MOS reference current cell *.MODEL NFET NMOS KP=25U VTO=0.75 PHI=0.6 GAMMA=0.5 LAMBDA=0.017 *.MODEL PFET PMOS KP=10U VTO=-0.75 PHI=0.6 GAMMA=0.75 LAMBDA=0.017 .OP .AC LIN 1 1000 1000 .PRINT AC ID(M1) ID(M2) .END
Results: (a) ID2 = 13.9 µA ID2 = 12.3 µA
D1 D2 SVI DD = 7.64 x10−2 SVI DD = 6.23x10−2
The currents differ considerably from the hand calculations. D1 D2 Results: (b) ID1 = 8.19 µA ID2 = 7.24 µA SVI DD = 7.75x10−2 SVI DD = 6.31x10−2
The currents differ considerably from the hand calculations. The currents are quite sensitive to the value of λ. The hand calculations used λ = 0. If the simulations are run with λ = 0, then the results are identical to the hand calculations. 15.204 V ⎛ I 5A ⎞ 0.025V ⎛ 2IC 2 5A ⎞ IC 2 = T ln⎜ C1 ln⎜ ⎟ | IC1 = IC 3 = 2IC 4 = 2IC 2 | IC 2 = ⎟ = 5.23 µA R ⎝ A IC 2 ⎠ 11kΩ ⎝ A IC 2 ⎠ V ⎛ I 3A ⎞ 0.025V ⎛15.7µA ⎞ ln⎜ IC 7 = 5IC 4 = 5(5.23µA) = 26.2 µA | IC 8 = T ln⎜ C 4 ⎟= ⎟ → IC 8 = 6.00 µA 4kΩ ⎝ IC 8 ⎠ R8 ⎝ A IC 8 ⎠ V ⎛ I A ⎞ 0.025V ⎛ 10.4µA ⎞ ln⎜ IC 5 = 2.5IC1 = 5IC 2 = 26.2 µA | IC 6 = T ln⎜ C1 ⎟= ⎟ → IC 6 = 5.42 µA 3kΩ ⎝ IC 6 ⎠ R6 ⎝ A IC 6 ⎠
15.205 V ⎛ I 10A ⎞ 0.025V ⎛ IC 2 10A ⎞ IC 2 = T ln⎜ C1 ln⎜ ⎟ | IC1 = IC 3 = IC 4 = IC 2 | IC 2 = ⎟ = 5.23 µA R ⎝ A IC 2 ⎠ 11kΩ ⎝ A IC 2 ⎠ V ⎛ I 3A ⎞ 0.025V ⎛15.7µA ⎞ ln⎜ IC 7 = 5IC 4 = 5(5.23µA) = 26.2 µA | IC 8 = T ln⎜ C 4 ⎟= ⎟ → IC 8 = 6.00 µA 4kΩ ⎝ IC 8 ⎠ R8 ⎝ A IC 8 ⎠ V ⎛ I A ⎞ 0.025V ⎛ 5.23µA ⎞ ln⎜ IC 5 = 2.5IC1 = 13.1 µA | IC 6 = T ln⎜ C1 ⎟= ⎟ → IC 6 = 3.45 µA 3kΩ ⎝ IC 6 ⎠ R6 ⎝ A IC 6 ⎠ 15.206
VT ⎛ IC1 IS 2 ⎞ 0.025V ⎛ 2IC 2 7IS1 ⎞ ⎜ln ⎟= ⎜ln ⎟ = 15.3 µA R ⎝ IC 2 IS1 ⎠ 4.3kΩ ⎝ IC 2 IS1 ⎠ = IC 5 = IC 6 = IC1 = 30.6 µA | IC 3 = IC 7 = IC 2 = 15.3 µA
(a) IC1 = 2IC 2 set by Q 4 and Q 3 IC1 = 2IC 2 = 30.6 µA | IC 4
(b) No change.
| IC 2 =
The currents are independent of the areas of Q5 , Q6 , and Q7 .
15.209 (a) The M 3 - M 4 current mirror forces ID1 = 1.5ID 2 .
VGS1 − VGS 2 = ID 2 R | ID 2 R = VTN +
2ID1 2ID 2 − VTN − ' 10K n 30K n'
⎞ ⎛ 1 ⎜ 1 ⎛ 3ID 2 2ID 2 ⎞ 2ID 2 3ID 2 ⎟ ID 2 = ⎜ − − ⎟= R ⎝ 10K n' 30K n' ⎠ 3300 ⎜⎝ 10(25x10−6 ) 30(25x10−6 )⎟⎠ 57.9 ID 2 = ⇒ ID 2 = 308 µA ID1 = 462 µA 3300 ID 4 = ID 5 = ID 6 = ID1 = 462 µA | ID 3 = ID 7 = ID 2 = 308 µA
(b) With λ
= 0, the currents do not depend upon the W/L ratios of M5 , M 6 or M 7
as long as all transistors remain in the active region. For λ ≠ 0, there will be a weak dependence, since the drain - source voltages of M2 and M 3 will change slightly. 15.210 *Problem 15.210 - MOS reference current cell VDD 1 0 DC 15 AC 1 M3 3 2 1 1 PFET W=10U L=1U M4 2 2 1 1 PFET W=15U L=1U M5 4 3 2 2 PFET W=10U L=1U M6 4 4 6 6 NFET W=10U L=1U M7 3 4 5 5 NFET W=10U L=1U M1 6 6 0 0 NFET W=10U L=1U M2 5 6 7 7 NFET W=30U L=1U R 7 0 3.3K *.MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0 *.MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0 .MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.017 .MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0.017 .OP .AC LIN 1 1000 1000 .PRINT AC ID(M1) ID(M2) .END
Results: ID2 = 265 µA ID1 = 377 µA These differ from the hand calculations due to the nonzero value of λ. Simulation with λ = 0 gives results very close to the hand calculations. D2 D2 = 9.82 x 10−4 SVI DD = 6.99 x 10−4 SVI DD
15.211 The M 3 - M 4 current mirror forces I D1 = I D2. ⎛ 2I D1 ⎞ ⎛ 2I D2 ⎞ ⎟ ⎜ ⎟ − V + VGS1 − VGS 2 = I D2 R | I D2 R = ⎜⎜VTN + TN 10Kn' ⎟⎠ ⎜⎝ 30Kn' ⎟⎠ ⎝ ⎛ 1 ⎜ 1 ⎛ 2I D2 2I D2 ⎞ I D2 I D2 ⎜ ⎟ = I D2 = ⎜ − − ' ' ⎟ − 6 R ⎝ 10Kn 30Kn ⎠ 3300 ⎜ 5 25x10 15 25x10−6 ⎝ 34.1 I D2 = ⇒ I D2 = 107 µA I D1 = 107 µA 3300 I D 4 = I D5 = I D6 = I D1 = 107 µA | I D3 = I D 7 = I D2 = 107 µA
(
)
(
⎞ ⎟ ⎟ ⎠
)
15.212 -
r o4
1 g m3
v3
+
r ο3
gm4 v3
i cc
icc
Current mirror model: 1 Assuming VDS ro2 g m2ro2 µ f 2
vo 1 ∆g m2 ≅ v ic 2 g m2
The collector current imbalance can be found as follows: Assume that VEC 4 = VEC 3 + ∆V 0.7 + ∆V ⎛ ∆V ⎞ V 75V VA | ∆V ≅ A = = IC 2 ⇒ IC1 = IC1⎜1− = 0.60V ⎟ 2 0.7 β F 125 ⎝ VA ⎠ 1+ + β F VA 1+
and equal Early voltages: IC 4
⎛ V ⎞ ⎛ V − ∆V ⎞ V ∆V ∆IC = IC1 − IC 2 = IC 0 ⎜1+ C1 ⎟ − IC 0 ⎜1+ C1 | IC 0 = IS exp BE ≅ IC ⎟ = IC 0 VT VA ⎠ VA ⎝ VA ⎠ ⎝ ∆IC ∆V 1 ∆gm 2 ∆IC 1 1 ∆V ∆V ∆IC = IC 0 ≅ IC | ≅ = | = = | Acd = VA β F 2β F IC gm 2 IC βF VA VA 1 1500 = 4 x10 -3 | CMRR = = 3.75x10 5 (112 dB) -3 2(125) 4 x10 15.218 continued on next page Acd =
For VIC : VCB1 = VCC − VEB 3 − VIC ≥ 0 | VCC ≥ VIC + VEB 3 = 1.5 + 0.7 = 2.2 V Assume that the current source needs VCS = 0.7 V across it to operate properly. VIC − VBE − (−VEE ) ≥ VCS | VEE ≥ VCS + VBE − VIC = 0.7 + 0.7 − (−1.5) = 2.9V We need ± 2.9 - V supplies or approximately ± 3V.
0.7 + ∆V ⎛ ∆V ⎞ v 1 ∆g m2 VA 100V VA | IC 4 = IC 2 ⇒ IC1 = IC1⎜1− = = 0.80V Acd = o ≅ ⎟ | ∆V ≅ 2 0.7 v ic 2 g m2 βF VA ⎠ 125 ⎝ 1+ + β F VA ⎛ V ⎞ ⎛ V − ∆V ⎞ V ∆V | IC0 = I S exp BE ≅ IC ∆IC = IC1 − IC2 = IC 0 ⎜1+ C1 ⎟ − IC0 ⎜1+ C1 ⎟ = IC 0 VT VA ⎠ VA ⎝ VA ⎠ ⎝ ∆IC ∆V 1 ∆g m2 ∆IC 1 1 ∆V ∆V ∆IC = IC 0 ≅ IC | ≅ = | = = | Acd = IC g m2 IC βF VA β F 2β F VA VA 1+
For VIC : VCB1 = VCC − VEB 3 − VIC ≥ 0 | VCC ≥ VIC + VEB 3 = 1.5 + 0.7 = 2.2 V Assume that the current source needs VCS = 0.7 V across it to operate properly.
VIC − VBE − (−VEE )≥ VCS | VEE ≥ VCS + VBE − VIC = 0.7 + 0.7 − (−1.5) = 2.9V We need ± 2.9 - V supplies or approximately ± 3V.
15.219 Results: For VA = 75 V, Adm = 1470 and Acd = 6.92x10-3. CMRR = 106 dB. The results are similar to hand calculations. Note that a very high CMRR is achieved when the circuit is brought back to balance (with VOS = 0.728mV), as is the case in operational amplifier input stages with feedback applied. For the case with the offset voltage applied, Acd = 2.71x10-7.
15.230 *Figure P15.229 - CMOS Amplifier with Active Load VDD 8 0 DC 10 VSS 14 0 DC -10 *An offset voltage is used to set Vo to approximately zero volts. V2 1 15 DC 0.3506M AC 0.5 V1 2 15 DC 0 AC -0.5 VIC 15 0 DC 0 M1 3 1 5 14 NFET W=20U L=1U M2 4 2 5 14 NFET W=20U L=1U M3 3 3 8 8 PFET W=50U L=1U M4 4 3 8 8 PFET W=50U L=1U M5 6 4 8 8 PFET W=100U L=1U *The offset can be adjusted to zero by correcting the value of W/L *M5 6 4 8 8 PFET W=89.5U L=1U M6 8 6 13 14 NFET W=10U L=1U M7 14 7 13 8 PFET W=25U L=1U MGG 6 6 7 14 NFET W=5U L=1U M10 9 9 14 14 NFET W=10U L=1U M11 5 9 14 14 NFET W=20U L=1U M12 7 9 14 14 NFET W=20U L=1U IREF 0 9 DC 100U .MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.017 .MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0.017 *.MODEL NFET NMOS KP=25U VTO=0.75 GAMMA=0.6 LAMBDA=0.017 *.MODEL PFET PMOS KP=10U VTO=-0.75 GAMMA=0.75 LAMBDA=0.017 .OP .AC LIN 1 1000 1000 .PRINT AC VM(13) VP(13) VM(4) VP(4) .TF V(13) VIC .END Results: Adm = 11200, Acm = 0.604, Rout = 3.10 kΩ. (a) 1 2 3 4 5 6 7 GG 10 11 12 IDS (µA) 112 112 112 112 223 44.2 44.2 223 100 223 223 VDS (V) 9.96 9.99 -1.41 -1.37 -8.70 10.0 -10.0 -2.60 1.63 8.63 8.70 (b) IDS (µA) 110 110 110 110 219 0 0 219 100 219 219 VDS (V) 11.2 11.2 -1.40 -1.37 -8.85 10.0 -9.97 -3.79 1.63 7.41 7.35
Note that the body effect has increased the threshold voltages of M6 and M7 to the point that they are no longer conducting. VTN6 = 2.24 V and VTP7 = -2.61V. The W/L ratio of MGG needs to be redesigned to solve this problem.
M 6 and M 7 are always saturated : e.g. VDS 6 ≥ VGS 6 The minimum supply voltages are : VDD ≥ 1.90V VSS ≥ 2.27V For the symmetrical supply case, VDD = VSS ≥ 2.27V (b) The values of VDD and VSS in part (a) do not provide any significant common - mode input voltage range. For saturation of M11 with VIC = −5V, VDS11 = VIC − VGS 2 − (−VSS ) = VSS −1.38 − 5 ≥ 0.894 → VSS ≥ 7.27V For saturation of M1 and M 2 : VDS1 = VDD − VSG 3 − (VIC − VGS1) = VDD − 5 −1.38 +1.38 ≥ 0.633 → VDD ≥ 5.63V For an output range of 5V, saturation of M12 requires V 2.54 ≥ 0.894 → VSS ≥ 7.25V VDS12 = −5 − GSGG − (−VSS ) = VSS − 5 − 2 2 For Saturation of M 5 : 2.54 − 5 ≥ 0.633V → VDD ≥ 6.90V VSD 5 = VDD − 2 The minimum supply voltages are : VDD ≥ 6.90V VSS ≥ 7.25V For the symmetrical supply case, VDD = VSS ≥ 7.25V
15.234 *Figure P15.233 - CMOS Amplifier with Active Load VDD 8 0 DC 10 VSS 14 0 DC -10 *Connect feedback to determine Vos *V1 1 13 DC 0 *The offset voltage must be used to set Vo to approximately zero voltages. V1 1 15 DC 0.4423M AC 0.5 V2 2 15 DC 0 AC -0.5 VIC 15 0 DC 0 M1 3 1 5 5 NFET W=40U L=1U M2 4 2 5 5 NFET W=40U L=1U M3 6 7 8 8 PFET W=80U L=1U M4 7 7 8 8 PFET W=80U L=1U M5 4 3 7 7 PFET W=80U L=1U M6 13 4 8 8 PFET W=42.9U L=1U *The offset can be adjusted to zero by correcting the value of W/L *M6 13 4 8 8 PFET W=37.25U L=1U M7 13 9 12 12 NFET W=15U L=1U M8 12 10 14 14 NFET W=15U L=1U M9 5 9 11 11 NFET W=5U L=1U M10 11 10 14 14 NFET W=5U L=1U M11 9 9 10 10 NFET W=5U L=1U M12 10 10 14 14 NFET W=5U L=1U M13 3 3 6 6 PFET W=80U L=1U IREF 0 9 DC 250U .MODEL NFET NMOS KP=25U VTO=0.75 LAMBDA=0.017 .MODEL PFET PMOS KP=10U VTO=-0.75 LAMBDA=0.017 .OP .AC LIN 1 1000 1000 .PRINT AC VM(13) VP(13) VM(4) VP(4) .TF V(13) VIC .END
Results: Vos = 0.4423 mV, Adm = 22500, Acm = 0.2305, CMRR = 99.9 dB, ROUT = 90.3 MΩ. The values of Add and Rout are similar to hand calculations. Acd and the CMRR are limited by the offset induced mismatches in the devices. With the W/L of M6 corrected, Vos ≈ 0, Adm = 20800, A = 9.28 x 10-3. R = 90.3 MΩ, CMRR = 127 dB. cm
The W/L ratios have been scaled to keep the Q-points and gain the same. Note that the output stage should remain a source follower pair and is not mirrored.
Note that the output stage should remain complementary emitter − followers. I The gain of the first stage is approximately Av1 = gm1rπ 5 = C1 β o5 , the mirror IC 5 image amplifier with an npn transistor for Q5 will have the highest gain. The voltage gain of the rest of the amplifier is the same.
IC23 = 3IC 22 = 138 µA | IC 24 = IC 22 = 46.0 µA | ⎛ 46.0µA ⎞ V ⎛ I ⎞ 0.025V ⎛ 46.0µA ⎞ I1 = T ln⎜ C 20 ⎟ = ln⎜ ⎟ = 6.25µAln⎜ ⎟ =→ I1 = 9.72µA 4kΩ R ⎝ I1 ⎠ ⎝ I1 ⎠ ⎝ I1 ⎠
(b) I
22V − 0.7 − 0.7 − (−22V )
= 426µA 100kΩ IC23 = 3IC 22 = 128 µA | IC 24 = IC 22 = 426 µA ⎛ 426µA ⎞ V ⎛I ⎞ I1 = T ln⎜ C 20 ⎟ = 6.25µAln⎜ ⎟ → I1 = 19.3µA R ⎝ I1 ⎠ ⎝ I1 ⎠ C 22
= IC20 =
(c) The input bias current and input resistance of the amplifier are directly dependent upon I1 , whereas the gain of the interior amplifier stages is approximately independent of bias current.
50µA (7.32µA) = 20.3µA 18µA 50µA Using Eq. 16.139 : io = −20(20.3µA)v id = (−0.406 mS )v id | IC 4 = (7.25µA) = 20.1µA 18µA ⎛ 20.3µA(1kΩ)⎞ 60V = 2.84 MΩ Rout 6 ≅ ro6⎜1+ ⎟ = 1.81ro6 | Rth = 1.81ro6 2ro4 = 0.952ro4 = 0.95 0.025V ⎠ 20.1µA ⎝ The input stage current is proportional to I1 : IC 2 =
io = (−4.06 x 10 -4 )v id | Rth = 2.84 MΩ As a check, we know that g m ∝ IC and ro ∝ ⎛ 50µA ⎞ -4 io = 1.46x10−4 v id ⎜ ⎟ = −4.06 x 10 v id 18 µ A ⎝ ⎠ which underestimates Rth . 15.245
(a)
R2 =
β o2 ro2 2
=
1 . Using the results from Fig. 16.60, IC ⎛ 18µA ⎞ and Rth = 6.54 MΩ⎜ ⎟ = 2.35MΩ ⎝ 50µA ⎠
50 60 + 15.7 = 2.84 MΩ | The cascode source uses up an extra VEB . 2 0.666mA
(b) Transistor Q11 replicates the reference current. This current divides in two and controls two matched current mirrors formed of Q4-Q3 and Q5-Q6. The currents of Q1 and Q7, and Q2 and Q8 are equal to the output current of Q3 and Q4. (c) v1 is the inverting input; v2 is the non-inverting input. g m5 = g m6 | g m2 = 2g m6 | ro8 = ro6 | io = g m6ve6 ve6 = v id Differential-mode Half Circuit
Q2 v id 2
+ -
Q6 1 g m5
15-146
io 2
g m2 1 1 = v | io = g m6 vid ⎛ 1 1 ⎞ 2 id 2 1+ g m2 ⎜ ⎟ ⎝ g m5 g m6 ⎠
(b) Transistors Q9 and Q10 form a current mirror that replicates the base current of transistor Q8. The output current divides in two and forms the base currents of Q3 and Q4. Since Q3 and Q4 match Q8, the collector currents of Q1-Q6 will all be equal to IREF/2. (c) v1 is the inverting input; v2 is the non-inverting input. io = g m4ve4 | io = 2g m4ve4 2 g m2 v v 1 ve4 = id = vid | io = g m4 id ⎛ 1 ⎞ 4 2 2 1+ g m2⎜ ⎟ ⎝ g m4 ⎠ g m2 = g m4 | ro6 = ro4 |
| 2 zeros at ω = 0 ⎛ C2 (RC + R3 ) 1⎞ C1⎜ RS + RE ⎟ gm ⎠ ⎝ ⎛ Rin ⎞ ⎛ Rin ⎞ ⎛ Rin ⎞ =⎜ ⎟ Avt = ⎜ ⎟ g m RL = ⎜ ⎟ g m Rout R3 | g m = 40(1mA)= 0.04S ⎝ RI + Rin ⎠ ⎝ RI + Rin ⎠ ⎝ RI + Rin ⎠
(
)
1 = 24.9Ω | RL = Rout R3 | Rout = RC ro = RC = 2.2kΩ gm ⎛ ⎞ 24.9Ω Amid = ⎜ ⎟(0.04) 2.2kΩ 51kΩ = +9.34 →19.4 dB ⎝ 200Ω + 24.9Ω ⎠ 1 rad 1 rad ω1 = = 946 | ω2 = −6 = 18.8 −6 s s 4.7x10 (200 + 24.9) 10 (2.2kΩ + 51kΩ) Rin = RE
(b) 500kΩ = 3V | REQ = 500kΩ 1.5MΩ = 3.75kΩ 500kΩ + 1.5MΩ VEQ − VBE (3 − 0.7)V = 100 = 33.1 µA IC = β F I B = β F 375kΩ + (101)(65kΩ) REQ + (β F + 1)RE
VEQ = 12V
⎛ ⎞ 101 65kΩ⎟ = 2.71 V | Q - Point : (33.1 µA, 2.71 V ) VCE = VCC − IC RC − I E RE = 12 − (33.1µA)⎜ 215kΩ + 100 ⎝ ⎠ Note: As designers, we are free to change the amplifier design, but we typically cannot change the characteristics of the source and load resistances. However, the problem statement indicated changing all resistors.
(a) 430kΩ = 5.21V | REQ = 430kΩ 560kΩ = 243kΩ 430kΩ + 560kΩ K 2 Assume active region operation : ID = n (VGS − VTN ) | VEQ = VGS + ID RS 2 ⎛ 0.5mA ⎞ 2 5.21 = VGS + 3.9kΩ⎜ ⎟(VGS −1) → VGS = 2.629V and ID = 663µA ⎝ 2 ⎠
VEQ = 12V
VDS = VDD − ID RD − IS RS = 12 − (663µA)(13kΩ + 3.9kΩ) = 0.795 V The transistor is not in pinch off! Reduce RD to 10 kΩ. VDS = VDD − ID RD − IS RS = 12 − (663µA)(10kΩ + 3.9kΩ) = 2.78 V - Active region is correct. RI 1kΩ
CU 8 5 0.75PF * .AC DEC 100 1 10MEG .PRINT AC VM(6) .PROBE .END Results: Amid = -128, fL = 47 Hz, fH = 1.10 MHz 16.48
(a ) See Eqs. (16.88 -16.96). ⎤ ⎡V (s)⎤ ⎡I (s)⎤ ⎡s(C + C )+ g −sC ⎥⎢ ⎥ ⎢ ⎥=⎢ s(C + C )+ g ⎥⎦ ⎢⎣V (s)⎥⎦ ⎣ 0 ⎦ ⎢⎣ −(sC − g ) ∆ = s [C (C + C )+ C C ]+ s[C g + C (g + g + g )+ C g ]+ g g π
S
µ
µ
2
(b) ω
π
P1
ω P2 ≅
≅
µ
L
πo
µ
µ
m
µ
L
1
L
π
L
L
µ
2
m
g L g πo = Cπ g L + Cµ (g m + g πo + g L )+ CL g πo
Cπ g L + Cµ (g m + g πo + g L )+ CL g πo Cπ (Cµ + CL )+ Cµ CL
=
πo
L
L
πo
L
πo
1 ⎡ R⎤ rπo ⎢Cπ + Cµ (1+ g m RL )+ (Cµ + CL ) L ⎥ rπo ⎦ ⎣ gm
⎛ C ⎞ Cπ ⎜⎜1+ L ⎟⎟ + CL ⎝ Cµ ⎠
(c) The three capacitors form a loop, and there are only two independent voltages among the three capacitors. 16.49 CT = Cπ + Cµ (1+ g m RL )= 20 pF + 1pF 1+ 40(1mA)(1kΩ) = 61 pF
1+ A 1+ A = = sC(1+ A) | Cin = C (1+ A)= 10−10 F 1+ 105 = 10 µF 1 Z (s) sC Z (s) s + 10 s + 10 1 105 (b) Zin = Y = 1+ A s = 106 = 105 s + 10 + 106 ≅ 105 s + 106 ( ) 1+ in s + 10 Using MATLAB : Zin (j2000π )= (4.95 + j6.28) Ω in
2500ZC = (752 − j1000) Ω | SPICE : (836 − j1040) Ω 2500 + ZC (d) *Problem 16.52 - Common-Emitter Amplifier IS 0 1 AC 1 RX 1 2 0.25K RPI 2 0 2.5K CPI 2 0 15PF CU 2 3 1PF GM 3 0 2 0 40MS RL 3 0 2.5K .AC LIN 1 1KHZ 1KHZ *.AC LIN 1 50KHZ 50KHZ *.AC LIN 1 1MEG 1MEG .PRINT AC VR(1) VI(1) VM(1) VP(1) .END Using MATLAB : Z = 250 +
Note that the CT approximation does not provide as good an estimate of Zin at high frequencies (note the discrepancy at 1 MHz). 16.53 Amid = 39.2 dB, fL = 0 Hz, fH = 5.53 MHz 16.54
(c) There are two poles. The SCTC technique assumes both are at low frequency and yields the largest pole. The OCTC assumes both are at high frequency and yields the smallest pole.
Rin 2.48kΩ g m RL = (0.320ms)(18.0kΩ)= +3.19 2kΩ + 2.48kΩ RI + Rin ⎛ ⎞ ⎛ ⎞ ⎜ ⎟ ⎜ ⎟ 1 1 1 ⎜ 1 ⎜ ⎟ = 11.3 MHz ⎟= fH = ⎜ ⎟ 3.0 pF 2π ⎜ CGS π 2 ⎟ + CGD RL ⎟ + 0.6 pF (18.0kΩ)⎟ ⎜ ⎜ ⎝ Gth + g m ⎠ ⎝ (0.5848 + 0.32)mS ⎠ Note that the contribution of the input pole cannot be neglected because of the low fT of the MOSFET. Amid =
R1S = RI + Rin = 4.48kΩ | R3S = R7 + Rout ≅ 100kΩ + 22kΩ = 122kΩ 1 ⎛ 1 1 ⎞ fL = + ⎜ ⎟ = 20.6 Hz 2π ⎝ R1S C1 R3S C3 ⎠ Note that the is no signal current in C2 , so it does not contribute to f L .
f L ≅ 15.5 Hz Note that a low frequency RHP zero makes the calculation of fH a very poor estimate for the FET case. See the analysis in Prob. 17.73 which shows ωz = gm/CGS. *Problem 16.72 - Common-Drain Amplifier VDD 6 0 DC 10 VS 1 0 AC 1 RS 1 2 2K C1 2 3 4.7UF R1 3 0 1.5MEG R2 6 3 2.2MEG M1 6 3 4 4 NFET R4 4 0 12K C3 4 5 0.1UF R7 5 0 100K .MODEL NFET NMOS VTO=2.10 KP=0.356MA CGSO=30NF CGDO=6NF .OP .AC DEC 100 1 500MEG .PRINT AC VM(5) VP(5) .END Results: Amid = 0.740, fL = 15.5 Hz, fH = 195MHz - Note that there is peaking in the response.